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From: <pbhagavatula@marvell.com>
To: <jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>,
	"Shijith Thotton" <sthotton@marvell.com>
Cc: <dev@dpdk.org>
Subject: [PATCH v3 2/3] event/cnxk: disable default wait time for dequeue
Date: Thu, 10 Feb 2022 15:49:39 +0530	[thread overview]
Message-ID: <20220210101940.1669-2-pbhagavatula@marvell.com> (raw)
In-Reply-To: <20220210101940.1669-1-pbhagavatula@marvell.com>

From: Pavan Nikhilesh <pbhagavatula@marvell.com>

Setting WAITW bit enables default min dequeue timeout of 1us.
Avoid the min dequeue timeout by setting WAITW only when dequeue_timeout
is configured.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---
 drivers/event/cnxk/cn10k_eventdev.c |  8 +++++--
 drivers/event/cnxk/cn9k_eventdev.c  |  9 ++++++-
 drivers/event/cnxk/cn9k_worker.h    | 37 +++++++++++++----------------
 drivers/event/cnxk/cnxk_eventdev.c  |  2 +-
 drivers/event/cnxk/cnxk_eventdev.h  |  2 ++
 5 files changed, 34 insertions(+), 24 deletions(-)

diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c
index 97a88feb13..26d65e3568 100644
--- a/drivers/event/cnxk/cn10k_eventdev.c
+++ b/drivers/event/cnxk/cn10k_eventdev.c
@@ -15,7 +15,10 @@
 static uint32_t
 cn10k_sso_gw_mode_wdata(struct cnxk_sso_evdev *dev)
 {
-	uint32_t wdata = BIT(16) | 1;
+	uint32_t wdata = 1;
+
+	if (dev->deq_tmo_ns)
+		wdata |= BIT(16);
 
 	switch (dev->gw_mode) {
 	case CN10K_GW_MODE_NONE:
@@ -88,7 +91,8 @@ cn10k_sso_hws_setup(void *arg, void *hws, uintptr_t grp_base)
 	ws->xaq_lmt = dev->xaq_lmt;
 
 	/* Set get_work timeout for HWS */
-	val = NSEC2USEC(dev->deq_tmo_ns) - 1;
+	val = NSEC2USEC(dev->deq_tmo_ns);
+	val = val ? val - 1 : 0;
 	plt_write64(val, ws->base + SSOW_LF_GWS_NW_TIM);
 }
 
diff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c
index f8652d4fbc..6d3d03c97c 100644
--- a/drivers/event/cnxk/cn9k_eventdev.c
+++ b/drivers/event/cnxk/cn9k_eventdev.c
@@ -72,7 +72,8 @@ cn9k_sso_hws_setup(void *arg, void *hws, uintptr_t grp_base)
 	uint64_t val;
 
 	/* Set get_work tmo for HWS */
-	val = dev->deq_tmo_ns ? NSEC2USEC(dev->deq_tmo_ns) - 1 : 0;
+	val = NSEC2USEC(dev->deq_tmo_ns);
+	val = val ? val - 1 : 0;
 	if (dev->dual_ws) {
 		dws = hws;
 		dws->grp_base = grp_base;
@@ -677,6 +678,9 @@ cn9k_sso_init_hws_mem(void *arg, uint8_t port_id)
 		dws->hws_id = port_id;
 		dws->swtag_req = 0;
 		dws->vws = 0;
+		if (dev->deq_tmo_ns)
+			dws->gw_wdata = BIT_ULL(16);
+		dws->gw_wdata |= 1;
 
 		data = dws;
 	} else {
@@ -695,6 +699,9 @@ cn9k_sso_init_hws_mem(void *arg, uint8_t port_id)
 		ws->base = roc_sso_hws_base_get(&dev->sso, port_id);
 		ws->hws_id = port_id;
 		ws->swtag_req = 0;
+		if (dev->deq_tmo_ns)
+			ws->gw_wdata = BIT_ULL(16);
+		ws->gw_wdata |= 1;
 
 		data = ws;
 	}
diff --git a/drivers/event/cnxk/cn9k_worker.h b/drivers/event/cnxk/cn9k_worker.h
index 8455272005..79374b8d95 100644
--- a/drivers/event/cnxk/cn9k_worker.h
+++ b/drivers/event/cnxk/cn9k_worker.h
@@ -149,10 +149,8 @@ cn9k_wqe_to_mbuf(uint64_t wqe, const uint64_t mbuf, uint8_t port_id,
 static __rte_always_inline uint16_t
 cn9k_sso_hws_dual_get_work(uint64_t base, uint64_t pair_base,
 			   struct rte_event *ev, const uint32_t flags,
-			   const void *const lookup_mem,
-			   struct cnxk_timesync_info *const tstamp)
+			   struct cn9k_sso_hws_dual *dws)
 {
-	const uint64_t set_gw = BIT_ULL(16) | 1;
 	union {
 		__uint128_t get_work;
 		uint64_t u64[2];
@@ -161,7 +159,7 @@ cn9k_sso_hws_dual_get_work(uint64_t base, uint64_t pair_base,
 	uint64_t mbuf;
 
 	if (flags & NIX_RX_OFFLOAD_PTYPE_F)
-		rte_prefetch_non_temporal(lookup_mem);
+		rte_prefetch_non_temporal(dws->lookup_mem);
 #ifdef RTE_ARCH_ARM64
 	asm volatile(PLT_CPU_FEATURE_PREAMBLE
 		     "rty%=:					\n"
@@ -175,14 +173,14 @@ cn9k_sso_hws_dual_get_work(uint64_t base, uint64_t pair_base,
 		     : [tag] "=&r"(gw.u64[0]), [wqp] "=&r"(gw.u64[1]),
 		       [mbuf] "=&r"(mbuf)
 		     : [tag_loc] "r"(base + SSOW_LF_GWS_TAG),
-		       [wqp_loc] "r"(base + SSOW_LF_GWS_WQP), [gw] "r"(set_gw),
+		       [wqp_loc] "r"(base + SSOW_LF_GWS_WQP), [gw] "r"(dws->gw_wdata),
 		       [pong] "r"(pair_base + SSOW_LF_GWS_OP_GET_WORK0));
 #else
 	gw.u64[0] = plt_read64(base + SSOW_LF_GWS_TAG);
 	while ((BIT_ULL(63)) & gw.u64[0])
 		gw.u64[0] = plt_read64(base + SSOW_LF_GWS_TAG);
 	gw.u64[1] = plt_read64(base + SSOW_LF_GWS_WQP);
-	plt_write64(set_gw, pair_base + SSOW_LF_GWS_OP_GET_WORK0);
+	plt_write64(dws->gw_wdata, pair_base + SSOW_LF_GWS_OP_GET_WORK0);
 	mbuf = (uint64_t)((char *)gw.u64[1] - sizeof(struct rte_mbuf));
 #endif
 
@@ -202,12 +200,13 @@ cn9k_sso_hws_dual_get_work(uint64_t base, uint64_t pair_base,
 			gw.u64[0] = CNXK_CLR_SUB_EVENT(gw.u64[0]);
 			cn9k_wqe_to_mbuf(gw.u64[1], mbuf, port,
 					 gw.u64[0] & 0xFFFFF, flags,
-					 lookup_mem);
+					 dws->lookup_mem);
 			/* Extracting tstamp, if PTP enabled*/
 			tstamp_ptr = *(uint64_t *)(((struct nix_wqe_hdr_s *)
 							    gw.u64[1]) +
 						   CNXK_SSO_WQE_SG_PTR);
-			cnxk_nix_mbuf_to_tstamp((struct rte_mbuf *)mbuf, tstamp,
+			cnxk_nix_mbuf_to_tstamp((struct rte_mbuf *)mbuf,
+						dws->tstamp,
 						flags & NIX_RX_OFFLOAD_TSTAMP_F,
 						flags & NIX_RX_MULTI_SEG_F,
 						(uint64_t *)tstamp_ptr);
@@ -232,9 +231,7 @@ cn9k_sso_hws_get_work(struct cn9k_sso_hws *ws, struct rte_event *ev,
 	uint64_t tstamp_ptr;
 	uint64_t mbuf;
 
-	plt_write64(BIT_ULL(16) | /* wait for work. */
-			    1,	  /* Use Mask set 0. */
-		    ws->base + SSOW_LF_GWS_OP_GET_WORK0);
+	plt_write64(ws->gw_wdata, ws->base + SSOW_LF_GWS_OP_GET_WORK0);
 
 	if (flags & NIX_RX_OFFLOAD_PTYPE_F)
 		rte_prefetch_non_temporal(lookup_mem);
@@ -529,9 +526,9 @@ NIX_RX_FASTPATH_MODES
 						SSOW_LF_GWS_TAG);              \
 			return 1;                                              \
 		}                                                              \
-		gw = cn9k_sso_hws_dual_get_work(                               \
-			dws->base[dws->vws], dws->base[!dws->vws], ev, flags,  \
-			dws->lookup_mem, dws->tstamp);                         \
+		gw = cn9k_sso_hws_dual_get_work(dws->base[dws->vws],           \
+						dws->base[!dws->vws], ev,      \
+						flags, dws);                   \
 		dws->vws = !dws->vws;                                          \
 		return gw;                                                     \
 	}
@@ -554,14 +551,14 @@ NIX_RX_FASTPATH_MODES
 						SSOW_LF_GWS_TAG);              \
 			return ret;                                            \
 		}                                                              \
-		ret = cn9k_sso_hws_dual_get_work(                              \
-			dws->base[dws->vws], dws->base[!dws->vws], ev, flags,  \
-			dws->lookup_mem, dws->tstamp);                         \
+		ret = cn9k_sso_hws_dual_get_work(dws->base[dws->vws],          \
+						 dws->base[!dws->vws], ev,     \
+						 flags, dws);                  \
 		dws->vws = !dws->vws;                                          \
 		for (iter = 1; iter < timeout_ticks && (ret == 0); iter++) {   \
-			ret = cn9k_sso_hws_dual_get_work(                      \
-				dws->base[dws->vws], dws->base[!dws->vws], ev, \
-				flags, dws->lookup_mem, dws->tstamp);          \
+			ret = cn9k_sso_hws_dual_get_work(dws->base[dws->vws],  \
+							 dws->base[!dws->vws], \
+							 ev, flags, dws);      \
 			dws->vws = !dws->vws;                                  \
 		}                                                              \
 		return ret;                                                    \
diff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c
index 6ad4e23e2b..be021d86c9 100644
--- a/drivers/event/cnxk/cnxk_eventdev.c
+++ b/drivers/event/cnxk/cnxk_eventdev.c
@@ -610,7 +610,7 @@ cnxk_sso_init(struct rte_eventdev *event_dev)
 	}
 
 	dev->is_timeout_deq = 0;
-	dev->min_dequeue_timeout_ns = USEC2NSEC(1);
+	dev->min_dequeue_timeout_ns = 0;
 	dev->max_dequeue_timeout_ns = USEC2NSEC(0x3FF);
 	dev->max_num_events = -1;
 	dev->nb_event_queues = 0;
diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h
index ab58508590..e3b5ffa7eb 100644
--- a/drivers/event/cnxk/cnxk_eventdev.h
+++ b/drivers/event/cnxk/cnxk_eventdev.h
@@ -144,6 +144,7 @@ struct cn10k_sso_hws {
 /* Event port a.k.a GWS */
 struct cn9k_sso_hws {
 	uint64_t base;
+	uint64_t gw_wdata;
 	/* PTP timestamp */
 	struct cnxk_timesync_info *tstamp;
 	void *lookup_mem;
@@ -160,6 +161,7 @@ struct cn9k_sso_hws {
 
 struct cn9k_sso_hws_dual {
 	uint64_t base[2]; /* Ping and Pong */
+	uint64_t gw_wdata;
 	/* PTP timestamp */
 	struct cnxk_timesync_info *tstamp;
 	void *lookup_mem;
-- 
2.17.1


  reply	other threads:[~2022-02-10 10:19 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-19  7:13 [PATCH v2 1/4] net/cnxk: avoid command copy from Tx queue pbhagavatula
2022-01-19  7:13 ` [PATCH v2 2/4] event/cnxk: store and reuse workslot status pbhagavatula
2022-01-19  7:13 ` [PATCH v2 3/4] event/cnxk: disable default wait time for dequeue pbhagavatula
2022-01-19  7:13 ` [PATCH v2 4/4] net/cnxk: improve Rx performance pbhagavatula
2022-02-07 14:03 ` [PATCH v2 1/4] net/cnxk: avoid command copy from Tx queue Jerin Jacob
2022-02-10 10:13 ` [PATCH v3] " pbhagavatula
2022-02-10 10:19   ` Jerin Jacob
2022-02-10 13:15   ` [PATCH v4] " pbhagavatula
2022-02-11 10:27     ` Jerin Jacob
2022-02-10 10:19 ` [PATCH v3 1/3] event/cnxk: store and reuse workslot status pbhagavatula
2022-02-10 10:19   ` pbhagavatula [this message]
2022-02-10 10:19   ` [PATCH v3 3/3] net/cnxk: improve Rx performance pbhagavatula
2022-02-10 13:20   ` [PATCH v4 1/3] event/cnxk: store and reuse workslot status pbhagavatula
2022-02-10 13:20     ` [PATCH v4 2/3] event/cnxk: disable default wait time for dequeue pbhagavatula
2022-02-10 13:20     ` [PATCH v4 3/3] event/cnxk: improve Rx performance pbhagavatula
2022-02-14  9:29     ` [PATCH v4 1/3] event/cnxk: store and reuse workslot status Jerin Jacob

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