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envelope-from=prvs=03511bb56=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Anup Patel The AIA specification defines IMSIC interface CSRs for easy access to the per-HART IMSIC registers without using indirect xiselect and xireg CSRs. This patch implements the AIA IMSIC interface CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Frank Chang Message-id: 20220204174700.534953-16-anup@brainfault.org Signed-off-by: Alistair Francis --- target/riscv/csr.c | 203 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 203 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index a186b31fcf..fe2c8dd40e 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -942,6 +942,16 @@ static int aia_xlate_vs_csrno(CPURISCVState *env, in= t csrno) return CSR_VSISELECT; case CSR_SIREG: return CSR_VSIREG; + case CSR_SSETEIPNUM: + return CSR_VSSETEIPNUM; + case CSR_SCLREIPNUM: + return CSR_VSCLREIPNUM; + case CSR_SSETEIENUM: + return CSR_VSSETEIENUM; + case CSR_SCLREIENUM: + return CSR_VSCLREIENUM; + case CSR_STOPEI: + return CSR_VSTOPEI; default: return csrno; }; @@ -1094,6 +1104,178 @@ done: return RISCV_EXCP_NONE; } =20 +static int rmw_xsetclreinum(CPURISCVState *env, int csrno, target_ulong = *val, + target_ulong new_val, target_ulong wr_mask) +{ + int ret =3D -EINVAL; + bool set, pend, virt; + target_ulong priv, isel, vgein, xlen, nval, wmask; + + /* Translate CSR number for VS-mode */ + csrno =3D aia_xlate_vs_csrno(env, csrno); + + /* Decode register details from CSR number */ + virt =3D set =3D pend =3D false; + switch (csrno) { + case CSR_MSETEIPNUM: + priv =3D PRV_M; + set =3D true; + pend =3D true; + break; + case CSR_MCLREIPNUM: + priv =3D PRV_M; + pend =3D true; + break; + case CSR_MSETEIENUM: + priv =3D PRV_M; + set =3D true; + break; + case CSR_MCLREIENUM: + priv =3D PRV_M; + break; + case CSR_SSETEIPNUM: + priv =3D PRV_S; + set =3D true; + pend =3D true; + break; + case CSR_SCLREIPNUM: + priv =3D PRV_S; + pend =3D true; + break; + case CSR_SSETEIENUM: + priv =3D PRV_S; + set =3D true; + break; + case CSR_SCLREIENUM: + priv =3D PRV_S; + break; + case CSR_VSSETEIPNUM: + priv =3D PRV_S; + virt =3D true; + set =3D true; + pend =3D true; + break; + case CSR_VSCLREIPNUM: + priv =3D PRV_S; + virt =3D true; + pend =3D true; + break; + case CSR_VSSETEIENUM: + priv =3D PRV_S; + virt =3D true; + set =3D true; + break; + case CSR_VSCLREIENUM: + priv =3D PRV_S; + virt =3D true; + break; + default: + goto done; + }; + + /* IMSIC CSRs only available when machine implements IMSIC. */ + if (!env->aia_ireg_rmw_fn[priv]) { + goto done; + } + + /* Find the selected guest interrupt file */ + vgein =3D (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0; + + /* Selected guest interrupt file should be valid */ + if (virt && (!vgein || env->geilen < vgein)) { + goto done; + } + + /* Set/Clear CSRs always read zero */ + if (val) { + *val =3D 0; + } + + if (wr_mask) { + /* Get interrupt number */ + new_val &=3D wr_mask; + + /* Find target interrupt pending/enable register */ + xlen =3D riscv_cpu_mxl_bits(env); + isel =3D (new_val / xlen); + isel *=3D (xlen / IMSIC_EIPx_BITS); + isel +=3D (pend) ? ISELECT_IMSIC_EIP0 : ISELECT_IMSIC_EIE0; + + /* Find the interrupt bit to be set/clear */ + wmask =3D ((target_ulong)1) << (new_val % xlen); + nval =3D (set) ? wmask : 0; + + /* Call machine specific IMSIC register emulation */ + ret =3D env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv= ], + AIA_MAKE_IREG(isel, priv, virt, + vgein, xlen), + NULL, nval, wmask); + } else { + ret =3D 0; + } + +done: + if (ret) { + return (riscv_cpu_virt_enabled(env) && virt) ? + RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_IN= ST; + } + return RISCV_EXCP_NONE; +} + +static int rmw_xtopei(CPURISCVState *env, int csrno, target_ulong *val, + target_ulong new_val, target_ulong wr_mask) +{ + bool virt; + int ret =3D -EINVAL; + target_ulong priv, vgein; + + /* Translate CSR number for VS-mode */ + csrno =3D aia_xlate_vs_csrno(env, csrno); + + /* Decode register details from CSR number */ + virt =3D false; + switch (csrno) { + case CSR_MTOPEI: + priv =3D PRV_M; + break; + case CSR_STOPEI: + priv =3D PRV_S; + break; + case CSR_VSTOPEI: + priv =3D PRV_S; + virt =3D true; + break; + default: + goto done; + }; + + /* IMSIC CSRs only available when machine implements IMSIC. */ + if (!env->aia_ireg_rmw_fn[priv]) { + goto done; + } + + /* Find the selected guest interrupt file */ + vgein =3D (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0; + + /* Selected guest interrupt file should be valid */ + if (virt && (!vgein || env->geilen < vgein)) { + goto done; + } + + /* Call machine specific IMSIC register emulation for TOPEI */ + ret =3D env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv], + AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI, priv, virt, vgein= , + riscv_cpu_mxl_bits(env)), + val, new_val, wr_mask); + +done: + if (ret) { + return (riscv_cpu_virt_enabled(env) && virt) ? + RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_IN= ST; + } + return RISCV_EXCP_NONE; +} + static RISCVException read_mtvec(CPURISCVState *env, int csrno, target_ulong *val) { @@ -2930,6 +3112,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { /* Machine-Level Interrupts (AIA) */ [CSR_MTOPI] =3D { "mtopi", aia_any, read_mtopi }, =20 + /* Machine-Level IMSIC Interface (AIA) */ + [CSR_MSETEIPNUM] =3D { "mseteipnum", aia_any, NULL, NULL, rmw_xsetcl= reinum }, + [CSR_MCLREIPNUM] =3D { "mclreipnum", aia_any, NULL, NULL, rmw_xsetcl= reinum }, + [CSR_MSETEIENUM] =3D { "mseteienum", aia_any, NULL, NULL, rmw_xsetcl= reinum }, + [CSR_MCLREIENUM] =3D { "mclreienum", aia_any, NULL, NULL, rmw_xsetcl= reinum }, + [CSR_MTOPEI] =3D { "mtopei", aia_any, NULL, NULL, rmw_xtopei= }, + /* Virtual Interrupts for Supervisor Level (AIA) */ [CSR_MVIEN] =3D { "mvien", aia_any, read_zero, write_ignore }, [CSR_MVIP] =3D { "mvip", aia_any, read_zero, write_ignore }, @@ -2966,6 +3155,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { /* Supervisor-Level Interrupts (AIA) */ [CSR_STOPI] =3D { "stopi", aia_smode, read_stopi }, =20 + /* Supervisor-Level IMSIC Interface (AIA) */ + [CSR_SSETEIPNUM] =3D { "sseteipnum", aia_smode, NULL, NULL, rmw_xset= clreinum }, + [CSR_SCLREIPNUM] =3D { "sclreipnum", aia_smode, NULL, NULL, rmw_xset= clreinum }, + [CSR_SSETEIENUM] =3D { "sseteienum", aia_smode, NULL, NULL, rmw_xset= clreinum }, + [CSR_SCLREIENUM] =3D { "sclreienum", aia_smode, NULL, NULL, rmw_xset= clreinum }, + [CSR_STOPEI] =3D { "stopei", aia_smode, NULL, NULL, rmw_xtop= ei }, + /* Supervisor-Level High-Half CSRs (AIA) */ [CSR_SIEH] =3D { "sieh", aia_smode32, NULL, NULL, rmw_sieh }= , [CSR_SIPH] =3D { "siph", aia_smode32, NULL, NULL, rmw_siph }= , @@ -3013,6 +3209,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { /* VS-Level Interrupts (H-extension with AIA) */ [CSR_VSTOPI] =3D { "vstopi", aia_hmode, read_vstopi }, =20 + /* VS-Level IMSIC Interface (H-extension with AIA) */ + [CSR_VSSETEIPNUM] =3D { "vsseteipnum", aia_hmode, NULL, NULL, rmw_xs= etclreinum }, + [CSR_VSCLREIPNUM] =3D { "vsclreipnum", aia_hmode, NULL, NULL, rmw_xs= etclreinum }, + [CSR_VSSETEIENUM] =3D { "vsseteienum", aia_hmode, NULL, NULL, rmw_xs= etclreinum }, + [CSR_VSCLREIENUM] =3D { "vsclreienum", aia_hmode, NULL, NULL, rmw_xs= etclreinum }, + [CSR_VSTOPEI] =3D { "vstopei", aia_hmode, NULL, NULL, rmw_xt= opei }, + /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ [CSR_HIDELEGH] =3D { "hidelegh", aia_hmode32, NULL, NULL, rmw_= hidelegh }, [CSR_HVIENH] =3D { "hvienh", aia_hmode32, read_zero, write= _ignore }, --=20 2.34.1