On 09.02.2022 17:38:03, Ulrich Hecht wrote:
> Adds support for the CANFD IP variant in the V3U SoC.
> 
> Differences to controllers in other SoCs are limited to an increase in
> the number of channels from two to eight, an absence of dedicated
> registers for "classic" CAN mode, and a number of differences in magic
> numbers (register offsets and layouts).
> 
> Inspired by BSP patch by Kazuya Mizuguchi.
> 
> Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
> ---
>  drivers/net/can/rcar/rcar_canfd.c | 219 ++++++++++++++++++++----------
>  1 file changed, 146 insertions(+), 73 deletions(-)
> 
> diff --git a/drivers/net/can/rcar/rcar_canfd.c b/drivers/net/can/rcar/rcar_canfd.c
> index b7dc1c32875f..3ad3a6f6a1dd 100644
> --- a/drivers/net/can/rcar/rcar_canfd.c
> +++ b/drivers/net/can/rcar/rcar_canfd.c
> @@ -44,6 +44,7 @@
>  enum rcanfd_chip_id {
>  	RENESAS_RCAR_GEN3 = 0,
>  	RENESAS_RZG2L,
> +	RENESAS_R8A779A0,
>  };
>  
>  /* Global register bits */
> @@ -79,6 +80,7 @@ enum rcanfd_chip_id {
>  #define RCANFD_GSTS_GNOPM		(BIT(0) | BIT(1) | BIT(2) | BIT(3))
>  
>  /* RSCFDnCFDGERFL / RSCFDnGERFL */
> +#define RCANFD_GERFL_EEF0_7		GENMASK(23, 16)
>  #define RCANFD_GERFL_EEF1		BIT(17)
>  #define RCANFD_GERFL_EEF0		BIT(16)
>  #define RCANFD_GERFL_CMPOF		BIT(3)	/* CAN FD only */
> @@ -86,20 +88,24 @@ enum rcanfd_chip_id {
>  #define RCANFD_GERFL_MES		BIT(1)
>  #define RCANFD_GERFL_DEF		BIT(0)
>  
> -#define RCANFD_GERFL_ERR(gpriv, x)	((x) & (RCANFD_GERFL_EEF1 |\
> -					RCANFD_GERFL_EEF0 | RCANFD_GERFL_MES |\
> -					(gpriv->fdmode ?\
> -					 RCANFD_GERFL_CMPOF : 0)))
> +#define RCANFD_GERFL_ERR(x)		((x) & (reg_v3u(gpriv, RCANFD_GERFL_EEF0_7, \
> +					RCANFD_GERFL_EEF0 | RCANFD_GERFL_EEF1) | \
> +					RCANFD_GERFL_MES | ((gpriv)->fdmode ? \
> +					RCANFD_GERFL_CMPOF : 0)))

The macros are relying on gpriv being in the scope. Please make them
arguments of the macros.

Marc

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