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[213.175.37.10]) by smtp.gmail.com with ESMTPSA id d25sm10600307ejz.4.2022.02.14.05.19.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Feb 2022 05:19:32 -0800 (PST) Date: Mon, 14 Feb 2022 14:19:31 +0100 From: Igor Mammedov To: Joao Martins Subject: Re: [PATCH RFCv2 1/4] hw/i386: add 4g boundary start to X86MachineState Message-ID: <20220214141931.61b87d43@redhat.com> In-Reply-To: <20220207202422.31582-2-joao.m.martins@oracle.com> References: <20220207202422.31582-1-joao.m.martins@oracle.com> <20220207202422.31582-2-joao.m.martins@oracle.com> X-Mailer: Claws Mail 4.0.0 (GTK+ 3.24.31; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=imammedo@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=imammedo@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -28 X-Spam_score: -2.9 X-Spam_bar: -- X-Spam_report: (-2.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.083, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , "Michael S . Tsirkin" , Richard Henderson , qemu-devel@nongnu.org, Daniel Jordan , David Edmondson , Alex Williamson , Suravee Suthikulpanit , Ani Sinha , Paolo Bonzini Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Mon, 7 Feb 2022 20:24:19 +0000 Joao Martins wrote: > Rather than hardcoding the 4G boundary everywhere, introduce a > X86MachineState property @above_4g_mem_start and use it > accordingly. > > This is in preparation for relocating ram-above-4g to be > dynamically start at 1T on AMD platforms. > > Signed-off-by: Joao Martins > --- > hw/i386/acpi-build.c | 2 +- > hw/i386/pc.c | 9 +++++---- > hw/i386/sgx.c | 2 +- > hw/i386/x86.c | 1 + > include/hw/i386/x86.h | 3 +++ > 5 files changed, 11 insertions(+), 6 deletions(-) > > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c > index ebd47aa26fd8..4bf54ccdab91 100644 > --- a/hw/i386/acpi-build.c > +++ b/hw/i386/acpi-build.c > @@ -2063,7 +2063,7 @@ build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) > build_srat_memory(table_data, mem_base, mem_len, i - 1, > MEM_AFFINITY_ENABLED); > } > - mem_base = 1ULL << 32; > + mem_base = x86ms->above_4g_mem_start; > mem_len = next_base - x86ms->below_4g_mem_size; > next_base = mem_base + mem_len; > } > diff --git a/hw/i386/pc.c b/hw/i386/pc.c > index c8696ac01e85..7de0e87f4a3f 100644 > --- a/hw/i386/pc.c > +++ b/hw/i386/pc.c > @@ -837,9 +837,10 @@ void pc_memory_init(PCMachineState *pcms, > machine->ram, > x86ms->below_4g_mem_size, > x86ms->above_4g_mem_size); > - memory_region_add_subregion(system_memory, 0x100000000ULL, > + memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start, > ram_above_4g); > - e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM); > + e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size, > + E820_RAM); > } > > if (pcms->sgx_epc.size != 0) { > @@ -880,7 +881,7 @@ void pc_memory_init(PCMachineState *pcms, > machine->device_memory->base = sgx_epc_above_4g_end(&pcms->sgx_epc); > } else { > machine->device_memory->base = > - 0x100000000ULL + x86ms->above_4g_mem_size; > + x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; > } > > machine->device_memory->base = > @@ -972,7 +973,7 @@ uint64_t pc_pci_hole64_start(void) > } else if (pcms->sgx_epc.size != 0) { > hole64_start = sgx_epc_above_4g_end(&pcms->sgx_epc); > } else { > - hole64_start = 0x100000000ULL + x86ms->above_4g_mem_size; > + hole64_start = x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; > } > > return ROUND_UP(hole64_start, 1 * GiB); > diff --git a/hw/i386/sgx.c b/hw/i386/sgx.c > index a2b318dd9387..164ee1ddb8de 100644 > --- a/hw/i386/sgx.c > +++ b/hw/i386/sgx.c > @@ -295,7 +295,7 @@ void pc_machine_init_sgx_epc(PCMachineState *pcms) > return; > } > > - sgx_epc->base = 0x100000000ULL + x86ms->above_4g_mem_size; > + sgx_epc->base = x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; > > memory_region_init(&sgx_epc->mr, OBJECT(pcms), "sgx-epc", UINT64_MAX); > memory_region_add_subregion(get_system_memory(), sgx_epc->base, > diff --git a/hw/i386/x86.c b/hw/i386/x86.c > index b84840a1bb99..912e96718ee8 100644 > --- a/hw/i386/x86.c > +++ b/hw/i386/x86.c > @@ -1319,6 +1319,7 @@ static void x86_machine_initfn(Object *obj) > x86ms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); > x86ms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); > x86ms->bus_lock_ratelimit = 0; > + x86ms->above_4g_mem_start = 0x100000000ULL; > } > > static void x86_machine_class_init(ObjectClass *oc, void *data) > diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h > index a145a303703f..2de7ec046b75 100644 > --- a/include/hw/i386/x86.h > +++ b/include/hw/i386/x86.h > @@ -58,6 +58,9 @@ struct X86MachineState { > /* RAM information (sizes, addresses, configuration): */ > ram_addr_t below_4g_mem_size, above_4g_mem_size; > > + /* RAM information when there's a hole in 1Tb */ s/^^^/GPA of the part of initial RAM above 4G/ or something like that, it doesn't have anything to do with hole at 1Tb on some hosts. > + ram_addr_t above_4g_mem_start; > + > /* CPU and apic information: */ > bool apic_xrupt_override; > unsigned pci_irq_mask;