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From: Will Deacon <will@kernel.org>
To: Mark Brown <broonie@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
	Joey Gouly <joey.gouly@arm.com>,
	Branislav Rankov <branislav.rankov@arm.com>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v1 1/4] arm64/mte: Document ABI for asymmetric mode
Date: Tue, 15 Feb 2022 18:14:23 +0000	[thread overview]
Message-ID: <20220215181422.GA8748@willie-the-truck> (raw)
In-Reply-To: <20220127195712.748150-2-broonie@kernel.org>

On Thu, Jan 27, 2022 at 07:57:09PM +0000, Mark Brown wrote:
> MTE3 adds a new mode which is synchronous for writes but asynchronous for
> reads. Document the userspace ABI for this feature, we call the new mode
> ASYMM and add a new prctl flag and mte_tcf_preferred value for it.
> 
> Signed-off-by: Mark Brown <broonie@kernel.org>
> ---
>  Documentation/arm64/memory-tagging-extension.rst | 12 +++++++-----
>  1 file changed, 7 insertions(+), 5 deletions(-)
> 
> diff --git a/Documentation/arm64/memory-tagging-extension.rst b/Documentation/arm64/memory-tagging-extension.rst
> index 7b99c8f428eb..5218b838d062 100644
> --- a/Documentation/arm64/memory-tagging-extension.rst
> +++ b/Documentation/arm64/memory-tagging-extension.rst
> @@ -76,6 +76,9 @@ configurable behaviours:
>    with ``.si_code = SEGV_MTEAERR`` and ``.si_addr = 0`` (the faulting
>    address is unknown).
>  
> +- *Asymmetric* - Reads are handled as for synchronous mode while writes
> +  are handled as for asynchronous mode.
> +
>  The user can select the above modes, per thread, using the
>  ``prctl(PR_SET_TAGGED_ADDR_CTRL, flags, 0, 0, 0)`` system call where ``flags``
>  contains any number of the following values in the ``PR_MTE_TCF_MASK``
> @@ -85,6 +88,7 @@ bit-field:
>                           (ignored if combined with other options)
>  - ``PR_MTE_TCF_SYNC``  - *Synchronous* tag check fault mode
>  - ``PR_MTE_TCF_ASYNC`` - *Asynchronous* tag check fault mode
> +- ``PR_MTE_TCF_ASYMM`` - *Asymmetric* tag check fault mode
>  
>  If no modes are specified, tag check faults are ignored. If a single
>  mode is specified, the program will run in that mode. If multiple
> @@ -139,16 +143,14 @@ tag checking mode as the CPU's preferred tag checking mode.
>  
>  The preferred tag checking mode for each CPU is controlled by
>  ``/sys/devices/system/cpu/cpu<N>/mte_tcf_preferred``, to which a
> -privileged user may write the value ``async`` or ``sync``.  The default
> -preferred mode for each CPU is ``async``.
> +privileged user may write the value ``async``, ``sync`` or ``asymm``.  The
> +default preferred mode for each CPU is ``async``.
>  
>  To allow a program to potentially run in the CPU's preferred tag
>  checking mode, the user program may set multiple tag check fault mode
>  bits in the ``flags`` argument to the ``prctl(PR_SET_TAGGED_ADDR_CTRL,
>  flags, 0, 0, 0)`` system call. If the CPU's preferred tag checking
> -mode is in the task's set of provided tag checking modes (this will
> -always be the case at present because the kernel only supports two
> -tag checking modes, but future kernels may support more modes), that
> +mode is in the task's set of provided tag checking modes, that
>  mode will be selected. Otherwise, one of the modes in the task's mode
>  set will be selected in a currently unspecified manner.

I think it's time we specified the "unspecified manner" now that we have
three options.

Will

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  parent reply	other threads:[~2022-02-15 18:15 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-27 19:57 [PATCH v1 0/4] arm64/mte: Asymmetric MTE support in userspace Mark Brown
2022-01-27 19:57 ` [PATCH v1 1/4] arm64/mte: Document ABI for asymmetric mode Mark Brown
2022-01-28 16:43   ` Catalin Marinas
2022-01-28 17:23     ` Mark Brown
2022-01-28 16:55   ` Vincenzo Frascino
2022-02-15 18:14   ` Will Deacon [this message]
2022-02-16 16:36     ` Mark Brown
2022-02-16 17:06       ` Will Deacon
2022-01-27 19:57 ` [PATCH v1 2/4] arm64/mte: Add a little bit of documentation for mte_update_sctlr_user() Mark Brown
2022-01-28 16:45   ` Catalin Marinas
2022-01-28 16:57   ` Vincenzo Frascino
2022-01-27 19:57 ` [PATCH v1 3/4] arm64/mte: Add hwcap for asymmetric mode Mark Brown
2022-01-28 16:51   ` Catalin Marinas
2022-01-28 17:00   ` Vincenzo Frascino
2022-01-27 19:57 ` [PATCH v1 4/4] arm64/mte: Add userspace interface for enabling " Mark Brown
2022-01-28 17:12   ` Vincenzo Frascino
2022-01-28 17:15   ` Catalin Marinas
2022-03-02  0:52   ` Evgenii Stepanov
2022-03-02 11:44     ` Catalin Marinas
2022-03-02 13:10       ` Mark Brown
2022-03-02 18:44         ` Evgenii Stepanov
2022-03-02 19:33           ` Mark Brown
2022-03-02 20:58             ` Evgenii Stepanov
2022-03-03 10:34               ` Catalin Marinas
2022-03-03 15:44                 ` Mark Brown
2022-03-03 22:47                   ` Evgenii Stepanov
2022-03-04 21:09                 ` Peter Collingbourne
2022-03-07 15:36                   ` Catalin Marinas
2022-03-07 19:10                     ` Mark Brown
2022-03-07 20:55                       ` Peter Collingbourne
2022-03-08 13:34                         ` Mark Brown
2022-03-07 20:55                     ` Peter Collingbourne
2022-03-08 18:26                       ` Catalin Marinas
2022-02-10 21:43 ` [PATCH v1 0/4] arm64/mte: Asymmetric MTE support in userspace Branislav Rankov

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