From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 86BBEC433FE for ; Tue, 15 Feb 2022 23:29:01 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 082D710E577; Tue, 15 Feb 2022 23:29:00 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 81E2F10E2D9; Tue, 15 Feb 2022 23:28:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644967738; x=1676503738; h=date:from:to:subject:message-id:references:mime-version: content-transfer-encoding:in-reply-to; bh=PuOlIBLnmV0UGsziClzfYD4ZKWpxWUaUI/U5AU60124=; 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charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20220208104524.2516209-9-lucas.demarchi@intel.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Tue, Feb 08, 2022 at 02:45:14AM -0800, Lucas De Marchi wrote: > Use iosys_map to read fields from the dma_blob so access to IO and > system memory is abstracted away. > > Cc: Matt Roper > Cc: Thomas Hellström > Cc: Daniel Vetter > Cc: John Harrison > Cc: Matthew Brost > Cc: Daniele Ceraolo Spurio Reviewed-by: Matt Atwood > Signed-off-by: Lucas De Marchi > --- > drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 14 ++++++-------- > drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h | 3 ++- > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 17 ++++++++++------- > 3 files changed, 18 insertions(+), 16 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c > index 6a34ab38b45f..383c5994d4ef 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c > @@ -695,18 +695,16 @@ void intel_guc_ads_reset(struct intel_guc *guc) > > u32 intel_guc_engine_usage_offset(struct intel_guc *guc) > { > - struct __guc_ads_blob *blob = guc->ads_blob; > - u32 base = intel_guc_ggtt_offset(guc, guc->ads_vma); > - u32 offset = base + ptr_offset(blob, engine_usage); > - > - return offset; > + return intel_guc_ggtt_offset(guc, guc->ads_vma) + > + offsetof(struct __guc_ads_blob, engine_usage); > } > > -struct guc_engine_usage_record *intel_guc_engine_usage(struct intel_engine_cs *engine) > +struct iosys_map intel_guc_engine_usage_record_map(struct intel_engine_cs *engine) > { > struct intel_guc *guc = &engine->gt->uc.guc; > - struct __guc_ads_blob *blob = guc->ads_blob; > u8 guc_class = engine_class_to_guc_class(engine->class); > + size_t offset = offsetof(struct __guc_ads_blob, > + engine_usage.engines[guc_class][ilog2(engine->logical_mask)]); > > - return &blob->engine_usage.engines[guc_class][ilog2(engine->logical_mask)]; > + return IOSYS_MAP_INIT_OFFSET(&guc->ads_map, offset); > } > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h > index e74c110facff..1c64f4d6ea21 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h > @@ -7,6 +7,7 @@ > #define _INTEL_GUC_ADS_H_ > > #include > +#include > > struct intel_guc; > struct drm_printer; > @@ -18,7 +19,7 @@ void intel_guc_ads_init_late(struct intel_guc *guc); > void intel_guc_ads_reset(struct intel_guc *guc); > void intel_guc_ads_print_policy_info(struct intel_guc *guc, > struct drm_printer *p); > -struct guc_engine_usage_record *intel_guc_engine_usage(struct intel_engine_cs *engine); > +struct iosys_map intel_guc_engine_usage_record_map(struct intel_engine_cs *engine); > u32 intel_guc_engine_usage_offset(struct intel_guc *guc); > > #endif > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > index b3a429a92c0d..ab3cea352fb3 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > @@ -1139,6 +1139,9 @@ __extend_last_switch(struct intel_guc *guc, u64 *prev_start, u32 new_start) > *prev_start = ((u64)gt_stamp_hi << 32) | new_start; > } > > +#define record_read(map_, field_) \ > + iosys_map_rd_field(map_, 0, struct guc_engine_usage_record, field_) > + > /* > * GuC updates shared memory and KMD reads it. Since this is not synchronized, > * we run into a race where the value read is inconsistent. Sometimes the > @@ -1153,17 +1156,17 @@ __extend_last_switch(struct intel_guc *guc, u64 *prev_start, u32 new_start) > static void __get_engine_usage_record(struct intel_engine_cs *engine, > u32 *last_in, u32 *id, u32 *total) > { > - struct guc_engine_usage_record *rec = intel_guc_engine_usage(engine); > + struct iosys_map rec_map = intel_guc_engine_usage_record_map(engine); > int i = 0; > > do { > - *last_in = READ_ONCE(rec->last_switch_in_stamp); > - *id = READ_ONCE(rec->current_context_index); > - *total = READ_ONCE(rec->total_runtime); > + *last_in = record_read(&rec_map, last_switch_in_stamp); > + *id = record_read(&rec_map, current_context_index); > + *total = record_read(&rec_map, total_runtime); > > - if (READ_ONCE(rec->last_switch_in_stamp) == *last_in && > - READ_ONCE(rec->current_context_index) == *id && > - READ_ONCE(rec->total_runtime) == *total) > + if (record_read(&rec_map, last_switch_in_stamp) == *last_in && > + record_read(&rec_map, current_context_index) == *id && > + record_read(&rec_map, total_runtime) == *total) > break; > } while (++i < 6); > } > -- > 2.35.1 >