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From: Sergey Matyukevich <geomatsi@gmail.com>
To: linux-snps-arc@lists.infradead.org
Cc: Vineet Gupta <vgupta@kernel.org>,
	Vladimir Isaev <isaev@synopsys.com>,
	Sergey Matyukevich <geomatsi@gmail.com>,
	Sergey Matyukevich <sergey.matyukevich@synopsys.com>
Subject: [RFC PATCH 06/13] ARCv2: memset: elide unaligned handling if hardware supports
Date: Tue, 22 Feb 2022 17:14:59 +0300	[thread overview]
Message-ID: <20220222141506.4003433-7-geomatsi@gmail.com> (raw)
In-Reply-To: <20220222141506.4003433-1-geomatsi@gmail.com>

From: Vineet Gupta <vgupta@kernel.org>

The only functional change is eliding the unaligned buffer head
handling. Also cleanup macros adding argument default values.

Signed-off-by: Vineet Gupta <vgupta@kernel.org>
---
 arch/arc/lib/memset-archs.S | 34 +++++++++++++++++-----------------
 1 file changed, 17 insertions(+), 17 deletions(-)

diff --git a/arch/arc/lib/memset-archs.S b/arch/arc/lib/memset-archs.S
index d0a5cec4cdca..330e22f7cf3c 100644
--- a/arch/arc/lib/memset-archs.S
+++ b/arch/arc/lib/memset-archs.S
@@ -17,43 +17,43 @@
 
 #if L1_CACHE_SHIFT == 6
 
-.macro PREALLOC_INSTR	reg, off
-	prealloc	[\reg, \off]
+.macro PREALLOCR s, off=0
+	prealloc [\s, \off]
 .endm
 
-.macro PREFETCHW_INSTR	reg, off
-	prefetchw	[\reg, \off]
+.macro PREFETCHWR s, off=0
+	prefetchw [\s, \off]
 .endm
 
 #else
 
-.macro PREALLOC_INSTR	reg, off
+.macro PREALLOCR s, off=0
 .endm
 
-.macro PREFETCHW_INSTR	reg, off
+.macro PREFETCHWR s, off=0
 .endm
 
 #endif
 
 ENTRY_CFI(memset)
+	; return if size 0 (happens lot)
 	mov.f	0, r2
-;;; if size is zero
 	jz.d	[blink]
-	mov	r3, r0		; don't clobber ret val
+	mov	r3, r0	; make a copy of input pointer reg
 
-	PREFETCHW_INSTR	r0, 0	; Prefetch the first write location
+	PREFETCHWR r0
 
-;;; if length < 8
-	brls.d.nt	r2, 8, .Lsmallchunk
-	mov.f	lp_count,r2
+	; small 1-8 byte handled in tail byte loop :-)
+	brlo	r2, 8, .Lbyteloop
 
-	and.f	r4, r0, 0x03
-	rsub	lp_count, r4, 4
-	lpnz	@.Laligndestination
-	;; LOOP BEGIN
+#ifndef CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS
+	; handle any starting unaligned bytes (upto 3)
+	and.f	lp_count, r0, 0x3
+	lpnz	1f
 	stb.ab	r1, [r3,1]
 	sub	r2, r2, 1
-.Laligndestination:
+1:
+#endif
 
 ;;; Destination is aligned
 	and	r1, r1, 0xFF
-- 
2.25.1


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  parent reply	other threads:[~2022-02-22 14:15 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-22 14:14 [RFC PATCH 00/13] ARC: handle the lack of ZOL support Sergey Matyukevich
2022-02-22 14:14 ` [RFC PATCH 01/13] ARC: uaccess: elide unaligned handling if hardware supports Sergey Matyukevich
2022-02-22 14:14 ` [RFC PATCH 02/13] ARC: Kconfig: introduce option to disable ZOL Sergey Matyukevich
2022-02-22 14:14 ` [RFC PATCH 03/13] ARC: uaccess: drop CC_OPTIMIZE_FOR_SIZE Sergey Matyukevich
2022-02-22 14:14 ` [RFC PATCH 04/13] ARC: uaccess: elide ZOL, use double load/stores Sergey Matyukevich
2022-02-22 14:14 ` [RFC PATCH 05/13] ARCv2: memset: don't prefetch for len == 0 which happens a lot Sergey Matyukevich
2022-02-22 14:14 ` Sergey Matyukevich [this message]
2022-02-22 14:15 ` [RFC PATCH 07/13] ARCv2: memset: rewrite using double load/stores Sergey Matyukevich
2022-02-22 14:15 ` [RFC PATCH 08/13] ARC: string: use generic C code if no ZOL support Sergey Matyukevich
2022-02-22 14:15 ` [RFC PATCH 09/13] ARC: delay: elide ZOL Sergey Matyukevich
2022-02-22 14:15 ` [RFC PATCH 10/13] ARC: checksum: " Sergey Matyukevich
2022-02-22 14:15 ` [RFC PATCH 11/13] ARC: head: " Sergey Matyukevich
2022-02-22 14:15 ` [RFC PATCH 12/13] ARC: build: inhibit ZOL generation by compiler Sergey Matyukevich
2022-02-22 14:15 ` [RFC PATCH 13/13] ARC: pt_regs: handle the case when ZOL is not supported Sergey Matyukevich
2022-02-28  2:09 ` [RFC PATCH 00/13] ARC: handle the lack of ZOL support Vineet Gupta
2022-03-03 19:22   ` Sergey Matyukevich
2022-03-23 10:09   ` [RFC PATCH 00/13] ARC: handle the lack of ZOL supporty Sergey Matyukevich

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