From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 30E54C433F5 for ; Tue, 22 Feb 2022 15:52:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233745AbiBVPwa (ORCPT ); Tue, 22 Feb 2022 10:52:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42782 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233707AbiBVPwK (ORCPT ); Tue, 22 Feb 2022 10:52:10 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7618B31519; Tue, 22 Feb 2022 07:51:44 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 01A2CB81B21; Tue, 22 Feb 2022 15:51:43 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6B8EAC340E8; Tue, 22 Feb 2022 15:51:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1645545101; bh=jhAZQpK2Xkwl6Uuj8dhwCmycOi92amDCrJPKvBaGcNs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IoIZBfB5KLbLmsyYgiWz81LP8qMF+ORSPtjBSduqUTzqTMhOdhudBvmFhgEMh7w08 gvY0uRXQz/GEItuc7Ej2Db2kLslKNy+aB5DoAFelMUek74n0JnQFbYBoim5MzboWNR 8m+EGYhUnrqEHS6qZRISW0rOHnGA2hvjDGAMur4RQ3ckrDqvot3EwiWeiukNFDUKmt E/7b4Nbltzei9ChKTUmkwvbslTRvxundb3gb2z4gYLkG4Ek4mdDfrIQRHIF9zM0JMZ ZJd1Qgml5JtSBgNIIjWOeb+zrddcFiGlD8/oRGwWSWNHzemt5kBfU78v7tGeO9HTGH 64muZZjkdd6YQ== Received: by pali.im (Postfix) id 1FDAEFDB; Tue, 22 Feb 2022 16:51:41 +0100 (CET) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: Lorenzo Pieralisi , Bjorn Helgaas , Rob Herring , Thomas Petazzoni , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , =?UTF-8?q?Marek=20Beh=C3=BAn?= , Russell King Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 07/12] PCI: mvebu: Add support for Advanced Error Reporting registers on emulated bridge Date: Tue, 22 Feb 2022 16:50:25 +0100 Message-Id: <20220222155030.988-8-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220222155030.988-1-pali@kernel.org> References: <20220222155030.988-1-pali@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org AER registers start at mvebu offset 0x0100. Registers PCI_ERR_ROOT_COMMAND, PCI_ERR_ROOT_STATUS and PCI_ERR_ROOT_ERR_SRC are not supported on pre-XP hardware and returns zeros. Note that AER interrupt is not supported yet as mvebu emulated bridge does not implement interrupts support at all yet. Also remove custom macro PCIE_HEADER_LOG_4_OFF as it is unused and correctly this register should be referenced via standard macros with offset, e.g. as: PCIE_CAP_PCIERR_OFF + PCI_ERR_HEADER_LOG + 4. Signed-off-by: Pali Rohár --- drivers/pci/controller/pci-mvebu.c | 67 +++++++++++++++++++++++++++++- 1 file changed, 66 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c index 566d8382afe6..1cf5c02499cd 100644 --- a/drivers/pci/controller/pci-mvebu.c +++ b/drivers/pci/controller/pci-mvebu.c @@ -34,7 +34,7 @@ #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3)) #define PCIE_SSDEV_ID_OFF 0x002c #define PCIE_CAP_PCIEXP 0x0060 -#define PCIE_HEADER_LOG_4_OFF 0x0128 +#define PCIE_CAP_PCIERR_OFF 0x0100 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4)) #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4)) #define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4)) @@ -603,6 +603,37 @@ mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge, return PCI_BRIDGE_EMUL_HANDLED; } +static pci_bridge_emul_read_status_t +mvebu_pci_bridge_emul_ext_conf_read(struct pci_bridge_emul *bridge, + int reg, u32 *value) +{ + struct mvebu_pcie_port *port = bridge->data; + + switch (reg) { + case 0: + case PCI_ERR_UNCOR_STATUS: + case PCI_ERR_UNCOR_MASK: + case PCI_ERR_UNCOR_SEVER: + case PCI_ERR_COR_STATUS: + case PCI_ERR_COR_MASK: + case PCI_ERR_CAP: + case PCI_ERR_HEADER_LOG+0: + case PCI_ERR_HEADER_LOG+4: + case PCI_ERR_HEADER_LOG+8: + case PCI_ERR_HEADER_LOG+12: + case PCI_ERR_ROOT_COMMAND: + case PCI_ERR_ROOT_STATUS: + case PCI_ERR_ROOT_ERR_SRC: + *value = mvebu_readl(port, PCIE_CAP_PCIERR_OFF + reg); + break; + + default: + return PCI_BRIDGE_EMUL_NOT_HANDLED; + } + + return PCI_BRIDGE_EMUL_HANDLED; +} + static void mvebu_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge, int reg, u32 old, u32 new, u32 mask) @@ -715,11 +746,45 @@ mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, } } +static void +mvebu_pci_bridge_emul_ext_conf_write(struct pci_bridge_emul *bridge, + int reg, u32 old, u32 new, u32 mask) +{ + struct mvebu_pcie_port *port = bridge->data; + + switch (reg) { + /* These are W1C registers, so clear other bits */ + case PCI_ERR_UNCOR_STATUS: + case PCI_ERR_COR_STATUS: + case PCI_ERR_ROOT_STATUS: + new &= mask; + fallthrough; + + case PCI_ERR_UNCOR_MASK: + case PCI_ERR_UNCOR_SEVER: + case PCI_ERR_COR_MASK: + case PCI_ERR_CAP: + case PCI_ERR_HEADER_LOG+0: + case PCI_ERR_HEADER_LOG+4: + case PCI_ERR_HEADER_LOG+8: + case PCI_ERR_HEADER_LOG+12: + case PCI_ERR_ROOT_COMMAND: + case PCI_ERR_ROOT_ERR_SRC: + mvebu_writel(port, new, PCIE_CAP_PCIERR_OFF + reg); + break; + + default: + break; + } +} + static const struct pci_bridge_emul_ops mvebu_pci_bridge_emul_ops = { .read_base = mvebu_pci_bridge_emul_base_conf_read, .write_base = mvebu_pci_bridge_emul_base_conf_write, .read_pcie = mvebu_pci_bridge_emul_pcie_conf_read, .write_pcie = mvebu_pci_bridge_emul_pcie_conf_write, + .read_ext = mvebu_pci_bridge_emul_ext_conf_read, + .write_ext = mvebu_pci_bridge_emul_ext_conf_write, }; /* -- 2.20.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: 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X0VSUl9ST09UX0NPTU1BTkQsClBDSV9FUlJfUk9PVF9TVEFUVVMgYW5kIFBDSV9FUlJfUk9PVF9F UlJfU1JDIGFyZSBub3Qgc3VwcG9ydGVkIG9uIHByZS1YUApoYXJkd2FyZSBhbmQgcmV0dXJucyB6 ZXJvcy4KCk5vdGUgdGhhdCBBRVIgaW50ZXJydXB0IGlzIG5vdCBzdXBwb3J0ZWQgeWV0IGFzIG12 ZWJ1IGVtdWxhdGVkIGJyaWRnZSBkb2VzCm5vdCBpbXBsZW1lbnQgaW50ZXJydXB0cyBzdXBwb3J0 IGF0IGFsbCB5ZXQuCgpBbHNvIHJlbW92ZSBjdXN0b20gbWFjcm8gUENJRV9IRUFERVJfTE9HXzRf T0ZGIGFzIGl0IGlzIHVudXNlZCBhbmQKY29ycmVjdGx5IHRoaXMgcmVnaXN0ZXIgc2hvdWxkIGJl IHJlZmVyZW5jZWQgdmlhIHN0YW5kYXJkIG1hY3JvcyB3aXRoCm9mZnNldCwgZS5nLiBhczogUENJ RV9DQVBfUENJRVJSX09GRiArIFBDSV9FUlJfSEVBREVSX0xPRyArIDQuCgpTaWduZWQtb2ZmLWJ5 OiBQYWxpIFJvaMOhciA8cGFsaUBrZXJuZWwub3JnPgotLS0KIGRyaXZlcnMvcGNpL2NvbnRyb2xs ZXIvcGNpLW12ZWJ1LmMgfCA2NyArKysrKysrKysrKysrKysrKysrKysrKysrKysrKy0KIDEgZmls ZSBjaGFuZ2VkLCA2NiBpbnNlcnRpb25zKCspLCAxIGRlbGV0aW9uKC0pCgpkaWZmIC0tZ2l0IGEv ZHJpdmVycy9wY2kvY29udHJvbGxlci9wY2ktbXZlYnUuYyBiL2RyaXZlcnMvcGNpL2NvbnRyb2xs ZXIvcGNpLW12ZWJ1LmMKaW5kZXggNTY2ZDgzODJhZmU2Li4xY2Y1YzAyNDk5Y2QgMTAwNjQ0Ci0t LSBhL2RyaXZlcnMvcGNpL2NvbnRyb2xsZXIvcGNpLW12ZWJ1LmMKKysrIGIvZHJpdmVycy9wY2kv Y29udHJvbGxlci9wY2ktbXZlYnUuYwpAQCAtMzQsNyArMzQsNyBAQAogI2RlZmluZSBQQ0lFX0JB Ul9ISV9PRkYobikJKDB4MDAxNCArICgobikgPDwgMykpCiAjZGVmaW5lIFBDSUVfU1NERVZfSURf T0ZGCTB4MDAyYwogI2RlZmluZSBQQ0lFX0NBUF9QQ0lFWFAJCTB4MDA2MAotI2RlZmluZSBQQ0lF X0hFQURFUl9MT0dfNF9PRkYJMHgwMTI4CisjZGVmaW5lIFBDSUVfQ0FQX1BDSUVSUl9PRkYJMHgw MTAwCiAjZGVmaW5lIFBDSUVfQkFSX0NUUkxfT0ZGKG4pCSgweDE4MDQgKyAoKChuKSAtIDEpICog NCkpCiAjZGVmaW5lIFBDSUVfV0lOMDRfQ1RSTF9PRkYobikJKDB4MTgyMCArICgobikgPDwgNCkp CiAjZGVmaW5lIFBDSUVfV0lOMDRfQkFTRV9PRkYobikJKDB4MTgyNCArICgobikgPDwgNCkpCkBA IC02MDMsNiArNjAzLDM3IEBAIG12ZWJ1X3BjaV9icmlkZ2VfZW11bF9wY2llX2NvbmZfcmVhZChz dHJ1Y3QgcGNpX2JyaWRnZV9lbXVsICpicmlkZ2UsCiAJcmV0dXJuIFBDSV9CUklER0VfRU1VTF9I QU5ETEVEOwogfQogCitzdGF0aWMgcGNpX2JyaWRnZV9lbXVsX3JlYWRfc3RhdHVzX3QKK212ZWJ1 X3BjaV9icmlkZ2VfZW11bF9leHRfY29uZl9yZWFkKHN0cnVjdCBwY2lfYnJpZGdlX2VtdWwgKmJy aWRnZSwKKwkJCQkgICAgaW50IHJlZywgdTMyICp2YWx1ZSkKK3sKKwlzdHJ1Y3QgbXZlYnVfcGNp ZV9wb3J0ICpwb3J0ID0gYnJpZGdlLT5kYXRhOworCisJc3dpdGNoIChyZWcpIHsKKwljYXNlIDA6 CisJY2FzZSBQQ0lfRVJSX1VOQ09SX1NUQVRVUzoKKwljYXNlIFBDSV9FUlJfVU5DT1JfTUFTSzoK KwljYXNlIFBDSV9FUlJfVU5DT1JfU0VWRVI6CisJY2FzZSBQQ0lfRVJSX0NPUl9TVEFUVVM6CisJ Y2FzZSBQQ0lfRVJSX0NPUl9NQVNLOgorCWNhc2UgUENJX0VSUl9DQVA6CisJY2FzZSBQQ0lfRVJS X0hFQURFUl9MT0crMDoKKwljYXNlIFBDSV9FUlJfSEVBREVSX0xPRys0OgorCWNhc2UgUENJX0VS Ul9IRUFERVJfTE9HKzg6CisJY2FzZSBQQ0lfRVJSX0hFQURFUl9MT0crMTI6CisJY2FzZSBQQ0lf RVJSX1JPT1RfQ09NTUFORDoKKwljYXNlIFBDSV9FUlJfUk9PVF9TVEFUVVM6CisJY2FzZSBQQ0lf RVJSX1JPT1RfRVJSX1NSQzoKKwkJKnZhbHVlID0gbXZlYnVfcmVhZGwocG9ydCwgUENJRV9DQVBf UENJRVJSX09GRiArIHJlZyk7CisJCWJyZWFrOworCisJZGVmYXVsdDoKKwkJcmV0dXJuIFBDSV9C UklER0VfRU1VTF9OT1RfSEFORExFRDsKKwl9CisKKwlyZXR1cm4gUENJX0JSSURHRV9FTVVMX0hB TkRMRUQ7Cit9CisKIHN0YXRpYyB2b2lkCiBtdmVidV9wY2lfYnJpZGdlX2VtdWxfYmFzZV9jb25m X3dyaXRlKHN0cnVjdCBwY2lfYnJpZGdlX2VtdWwgKmJyaWRnZSwKIAkJCQkgICAgICBpbnQgcmVn LCB1MzIgb2xkLCB1MzIgbmV3LCB1MzIgbWFzaykKQEAgLTcxNSwxMSArNzQ2LDQ1IEBAIG12ZWJ1 X3BjaV9icmlkZ2VfZW11bF9wY2llX2NvbmZfd3JpdGUoc3RydWN0IHBjaV9icmlkZ2VfZW11bCAq YnJpZGdlLAogCX0KIH0KIAorc3RhdGljIHZvaWQKK212ZWJ1X3BjaV9icmlkZ2VfZW11bF9leHRf Y29uZl93cml0ZShzdHJ1Y3QgcGNpX2JyaWRnZV9lbXVsICpicmlkZ2UsCisJCQkJICAgICBpbnQg cmVnLCB1MzIgb2xkLCB1MzIgbmV3LCB1MzIgbWFzaykKK3sKKwlzdHJ1Y3QgbXZlYnVfcGNpZV9w b3J0ICpwb3J0ID0gYnJpZGdlLT5kYXRhOworCisJc3dpdGNoIChyZWcpIHsKKwkvKiBUaGVzZSBh cmUgVzFDIHJlZ2lzdGVycywgc28gY2xlYXIgb3RoZXIgYml0cyAqLworCWNhc2UgUENJX0VSUl9V TkNPUl9TVEFUVVM6CisJY2FzZSBQQ0lfRVJSX0NPUl9TVEFUVVM6CisJY2FzZSBQQ0lfRVJSX1JP T1RfU1RBVFVTOgorCQluZXcgJj0gbWFzazsKKwkJZmFsbHRocm91Z2g7CisKKwljYXNlIFBDSV9F UlJfVU5DT1JfTUFTSzoKKwljYXNlIFBDSV9FUlJfVU5DT1JfU0VWRVI6CisJY2FzZSBQQ0lfRVJS X0NPUl9NQVNLOgorCWNhc2UgUENJX0VSUl9DQVA6CisJY2FzZSBQQ0lfRVJSX0hFQURFUl9MT0cr MDoKKwljYXNlIFBDSV9FUlJfSEVBREVSX0xPRys0OgorCWNhc2UgUENJX0VSUl9IRUFERVJfTE9H Kzg6CisJY2FzZSBQQ0lfRVJSX0hFQURFUl9MT0crMTI6CisJY2FzZSBQQ0lfRVJSX1JPT1RfQ09N TUFORDoKKwljYXNlIFBDSV9FUlJfUk9PVF9FUlJfU1JDOgorCQltdmVidV93cml0ZWwocG9ydCwg bmV3LCBQQ0lFX0NBUF9QQ0lFUlJfT0ZGICsgcmVnKTsKKwkJYnJlYWs7CisKKwlkZWZhdWx0Ogor CQlicmVhazsKKwl9Cit9CisKIHN0YXRpYyBjb25zdCBzdHJ1Y3QgcGNpX2JyaWRnZV9lbXVsX29w cyBtdmVidV9wY2lfYnJpZGdlX2VtdWxfb3BzID0gewogCS5yZWFkX2Jhc2UgPSBtdmVidV9wY2lf YnJpZGdlX2VtdWxfYmFzZV9jb25mX3JlYWQsCiAJLndyaXRlX2Jhc2UgPSBtdmVidV9wY2lfYnJp ZGdlX2VtdWxfYmFzZV9jb25mX3dyaXRlLAogCS5yZWFkX3BjaWUgPSBtdmVidV9wY2lfYnJpZGdl X2VtdWxfcGNpZV9jb25mX3JlYWQsCiAJLndyaXRlX3BjaWUgPSBtdmVidV9wY2lfYnJpZGdlX2Vt dWxfcGNpZV9jb25mX3dyaXRlLAorCS5yZWFkX2V4dCA9IG12ZWJ1X3BjaV9icmlkZ2VfZW11bF9l eHRfY29uZl9yZWFkLAorCS53cml0ZV9leHQgPSBtdmVidV9wY2lfYnJpZGdlX2VtdWxfZXh0X2Nv bmZfd3JpdGUsCiB9OwogCiAvKgotLSAKMi4yMC4xCgoKX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX18KbGludXgtYXJtLWtlcm5lbCBtYWlsaW5nIGxpc3QKbGlu dXgtYXJtLWtlcm5lbEBsaXN0cy5pbmZyYWRlYWQub3JnCmh0dHA6Ly9saXN0cy5pbmZyYWRlYWQu b3JnL21haWxtYW4vbGlzdGluZm8vbGludXgtYXJtLWtlcm5lbAo=