From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22869C433EF for ; Wed, 23 Feb 2022 10:01:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238612AbiBWKCU (ORCPT ); Wed, 23 Feb 2022 05:02:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56176 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236112AbiBWKCU (ORCPT ); Wed, 23 Feb 2022 05:02:20 -0500 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 3ADF63F332; Wed, 23 Feb 2022 02:01:53 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 063E41042; Wed, 23 Feb 2022 02:01:53 -0800 (PST) Received: from lpieralisi (e121166-lin.cambridge.arm.com [10.1.196.255]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DE24E3F70D; Wed, 23 Feb 2022 02:01:51 -0800 (PST) Date: Wed, 23 Feb 2022 10:01:45 +0000 From: Lorenzo Pieralisi To: Manivannan Sadhasivam , bjorn.andersson@linaro.org Cc: bhelgaas@google.com, svarbanov@mm-sol.com, robh@kernel.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] PCI: qcom: Add support for handling MSIs from 8 endpoints Message-ID: <20220223100145.GA26873@lpieralisi> References: <20211214101319.25258-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20211214101319.25258-1-manivannan.sadhasivam@linaro.org> User-Agent: Mutt/1.9.4 (2018-02-28) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Tue, Dec 14, 2021 at 03:43:19PM +0530, Manivannan Sadhasivam wrote: > The DWC controller used in the Qcom Platforms are capable of addressing the > MSIs generated from 8 different endpoints each with 32 vectors (256 in > total). Currently the driver is using the default value of addressing the > MSIs from 1 endpoint only. Extend it by passing the MAX_MSI_IRQS to the > num_vectors field of pcie_port structure. > > Signed-off-by: Manivannan Sadhasivam > --- > drivers/pci/controller/dwc/pcie-qcom.c | 1 + > 1 file changed, 1 insertion(+) Need an ACK from qcom maintainers. Thanks, Lorenzo > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 1c3d1116bb60..8a4c08d815a5 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -1550,6 +1550,7 @@ static int qcom_pcie_probe(struct platform_device *pdev) > pci->dev = dev; > pci->ops = &dw_pcie_ops; > pp = &pci->pp; > + pp->num_vectors = MAX_MSI_IRQS; > > pcie->pci = pci; > > -- > 2.25.1 >