From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E7FDC6A for ; Wed, 23 Feb 2022 12:54:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1645620853; x=1677156853; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=hh7zR6Pvu7wP8j5WrsKvOxqv9nPHKiPowFIoGx++A9Y=; b=fj+sO2ldKqKwX4UAl8Q2O10LXLjOV6M4dnZe4CkmeGLDuV9jFjg4MdDx ylGJo2FVxR6c5hT5N3mI+1VCE+QHZKNkSA7CFshCFgV2Zwb0qiwhY3LiB wY4JUksVYfA7vRbd5i4TlWB4QjzIxzzTYAaze3uz2DdH5Mvg50FFVyNtI tKv6qxoS6vytCQai662kcg7f/s/s7Vgoa5eUWafiqKYgHjCJ/Q/dDE93e fQkw6/2yUYFFGSYnqQ6+6ZJst20X5JkDwlcZ7SV0TMxbPaW4HltVTS2iq XUu2F3c7T+0+WwRj78TEvEsfRyZoegKQ/CU/M7NWhU8evx4/C+S0lxe4a w==; X-IronPort-AV: E=McAfee;i="6200,9189,10266"; a="232575565" X-IronPort-AV: E=Sophos;i="5.88,390,1635231600"; d="scan'208";a="232575565" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Feb 2022 04:54:12 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,390,1635231600"; d="scan'208";a="781871281" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga005.fm.intel.com with ESMTP; 23 Feb 2022 04:54:08 -0800 Received: by black.fi.intel.com (Postfix, from userid 1000) id D99DA143; Wed, 23 Feb 2022 14:54:24 +0200 (EET) Date: Wed, 23 Feb 2022 15:54:24 +0300 From: "Kirill A. Shutemov" To: Borislav Petkov Cc: Brijesh Singh , x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-coco@lists.linux.dev, Thomas Gleixner , Ingo Molnar , Joerg Roedel , Tom Lendacky , "H. Peter Anvin" , Paolo Bonzini , Sean Christopherson , Andy Lutomirski , Dave Hansen , Peter Gonda , Peter Zijlstra , David Rientjes , Michael Roth , Andi Kleen Subject: Re: [PATCH] x86/mm/cpa: Generalize __set_memory_enc_pgtable() Message-ID: <20220223125424.ynwfqjejnzx3cdbw@black.fi.intel.com> References: <20220222185740.26228-1-kirill.shutemov@linux.intel.com> <20220223043528.2093214-1-brijesh.singh@amd.com> <20220223115539.pqk7624xku2qwhlu@black.fi.intel.com> <20220223122508.3nvvz4b7fj2fsr2a@black.fi.intel.com> Precedence: bulk X-Mailing-List: linux-coco@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Wed, Feb 23, 2022 at 01:38:03PM +0100, Borislav Petkov wrote: > On Wed, Feb 23, 2022 at 03:25:08PM +0300, Kirill A. Shutemov wrote: > > So far it is only success or failure. I used int and -EIO as failure. > > bool is enough, but I don't see a reason not to use int. > > bool it is. > > --- > From 8855bca859d8768ac04bfcf5b4aeb9cf3c69295a Mon Sep 17 00:00:00 2001 > From: Brijesh Singh > Date: Tue, 22 Feb 2022 22:35:28 -0600 > Subject: [PATCH] x86/mm/cpa: Generalize __set_memory_enc_pgtable() > > The kernel provides infrastructure to set or clear the encryption mask > from the pages for AMD SEV, but TDX requires few tweaks. > > - TDX and SEV have different requirements to the cache and TLB > flushing. > > - TDX has own routine to notify VMM about page encryption status change. > > Modify __set_memory_enc_pgtable() and make it flexible enough to cover > both AMD SEV and Intel TDX. The AMD-specific behavior is isolated in > callback under x86_platform_cc. TDX will provide own version of the "under x86_platform.guest" > callbacks. > > [ bp: Beat into submission. ] > > Signed-off-by: Brijesh Singh > Signed-off-by: Borislav Petkov > Link: https://lore.kernel.org/r/20220223043528.2093214-1-brijesh.singh@amd.com Otherwise, LGTM: Acked-by: Kirill A. Shutemov -- Kirill A. Shutemov