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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Alistair Francis" <alistair.francis@wdc.com>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PATCH v2 8/9] tcg/riscv: Support TCG_TARGET_SIGNED_ADDR32
Date: Sat, 26 Feb 2022 16:04:12 -1000	[thread overview]
Message-ID: <20220227020413.11741-9-richard.henderson@linaro.org> (raw)
In-Reply-To: <20220227020413.11741-1-richard.henderson@linaro.org>

All RV64 32-bit operations sign-extend the output, so we are easily
able to keep TCG_TYPE_I32 values sign-extended in host registers.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/riscv/tcg-target-sa32.h | 6 +++++-
 tcg/riscv/tcg-target.c.inc  | 8 ++------
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/tcg/riscv/tcg-target-sa32.h b/tcg/riscv/tcg-target-sa32.h
index cb185b1526..703467b37a 100644
--- a/tcg/riscv/tcg-target-sa32.h
+++ b/tcg/riscv/tcg-target-sa32.h
@@ -1 +1,5 @@
-#define TCG_TARGET_SIGNED_ADDR32 0
+/*
+ * Do not set TCG_TARGET_SIGNED_ADDR32 for RV32;
+ * TCG expects this to only be set for 64-bit hosts.
+ */
+#define TCG_TARGET_SIGNED_ADDR32  (__riscv_xlen == 64)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index 6409d9c3d5..c999711494 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -951,10 +951,6 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
     tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0);
 
     /* TLB Hit - translate address using addend.  */
-    if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
-        tcg_out_ext32u(s, TCG_REG_TMP0, addrl);
-        addrl = TCG_REG_TMP0;
-    }
     tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addrl);
 }
 
@@ -1175,7 +1171,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
                         data_regl, data_regh, addr_regl, addr_regh,
                         s->code_ptr, label_ptr);
 #else
-    if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
+    if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS && !guest_base_signed_addr32) {
         tcg_out_ext32u(s, base, addr_regl);
         addr_regl = base;
     }
@@ -1247,7 +1243,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
                         data_regl, data_regh, addr_regl, addr_regh,
                         s->code_ptr, label_ptr);
 #else
-    if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
+    if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS && !guest_base_signed_addr32) {
         tcg_out_ext32u(s, base, addr_regl);
         addr_regl = base;
     }
-- 
2.25.1



  parent reply	other threads:[~2022-02-27  2:09 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-27  2:04 [PATCH v2 0/9] tcg: support 32-bit guest addresses as signed Richard Henderson
2022-02-27  2:04 ` [PATCH v2 1/9] tcg: Add TCG_TARGET_SIGNED_ADDR32 Richard Henderson
2022-02-27  2:04 ` [PATCH v2 2/9] accel/tcg: Split out g2h_tlbe Richard Henderson
2022-02-27  2:04 ` [PATCH v2 3/9] accel/tcg: Support TCG_TARGET_SIGNED_ADDR32 for softmmu Richard Henderson
2022-02-27 22:32   ` Philippe Mathieu-Daudé
2022-03-03 15:14   ` Peter Maydell
2022-02-27  2:04 ` [PATCH v2 4/9] accel/tcg: Add guest_base_signed_addr32 for user-only Richard Henderson
2022-03-03 15:14   ` Peter Maydell
2022-02-27  2:04 ` [PATCH v2 5/9] linux-user: Support TCG_TARGET_SIGNED_ADDR32 Richard Henderson
2022-02-27 22:48   ` Philippe Mathieu-Daudé
2022-02-27  2:04 ` [PATCH v2 6/9] tcg/aarch64: " Richard Henderson
2022-03-03 15:04   ` Peter Maydell
2022-03-03 15:43     ` Richard Henderson
2022-03-03 16:19       ` Peter Maydell
2022-02-27  2:04 ` [PATCH v2 7/9] tcg/mips: " Richard Henderson
2022-02-27 22:51   ` Philippe Mathieu-Daudé
2022-02-27  2:04 ` Richard Henderson [this message]
2022-02-27  2:04 ` [PATCH v2 9/9] tcg/loongarch64: " Richard Henderson
2022-02-27 22:52   ` Philippe Mathieu-Daudé

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