From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B0B9C433F5 for ; Mon, 28 Feb 2022 03:22:01 +0000 (UTC) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EBD9E4068C; Mon, 28 Feb 2022 04:21:59 +0100 (CET) Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by mails.dpdk.org (Postfix) with ESMTP id 6A4EF4068A for ; Mon, 28 Feb 2022 04:21:57 +0100 (CET) Received: from dggeme756-chm.china.huawei.com (unknown [172.30.72.57]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4K6QXt73rGzbbtr; Mon, 28 Feb 2022 11:17:18 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by dggeme756-chm.china.huawei.com (10.3.19.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.21; Mon, 28 Feb 2022 11:21:55 +0800 From: "Min Hu (Connor)" To: CC: , Subject: [PATCH 6/6] net/hns3: fix VF RSS TC mode entry Date: Mon, 28 Feb 2022 11:21:46 +0800 Message-ID: <20220228032146.37407-7-humin29@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220228032146.37407-1-humin29@huawei.com> References: <20220228032146.37407-1-humin29@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.69.192.56] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggeme756-chm.china.huawei.com (10.3.19.102) X-CFilter-Loop: Reflected X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Huisong Li For packets with VLAN priorities destined for the VF, hardware still assign Rx queue based on the Up-to-TC mapping PF configured. But VF has only one TC. If other TC don't enable, it causes that the priority packets that aren't destined for TC0 aren't received by RSS hash but is destined for queue 0. So driver has to enable the unused TC by using TC0 queue mapping configuration. Fixes: c37ca66f2b27 ("net/hns3: support RSS") Cc: stable@dpdk.org Signed-off-by: Huisong Li --- drivers/net/hns3/hns3_rss.c | 56 +++++++++++++++++++++++++++---------- 1 file changed, 41 insertions(+), 15 deletions(-) diff --git a/drivers/net/hns3/hns3_rss.c b/drivers/net/hns3/hns3_rss.c index 5077d49882..9606801140 100644 --- a/drivers/net/hns3/hns3_rss.c +++ b/drivers/net/hns3/hns3_rss.c @@ -587,33 +587,59 @@ hns3_dev_rss_reta_query(struct rte_eth_dev *dev, return 0; } -/* - * Used to configure the tc_size and tc_offset. - */ +static void +hns3_set_rss_tc_mode_entry(struct hns3_hw *hw, uint8_t *tc_valid, + uint16_t *tc_size, uint16_t *tc_offset, + uint8_t tc_num) +{ + struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); + uint16_t rss_size = hw->alloc_rss_size; + uint16_t roundup_size; + uint16_t i; + + roundup_size = roundup_pow_of_two(rss_size); + roundup_size = ilog2(roundup_size); + + for (i = 0; i < tc_num; i++) { + if (hns->is_vf) { + /* + * For packets with VLAN priorities destined for the VF, + * hardware still assign Rx queue based on the Up-to-TC + * mapping PF configured. But VF has only one TC. If + * other TC don't enable, it causes that the priority + * packets that aren't destined for TC0 aren't received + * by RSS hash but is destined for queue 0. So driver + * has to enable the unused TC by using TC0 queue + * mapping configuration. + */ + tc_valid[i] = (hw->hw_tc_map & BIT(i)) ? + !!(hw->hw_tc_map & BIT(i)) : 1; + tc_size[i] = roundup_size; + tc_offset[i] = (hw->hw_tc_map & BIT(i)) ? + rss_size * i : 0; + } else { + tc_valid[i] = !!(hw->hw_tc_map & BIT(i)); + tc_size[i] = tc_valid[i] ? roundup_size : 0; + tc_offset[i] = tc_valid[i] ? rss_size * i : 0; + } + } +} + static int hns3_set_rss_tc_mode(struct hns3_hw *hw) { - uint16_t rss_size = hw->alloc_rss_size; struct hns3_rss_tc_mode_cmd *req; uint16_t tc_offset[HNS3_MAX_TC_NUM]; uint8_t tc_valid[HNS3_MAX_TC_NUM]; uint16_t tc_size[HNS3_MAX_TC_NUM]; struct hns3_cmd_desc desc; - uint16_t roundup_size; uint16_t i; int ret; - req = (struct hns3_rss_tc_mode_cmd *)desc.data; - - roundup_size = roundup_pow_of_two(rss_size); - roundup_size = ilog2(roundup_size); - - for (i = 0; i < HNS3_MAX_TC_NUM; i++) { - tc_valid[i] = !!(hw->hw_tc_map & BIT(i)); - tc_size[i] = tc_valid[i] ? roundup_size : 0; - tc_offset[i] = tc_valid[i] ? rss_size * i : 0; - } + hns3_set_rss_tc_mode_entry(hw, tc_valid, tc_size, + tc_offset, HNS3_MAX_TC_NUM); + req = (struct hns3_rss_tc_mode_cmd *)desc.data; hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RSS_TC_MODE, false); for (i = 0; i < HNS3_MAX_TC_NUM; i++) { uint16_t mode = 0; -- 2.33.0