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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT030.mail.protection.outlook.com (10.13.177.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5017.22 via Frontend Transport; Mon, 28 Feb 2022 16:14:41 +0000 Received: from milan-ETHANOL-X.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Mon, 28 Feb 2022 10:14:38 -0600 From: Naveen Krishna Chatradhi To: CC: , , , , Muralidhara M K , "Naveen Krishna Chatradhi" Subject: [PATCH 09/14] EDAC/amd64: Add determine_edac_ctl_cap() into pvt->ops Date: Mon, 28 Feb 2022 21:43:49 +0530 Message-ID: <20220228161354.54923-10-nchatrad@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220228161354.54923-1-nchatrad@amd.com> References: <20220228161354.54923-1-nchatrad@amd.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a5d77f04-27c5-437a-a895-08d9fad56d2b X-MS-TrafficTypeDiagnostic: BN6PR12MB1747:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Feb 2022 16:14:41.5566 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a5d77f04-27c5-437a-a895-08d9fad56d2b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT030.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1747 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Muralidhara M K Add function pointer for determine_edac_ctl_cap() in pvt->ops and assign family specific determine_edac_ctl_cap() definitions appropriately. Signed-off-by: Muralidhara M K Signed-off-by: Naveen Krishna Chatradhi --- This patch is created by splitting the 5/12th patch in series [v7 5/12] https://patchwork.kernel.org/project/linux-edac/patch/20220203174942.31630-6-nchatrad@amd.com/ drivers/edac/amd64_edac.c | 30 +++++++++++++++++++----------- drivers/edac/amd64_edac.h | 1 + 2 files changed, 20 insertions(+), 11 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index af6711cf03e9..e3b0a0329f43 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -3716,7 +3716,17 @@ static bool f17_ecc_enabled(struct amd64_pvt *pvt) } static inline void -f17h_determine_edac_ctl_cap(struct mem_ctl_info *mci, struct amd64_pvt *pvt) +f1x_determine_edac_ctl_cap(struct mem_ctl_info *mci, struct amd64_pvt *pvt) +{ + if (pvt->nbcap & NBCAP_SECDED) + mci->edac_ctl_cap |= EDAC_FLAG_SECDED; + + if (pvt->nbcap & NBCAP_CHIPKILL) + mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED; +} + +static inline void +f17_determine_edac_ctl_cap(struct mem_ctl_info *mci, struct amd64_pvt *pvt) { u8 i, ecc_en = 1, cpk_en = 1, dev_x4 = 1, dev_x16 = 1; @@ -3753,15 +3763,7 @@ static void setup_mci_misc_attrs(struct mem_ctl_info *mci) mci->mtype_cap = MEM_FLAG_DDR2 | MEM_FLAG_RDDR2; mci->edac_ctl_cap = EDAC_FLAG_NONE; - if (pvt->umc) { - f17h_determine_edac_ctl_cap(mci, pvt); - } else { - if (pvt->nbcap & NBCAP_SECDED) - mci->edac_ctl_cap |= EDAC_FLAG_SECDED; - - if (pvt->nbcap & NBCAP_CHIPKILL) - mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED; - } + pvt->ops->determine_edac_ctl_cap(mci, pvt); mci->edac_cap = pvt->ops->determine_edac_cap(pvt); mci->mod_name = EDAC_MOD_STR; @@ -3801,6 +3803,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->get_mc_regs = read_mc_regs; pvt->ops->ecc_enabled = f1x_ecc_enabled; pvt->ops->determine_edac_cap = f1x_determine_edac_cap; + pvt->ops->determine_edac_ctl_cap = f1x_determine_edac_ctl_cap; break; case 0x10: @@ -3817,6 +3820,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->get_mc_regs = read_mc_regs; pvt->ops->ecc_enabled = f1x_ecc_enabled; pvt->ops->determine_edac_cap = f1x_determine_edac_cap; + pvt->ops->determine_edac_ctl_cap = f1x_determine_edac_ctl_cap; break; case 0x15: @@ -3849,6 +3853,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->get_mc_regs = read_mc_regs; pvt->ops->ecc_enabled = f1x_ecc_enabled; pvt->ops->determine_edac_cap = f1x_determine_edac_cap; + pvt->ops->determine_edac_ctl_cap = f1x_determine_edac_ctl_cap; break; case 0x16: @@ -3871,6 +3876,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->get_mc_regs = read_mc_regs; pvt->ops->ecc_enabled = f1x_ecc_enabled; pvt->ops->determine_edac_cap = f1x_determine_edac_cap; + pvt->ops->determine_edac_ctl_cap = f1x_determine_edac_ctl_cap; break; case 0x17: @@ -3907,6 +3913,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->get_mc_regs = __read_mc_regs_df; pvt->ops->ecc_enabled = f17_ecc_enabled; pvt->ops->determine_edac_cap = f17_determine_edac_cap; + pvt->ops->determine_edac_ctl_cap = f17_determine_edac_ctl_cap; if (pvt->fam == 0x18) { pvt->ctl_name = "F18h"; @@ -3949,6 +3956,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->get_mc_regs = __read_mc_regs_df; pvt->ops->ecc_enabled = f17_ecc_enabled; pvt->ops->determine_edac_cap = f17_determine_edac_cap; + pvt->ops->determine_edac_ctl_cap = f17_determine_edac_ctl_cap; break; default: @@ -3961,7 +3969,7 @@ static int per_family_init(struct amd64_pvt *pvt) !pvt->ops->get_base_mask || !pvt->ops->prep_chip_selects || !pvt->ops->determine_memory_type || !pvt->ops->determine_ecc_sym_sz || !pvt->ops->get_mc_regs || !pvt->ops->ecc_enabled || - !pvt->ops->determine_edac_cap) { + !pvt->ops->determine_edac_cap || !pvt->ops->determine_edac_ctl_cap) { edac_dbg(1, "Common helper routines not defined.\n"); return -EFAULT; } diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index 9a789cb01f4d..0e0715a16981 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h @@ -471,6 +471,7 @@ struct low_ops { void (*get_mc_regs)(struct amd64_pvt *pvt); bool (*ecc_enabled)(struct amd64_pvt *pvt); unsigned long (*determine_edac_cap)(struct amd64_pvt *pvt); + void (*determine_edac_ctl_cap)(struct mem_ctl_info *mci, struct amd64_pvt *pvt); }; int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset, -- 2.25.1