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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Feb 2022 16:14:44.2447 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9ea8f937-9b9f-4b8b-d434-08d9fad56ec5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT057.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4583 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Muralidhara M K Add function pointer for setup_mci_misc_sttrs() in pvt->ops and assign family specific setup_mci_misc_sttrs() definitions appropriately Signed-off-by: Muralidhara M K Signed-off-by: Naveen Krishna Chatradhi --- This patch is created by splitting the 5/12th patch in series [v7 5/12] https://patchwork.kernel.org/project/linux-edac/patch/20220203174942.31630-6-nchatrad@amd.com/ drivers/edac/amd64_edac.c | 13 ++++++++++--- drivers/edac/amd64_edac.h | 1 + 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index e3b0a0329f43..c86674c3238d 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -3756,7 +3756,7 @@ f17_determine_edac_ctl_cap(struct mem_ctl_info *mci, struct amd64_pvt *pvt) } } -static void setup_mci_misc_attrs(struct mem_ctl_info *mci) +static void f1x_setup_mci_misc_attrs(struct mem_ctl_info *mci) { struct amd64_pvt *pvt = mci->pvt_info; @@ -3804,6 +3804,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->ecc_enabled = f1x_ecc_enabled; pvt->ops->determine_edac_cap = f1x_determine_edac_cap; pvt->ops->determine_edac_ctl_cap = f1x_determine_edac_ctl_cap; + pvt->ops->setup_mci_misc_attrs = f1x_setup_mci_misc_attrs; break; case 0x10: @@ -3821,6 +3822,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->ecc_enabled = f1x_ecc_enabled; pvt->ops->determine_edac_cap = f1x_determine_edac_cap; pvt->ops->determine_edac_ctl_cap = f1x_determine_edac_ctl_cap; + pvt->ops->setup_mci_misc_attrs = f1x_setup_mci_misc_attrs; break; case 0x15: @@ -3854,6 +3856,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->ecc_enabled = f1x_ecc_enabled; pvt->ops->determine_edac_cap = f1x_determine_edac_cap; pvt->ops->determine_edac_ctl_cap = f1x_determine_edac_ctl_cap; + pvt->ops->setup_mci_misc_attrs = f1x_setup_mci_misc_attrs; break; case 0x16: @@ -3877,6 +3880,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->ecc_enabled = f1x_ecc_enabled; pvt->ops->determine_edac_cap = f1x_determine_edac_cap; pvt->ops->determine_edac_ctl_cap = f1x_determine_edac_ctl_cap; + pvt->ops->setup_mci_misc_attrs = f1x_setup_mci_misc_attrs; break; case 0x17: @@ -3914,6 +3918,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->ecc_enabled = f17_ecc_enabled; pvt->ops->determine_edac_cap = f17_determine_edac_cap; pvt->ops->determine_edac_ctl_cap = f17_determine_edac_ctl_cap; + pvt->ops->setup_mci_misc_attrs = f1x_setup_mci_misc_attrs; if (pvt->fam == 0x18) { pvt->ctl_name = "F18h"; @@ -3957,6 +3962,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->ecc_enabled = f17_ecc_enabled; pvt->ops->determine_edac_cap = f17_determine_edac_cap; pvt->ops->determine_edac_ctl_cap = f17_determine_edac_ctl_cap; + pvt->ops->setup_mci_misc_attrs = f1x_setup_mci_misc_attrs; break; default: @@ -3969,7 +3975,8 @@ static int per_family_init(struct amd64_pvt *pvt) !pvt->ops->get_base_mask || !pvt->ops->prep_chip_selects || !pvt->ops->determine_memory_type || !pvt->ops->determine_ecc_sym_sz || !pvt->ops->get_mc_regs || !pvt->ops->ecc_enabled || - !pvt->ops->determine_edac_cap || !pvt->ops->determine_edac_ctl_cap) { + !pvt->ops->determine_edac_cap || !pvt->ops->determine_edac_ctl_cap || + !pvt->ops->setup_mci_misc_attrs) { edac_dbg(1, "Common helper routines not defined.\n"); return -EFAULT; } @@ -4064,7 +4071,7 @@ static int init_one_instance(struct amd64_pvt *pvt) mci->pvt_info = pvt; mci->pdev = &pvt->F3->dev; - setup_mci_misc_attrs(mci); + pvt->ops->setup_mci_misc_attrs(mci); if (init_csrows(mci)) mci->edac_cap = EDAC_FLAG_NONE; diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index 0e0715a16981..1ffee0009a53 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h @@ -472,6 +472,7 @@ struct low_ops { bool (*ecc_enabled)(struct amd64_pvt *pvt); unsigned long (*determine_edac_cap)(struct amd64_pvt *pvt); void (*determine_edac_ctl_cap)(struct mem_ctl_info *mci, struct amd64_pvt *pvt); + void (*setup_mci_misc_attrs)(struct mem_ctl_info *mci); }; int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset, -- 2.25.1