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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Feb 2022 16:14:34.0148 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d657bce7-7171-4516-3edb-08d9fad568af X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT051.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4797 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Muralidhara M K Add function pointer for get_mc_regs() in pvt->ops and assign family specific get_mc_regs() definitions appropriately. Signed-off-by: Muralidhara M K Signed-off-by: Naveen Krishna Chatradhi --- This patch is created by splitting the 5/12th patch in series [v7 5/12] https://patchwork.kernel.org/project/linux-edac/patch/20220203174942.31630-6-nchatrad@amd.com/ drivers/edac/amd64_edac.c | 77 +++++++++++++++++++++------------------ drivers/edac/amd64_edac.h | 1 + 2 files changed, 43 insertions(+), 35 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 69c33eb17e4f..713ffe763e64 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -3214,6 +3214,27 @@ static void f17_determine_ecc_sym_sz(struct amd64_pvt *pvt) } } +static void read_top_mem_registers(struct amd64_pvt *pvt) +{ + u64 msr_val; + + /* + * Retrieve TOP_MEM and TOP_MEM2; no masking off of reserved bits since + * those are Read-As-Zero. + */ + rdmsrl(MSR_K8_TOP_MEM1, pvt->top_mem); + edac_dbg(0, " TOP_MEM: 0x%016llx\n", pvt->top_mem); + + /* Check first whether TOP_MEM2 is enabled: */ + rdmsrl(MSR_AMD64_SYSCFG, msr_val); + if (msr_val & BIT(21)) { + rdmsrl(MSR_K8_TOP_MEM2, pvt->top_mem2); + edac_dbg(0, " TOP_MEM2: 0x%016llx\n", pvt->top_mem2); + } else { + edac_dbg(0, " TOP_MEM2 disabled\n"); + } +} + /* * Retrieve the hardware registers of the memory controller. */ @@ -3235,6 +3256,8 @@ static void __read_mc_regs_df(struct amd64_pvt *pvt) amd_smn_read(nid, umc_base + UMCCH_ECC_CTRL, &umc->ecc_ctrl); amd_smn_read(nid, umc_base + UMCCH_UMC_CAP_HI, &umc->umc_cap_hi); } + + amd64_read_pci_cfg(pvt->F0, DF_DHAR, &pvt->dhar); } /* @@ -3244,30 +3267,8 @@ static void __read_mc_regs_df(struct amd64_pvt *pvt) static void read_mc_regs(struct amd64_pvt *pvt) { unsigned int range; - u64 msr_val; - /* - * Retrieve TOP_MEM and TOP_MEM2; no masking off of reserved bits since - * those are Read-As-Zero. - */ - rdmsrl(MSR_K8_TOP_MEM1, pvt->top_mem); - edac_dbg(0, " TOP_MEM: 0x%016llx\n", pvt->top_mem); - - /* Check first whether TOP_MEM2 is enabled: */ - rdmsrl(MSR_AMD64_SYSCFG, msr_val); - if (msr_val & BIT(21)) { - rdmsrl(MSR_K8_TOP_MEM2, pvt->top_mem2); - edac_dbg(0, " TOP_MEM2: 0x%016llx\n", pvt->top_mem2); - } else { - edac_dbg(0, " TOP_MEM2 disabled\n"); - } - - if (pvt->umc) { - __read_mc_regs_df(pvt); - amd64_read_pci_cfg(pvt->F0, DF_DHAR, &pvt->dhar); - - goto skip; - } + read_top_mem_registers(pvt); amd64_read_pci_cfg(pvt->F3, NBCAP, &pvt->nbcap); @@ -3308,16 +3309,6 @@ static void read_mc_regs(struct amd64_pvt *pvt) amd64_read_dct_pci_cfg(pvt, 1, DCLR0, &pvt->dclr1); amd64_read_dct_pci_cfg(pvt, 1, DCHR0, &pvt->dchr1); } - -skip: - pvt->ops->prep_chip_selects(pvt); - - pvt->ops->get_base_mask(pvt); - - pvt->ops->determine_memory_type(pvt); - edac_dbg(1, " DIMM type: %s\n", edac_mem_types[pvt->dram_type]); - - pvt->ops->determine_ecc_sym_sz(pvt); } /* @@ -3792,6 +3783,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->prep_chip_selects = k8_prep_chip_selects; pvt->ops->determine_memory_type = f1x_determine_memory_type; pvt->ops->determine_ecc_sym_sz = f1x_determine_ecc_sym_sz; + pvt->ops->get_mc_regs = read_mc_regs; break; case 0x10: @@ -3805,6 +3797,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->prep_chip_selects = default_prep_chip_selects; pvt->ops->determine_memory_type = f1x_determine_memory_type; pvt->ops->determine_ecc_sym_sz = f1x_determine_ecc_sym_sz; + pvt->ops->get_mc_regs = read_mc_regs; break; case 0x15: @@ -3834,6 +3827,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->get_base_mask = read_dct_base_mask; pvt->ops->determine_memory_type = f1x_determine_memory_type; pvt->ops->determine_ecc_sym_sz = f1x_determine_ecc_sym_sz; + pvt->ops->get_mc_regs = read_mc_regs; break; case 0x16: @@ -3853,6 +3847,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->prep_chip_selects = default_prep_chip_selects; pvt->ops->determine_memory_type = f1x_determine_memory_type; pvt->ops->determine_ecc_sym_sz = f1x_determine_ecc_sym_sz; + pvt->ops->get_mc_regs = read_mc_regs; break; case 0x17: @@ -3886,6 +3881,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->prep_chip_selects = f17_prep_chip_selects; pvt->ops->determine_memory_type = f17_determine_memory_type; pvt->ops->determine_ecc_sym_sz = f17_determine_ecc_sym_sz; + pvt->ops->get_mc_regs = __read_mc_regs_df; if (pvt->fam == 0x18) { pvt->ctl_name = "F18h"; @@ -3925,6 +3921,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->prep_chip_selects = f17_prep_chip_selects; pvt->ops->determine_memory_type = f17_determine_memory_type; pvt->ops->determine_ecc_sym_sz = f17_determine_ecc_sym_sz; + pvt->ops->get_mc_regs = __read_mc_regs_df; break; default: @@ -3935,7 +3932,8 @@ static int per_family_init(struct amd64_pvt *pvt) /* ops required for all the families */ if (!pvt->ops->early_channel_count || !pvt->ops->dbam_to_cs || !pvt->ops->get_base_mask || !pvt->ops->prep_chip_selects || - !pvt->ops->determine_memory_type || !pvt->ops->determine_ecc_sym_sz) { + !pvt->ops->determine_memory_type || !pvt->ops->determine_ecc_sym_sz || + !pvt->ops->get_mc_regs) { edac_dbg(1, "Common helper routines not defined.\n"); return -EFAULT; } @@ -3972,7 +3970,16 @@ static int hw_info_get(struct amd64_pvt *pvt) if (ret) return ret; - read_mc_regs(pvt); + pvt->ops->get_mc_regs(pvt); + + pvt->ops->prep_chip_selects(pvt); + + pvt->ops->get_base_mask(pvt); + + pvt->ops->determine_memory_type(pvt); + edac_dbg(1, " DIMM type: %s\n", edac_mem_types[pvt->dram_type]); + + pvt->ops->determine_ecc_sym_sz(pvt); return 0; } diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index f6769148d8b7..1b6df33bb0a8 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h @@ -468,6 +468,7 @@ struct low_ops { void (*prep_chip_selects)(struct amd64_pvt *pvt); void (*determine_memory_type)(struct amd64_pvt *pvt); void (*determine_ecc_sym_sz)(struct amd64_pvt *pvt); + void (*get_mc_regs)(struct amd64_pvt *pvt); }; int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset, -- 2.25.1