From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D4D5BC433EF for ; Tue, 1 Mar 2022 01:48:23 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 31B0583C99; Tue, 1 Mar 2022 02:48:06 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="p4sA2TBc"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 46F1983CA0; Tue, 1 Mar 2022 02:48:02 +0100 (CET) Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [IPv6:2a00:1450:4864:20::629]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 1F23D83C6E for ; Tue, 1 Mar 2022 02:47:58 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=jbx6244@gmail.com Received: by mail-ej1-x629.google.com with SMTP id hw13so28415560ejc.9 for ; Mon, 28 Feb 2022 17:47:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=z2ag0IQywVT5upB0M23uSoyahEasYPCiI2DvA2NxjKs=; b=p4sA2TBcXcFSJz19Tu30CfEKDjX3nilsOg+pTCrNNwhjfWshUhsYDGiSwFHB3iuvxh 9X8js9D5vDNCjqgxpMYDxjdRlB+1Z8sJ2brE8ezyUVi/WAVPpJ4YCvnNVd3aRw2VPZVF Gx0+8lofx1MTnxZUtHV+4KC9bRFEttVUOxAcpWzr5jv3puzB68gvsCTHMyHjJmfR2/OE ulkQ1PmDQ6RUKI8coXyQ6ElEdb7TDGdPf9vZd7IeWWG+b5q+Xk0vMikDWV4dcvyo7iig +WtF6W6v8WtUpNjikTghAWxdheJlox7HaMud6Xt+BWvtp5LoLCzOrL2BJ+oFnqc9gklr X/nQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=z2ag0IQywVT5upB0M23uSoyahEasYPCiI2DvA2NxjKs=; b=JGVpcRwlbpMXCF/RcUA/TXsY30/AOwNzCdWAWex5HP2lA4BJ+uxGw9R+39U5KBTabs vE0XlvOZCnJv1i3EJKLOgXsTNOvgBG4UpSnxr6/a4JkHeiaX1OCjsJGkao9Pq7sszMtF c7aFu10r+mD00Y8MtE6OvuARlqLNmilvAzWQ9B9CUQANvs23edZK7wGKSq4XnmWR5evI kEhM5sBxqDqSNfWFU0B1NKa3vcwzz/Ygyy86Dl4qnVoancy+C8lD3irKkBOJya4TlcY0 Yzj6qtRH+bmAsL9oNzIU1Jsq0nXPREUVajxvdZy4j48JxgHepfrOicfFtUFLCxDZ9WZy NoEg== X-Gm-Message-State: AOAM532XZeXNLoUBfQX3IUx73jeDEFyDn7+HCyDXWC+7dL3+OX4BmI2j fd+LryXUGXvhBaY2eDOOTTc= X-Google-Smtp-Source: ABdhPJzyg/cxJ1BimmUSFVSRlayRI42R5tx5NdvncEszD98OLZvDA8u4gXfZZHlb5AhVNhtMaj4irQ== X-Received: by 2002:a17:907:766e:b0:6cf:d1d1:db1d with SMTP id kk14-20020a170907766e00b006cfd1d1db1dmr17069106ejc.503.1646099277581; Mon, 28 Feb 2022 17:47:57 -0800 (PST) Received: from debian.home (81-204-249-205.fixed.kpn.net. [81.204.249.205]) by smtp.gmail.com with ESMTPSA id g9-20020aa7c849000000b00412fc6bf26dsm6816738edt.80.2022.02.28.17.47.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Feb 2022 17:47:57 -0800 (PST) From: Johan Jonker To: kever.yang@rock-chips.com Cc: sjg@chromium.org, philipp.tomsich@vrull.eu, u-boot@lists.denx.de, w.egorov@phytec.de, hl@rock-chips.com, jagan@amarulasolutions.com, heiko@sntech.de Subject: [PATCH v2 02/12] rockchip: rk3228-cru: sync the clock dt-binding header from Linux Date: Tue, 1 Mar 2022 02:47:39 +0100 Message-Id: <20220301014749.6446-2-jbx6244@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220301014749.6446-1-jbx6244@gmail.com> References: <20220301014749.6446-1-jbx6244@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean In order to update the DT for rk3228 sync the clock dt-binding header. This is the state as of v5.17 in Linux. Signed-off-by: Johan Jonker Reviewed-by: Simon Glass --- include/dt-bindings/clock/rk3228-cru.h | 54 +++++++++++++++++++++++++- 1 file changed, 52 insertions(+), 2 deletions(-) diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h index 1217d523..de550ea5 100644 --- a/include/dt-bindings/clock/rk3228-cru.h +++ b/include/dt-bindings/clock/rk3228-cru.h @@ -1,6 +1,7 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* - * (C) Copyright 2017 Rockchip Electronics Co., Ltd. + * Copyright (c) 2015 Rockchip Electronics Co. Ltd. + * Author: Jeffy Chen */ #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H @@ -39,6 +40,7 @@ #define SCLK_EMMC_DRV 117 #define SCLK_SDMMC_SAMPLE 118 #define SCLK_SDIO_SAMPLE 119 +#define SCLK_SDIO_SRC 120 #define SCLK_EMMC_SAMPLE 121 #define SCLK_VOP 122 #define SCLK_HDMI_HDCP 123 @@ -51,6 +53,18 @@ #define SCLK_MAC_TX 130 #define SCLK_MAC_PHY 131 #define SCLK_MAC_OUT 132 +#define SCLK_VDEC_CABAC 133 +#define SCLK_VDEC_CORE 134 +#define SCLK_RGA 135 +#define SCLK_HDCP 136 +#define SCLK_HDMI_CEC 137 +#define SCLK_CRYPTO 138 +#define SCLK_TSP 139 +#define SCLK_HSADC 140 +#define SCLK_WIFI 141 +#define SCLK_OTGPHY0 142 +#define SCLK_OTGPHY1 143 +#define SCLK_HDMI_PHY 144 /* dclk gates */ #define DCLK_VOP 190 @@ -58,15 +72,32 @@ /* aclk gates */ #define ACLK_DMAC 194 +#define ACLK_CPU 195 +#define ACLK_VPU_PRE 196 +#define ACLK_RKVDEC_PRE 197 +#define ACLK_RGA_PRE 198 +#define ACLK_IEP_PRE 199 +#define ACLK_HDCP_PRE 200 +#define ACLK_VOP_PRE 201 +#define ACLK_VPU 202 +#define ACLK_RKVDEC 203 +#define ACLK_IEP 204 +#define ACLK_RGA 205 +#define ACLK_HDCP 206 #define ACLK_PERI 210 #define ACLK_VOP 211 #define ACLK_GMAC 212 +#define ACLK_GPU 213 /* pclk gates */ #define PCLK_GPIO0 320 #define PCLK_GPIO1 321 #define PCLK_GPIO2 322 #define PCLK_GPIO3 323 +#define PCLK_VIO_H2P 324 +#define PCLK_HDCP 325 +#define PCLK_EFUSE_1024 326 +#define PCLK_EFUSE_256 327 #define PCLK_GRF 329 #define PCLK_I2C0 332 #define PCLK_I2C1 333 @@ -79,6 +110,7 @@ #define PCLK_TSADC 344 #define PCLK_PWM 350 #define PCLK_TIMER 353 +#define PCLK_CPU 354 #define PCLK_PERI 363 #define PCLK_HDMI_CTRL 364 #define PCLK_HDMI_PHY 365 @@ -94,6 +126,24 @@ #define HCLK_SDMMC 456 #define HCLK_SDIO 457 #define HCLK_EMMC 459 +#define HCLK_CPU 460 +#define HCLK_VPU_PRE 461 +#define HCLK_RKVDEC_PRE 462 +#define HCLK_VIO_PRE 463 +#define HCLK_VPU 464 +#define HCLK_RKVDEC 465 +#define HCLK_VIO 466 +#define HCLK_RGA 467 +#define HCLK_IEP 468 +#define HCLK_VIO_H2P 469 +#define HCLK_HDCP_MMU 470 +#define HCLK_HOST0 471 +#define HCLK_HOST1 472 +#define HCLK_HOST2 473 +#define HCLK_OTG 474 +#define HCLK_TSP 475 +#define HCLK_M_CRYPTO 476 +#define HCLK_S_CRYPTO 477 #define HCLK_PERI 478 #define CLK_NR_CLKS (HCLK_PERI + 1) -- 2.20.1