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[2603:6081:7b01:cbda:2ef0:5dff:fedb:a8ba]) by smtp.gmail.com with ESMTPSA id q9-20020a05622a030900b002dd2c3a9fccsm239459qtw.38.2022.03.02.14.41.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Mar 2022 14:41:15 -0800 (PST) Date: Wed, 2 Mar 2022 17:41:13 -0500 From: Tom Rini To: Andre Przywara Cc: Simon Glass , Heinrich Schuchardt , Michael Walle , Nishanth Menon , Alison Wang , Peter Hoyes , Marek Vasut , Priyanka Jain , Priyanka Singh , Mark Kettenis , u-boot@lists.denx.de Subject: Re: [PATCH v2 2/6] armv8: Always unmask SErrors Message-ID: <20220302224113.GV5020@bill-the-cat> References: <20220211112939.1327953-1-andre.przywara@arm.com> <20220211112939.1327953-3-andre.przywara@arm.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="AQYPrgrEUc/1pSX1" Content-Disposition: inline In-Reply-To: <20220211112939.1327953-3-andre.przywara@arm.com> X-Clacks-Overhead: GNU Terry Pratchett X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean --AQYPrgrEUc/1pSX1 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Feb 11, 2022 at 11:29:35AM +0000, Andre Przywara wrote: > The ARMv8 architecture describes the "SError interrupt" as the fourth > kind of exception, next to synchronous exceptions, IRQs, and FIQs. > Those SErrors signal exceptional conditions from which the system might > not easily recover, and are normally generated by the interconnect as a > response to some bus error. A typical situation is access to a > non-existing memory address or device, but it might be deliberately > triggered by a device as well. > The SError interrupt replaces the Armv7 asynchronous abort. >=20 > Trusted Firmware enters U-Boot (BL33) typically with SErrors masked, > and we never enable them. However any SError condition still triggers > the SError interrupt, and this condition stays pending, it just won't be > handled. If now later on the Linux kernel unmasks the "A" bit in PState, > it will immediately take the exception, leading to a kernel crash. > This leaves many people scratching their head about the reason for > this, and leads to long debug sessions, possibly looking at the wrong > places (the kernel, but not U-Boot). >=20 > To avoid the situation, just unmask SErrors early in the ARMv8 boot > process, so that the U-Boot exception handlers reports them in a timely > manner. As SErrors are typically asynchronous, the register dump does > not need to point at the actual culprit, but it should happen very > shortly after the condition. >=20 > For those exceptions to be taken, we also need to route them to EL2, > if U-Boot is running in this exception level. >=20 > This removes the respective code snippet from the Freescale lowlevel > routine, as this is now handled in generic ARMv8 code. >=20 > Reported-by: Nishanth Menon > Signed-off-by: Andre Przywara Applied to u-boot/next, thanks! --=20 Tom --AQYPrgrEUc/1pSX1 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQGzBAABCgAdFiEEGjx/cOCPqxcHgJu/FHw5/5Y0tywFAmIf8okACgkQFHw5/5Y0 tywPTQwAhz3XQVnACtlfkezrXTbVv4b5L7/RC1ZSetRJzLTgdXRyaJm8sGhUfvh1 Zoudx/y2DfX8v9UcYRL+Wnbz/PEDlkD3a0HRWPrf3w/nV8M1f6rmptjxtOOQ6b7i wsCURSnVXxfhAFaCn7Cq2ofGQP2oE3mdrkdTKmQPOX2ZXL9Pt/iC4ur+w9yhwUBX RnltF+mIsRBpaf2KwuzbYvYEaQIHYCH10YmIClQ0bAT1OkzeHHwsDQlIeEW0BWn1 sOC2P1HOO5nN/MNrYo3ZsMRYK/kz8vGWsvnRKkdrn5+58RZ39qaH/V/KVnHypKOh hzKvDDozN/ra9zF3ZCp9F8V9DuBNHVeahUijA4AMuwJtOgTujxrEZw8z4Qga4GyZ V4r/SqiY3dVe71Q3NHOIZSWkpfyiY9PbZmBupRjsIg4QJLjJpu2SYPJ3B+arIbNS NfGu/2aiQ4HzM5f8/VkGd8+k052ptRmUhIIRMEwDooFI7gCrds0xXEaievxJ+4qe qe7AwPec =2x+x -----END PGP SIGNATURE----- --AQYPrgrEUc/1pSX1--