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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 17/18] target/arm: Provide cpu property for controling FEAT_LPA2
Date: Mon,  7 Mar 2022 16:47:08 +0000	[thread overview]
Message-ID: <20220307164709.2503250-18-peter.maydell@linaro.org> (raw)
In-Reply-To: <20220307164709.2503250-1-peter.maydell@linaro.org>

From: Richard Henderson <richard.henderson@linaro.org>

There is a Linux kernel bug present until v5.12 that prevents
booting with FEAT_LPA2 enabled.  As a workaround for TCG, allow
the feature to be disabled from -cpu max.

Since this kernel bug is present in the Fedora 31 image that
we test in avocado, disable lpa2 on the command-line.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h            |  5 ++++-
 target/arm/cpu.c            |  6 ++++++
 target/arm/cpu64.c          | 24 ++++++++++++++++++++++++
 tests/avocado/boot_linux.py |  2 ++
 4 files changed, 36 insertions(+), 1 deletion(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 24d9fff1705..4aa70ceca12 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -204,10 +204,12 @@ typedef struct {
 # define ARM_MAX_VQ    16
 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
 void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
+void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp);
 #else
 # define ARM_MAX_VQ    1
 static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { }
 static inline void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { }
+static inline void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) { }
 #endif
 
 typedef struct ARMVectorReg {
@@ -975,10 +977,11 @@ struct ARMCPU {
 
     /*
      * Intermediate values used during property parsing.
-     * Once finalized, the values should be read from ID_AA64ISAR1.
+     * Once finalized, the values should be read from ID_AA64*.
      */
     bool prop_pauth;
     bool prop_pauth_impdef;
+    bool prop_lpa2;
 
     /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
     uint32_t dcz_blocksize;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 7091684a16d..185d4e774d5 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1392,6 +1392,12 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp)
             error_propagate(errp, local_err);
             return;
         }
+
+        arm_cpu_lpa2_finalize(cpu, &local_err);
+        if (local_err != NULL) {
+            error_propagate(errp, local_err);
+            return;
+        }
     }
 
     if (kvm_enabled()) {
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 2fdc16bf182..eb44c05822c 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -688,6 +688,29 @@ void aarch64_add_pauth_properties(Object *obj)
     }
 }
 
+static Property arm_cpu_lpa2_property =
+    DEFINE_PROP_BOOL("lpa2", ARMCPU, prop_lpa2, true);
+
+void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp)
+{
+    uint64_t t;
+
+    /*
+     * We only install the property for tcg -cpu max; this is the
+     * only situation in which the cpu field can be true.
+     */
+    if (!cpu->prop_lpa2) {
+        return;
+    }
+
+    t = cpu->isar.id_aa64mmfr0;
+    t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 2);   /* 16k pages w/ LPA2 */
+    t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4, 1);    /*  4k pages w/ LPA2 */
+    t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 3); /* 16k stage2 w/ LPA2 */
+    t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 3);  /*  4k stage2 w/ LPA2 */
+    cpu->isar.id_aa64mmfr0 = t;
+}
+
 static void aarch64_host_initfn(Object *obj)
 {
 #if defined(CONFIG_KVM)
@@ -897,6 +920,7 @@ static void aarch64_max_initfn(Object *obj)
     aarch64_add_sve_properties(obj);
     object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
                         cpu_max_set_sve_max_vq, NULL, NULL);
+    qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property);
 }
 
 static void aarch64_a64fx_initfn(Object *obj)
diff --git a/tests/avocado/boot_linux.py b/tests/avocado/boot_linux.py
index ab19146d1ee..ee584d2fdf2 100644
--- a/tests/avocado/boot_linux.py
+++ b/tests/avocado/boot_linux.py
@@ -79,6 +79,7 @@ def test_virt_tcg_gicv2(self):
         """
         self.require_accelerator("tcg")
         self.vm.add_args("-accel", "tcg")
+        self.vm.add_args("-cpu", "max,lpa2=off")
         self.vm.add_args("-machine", "virt,gic-version=2")
         self.add_common_args()
         self.launch_and_wait(set_up_ssh_connection=False)
@@ -91,6 +92,7 @@ def test_virt_tcg_gicv3(self):
         """
         self.require_accelerator("tcg")
         self.vm.add_args("-accel", "tcg")
+        self.vm.add_args("-cpu", "max,lpa2=off")
         self.vm.add_args("-machine", "virt,gic-version=3")
         self.add_common_args()
         self.launch_and_wait(set_up_ssh_connection=False)
-- 
2.25.1



  parent reply	other threads:[~2022-03-07 16:53 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-07 16:46 [PULL 00/18] target-arm queue Peter Maydell
2022-03-07 16:46 ` [PULL 01/18] util: Make qemu_oom_check() a static function Peter Maydell
2022-03-07 16:46 ` [PULL 02/18] util: Unify implementations of qemu_memalign() Peter Maydell
2022-03-07 16:46 ` [PULL 03/18] util: Return valid allocation for qemu_try_memalign() with zero size Peter Maydell
2022-03-07 16:46 ` [PULL 04/18] meson.build: Don't misdetect posix_memalign() on Windows Peter Maydell
2022-03-07 16:46 ` [PULL 05/18] util: Share qemu_try_memalign() implementation between POSIX and Windows Peter Maydell
2022-03-07 16:46 ` [PULL 06/18] util: Use meson checks for valloc() and memalign() presence Peter Maydell
2022-03-07 16:46 ` [PULL 07/18] util: Put qemu_vfree() in memalign.c Peter Maydell
2022-03-07 16:46 ` [PULL 08/18] osdep: Move memalign-related functions to their own header Peter Maydell
2022-03-07 16:47 ` [PULL 09/18] target/arm/translate-neon: UNDEF if VLD1/VST1 stride bits are non-zero Peter Maydell
2022-03-07 16:47 ` [PULL 10/18] target/arm/translate-neon: Simplify align field check for VLD3 Peter Maydell
2022-03-07 16:47 ` [PULL 11/18] hw/intc/arm_gicv3_its: Add trace events for commands Peter Maydell
2022-03-07 16:47 ` [PULL 12/18] hw/intc/arm_gicv3_its: Add trace events for table reads and writes Peter Maydell
2022-03-07 16:47 ` [PULL 13/18] hw/intc/arm_gicv3: Specify valid and impl in MemoryRegionOps Peter Maydell
2022-03-07 16:47 ` [PULL 14/18] hw/intc/arm_gicv3: Fix missing spaces in error log messages Peter Maydell
2022-03-07 16:47 ` [PULL 15/18] hw/intc/arm_gicv3_cpuif: Fix register names in ICV_HPPIR read trace event Peter Maydell
2022-03-07 16:47 ` [PULL 16/18] ui/cocoa: Use the standard about panel Peter Maydell
2022-03-07 16:47 ` Peter Maydell [this message]
2022-03-07 16:47 ` [PULL 18/18] hw/arm/virt: Disable LPA2 for -machine virt-6.2 Peter Maydell
2022-03-08 17:08 ` [PULL 00/18] target-arm queue Peter Maydell

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