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Date: Tue, 8 Mar 2022 10:39:14 -0600 Message-ID: <20220308163926.563994-1-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5a7cc6a0-b9e4-44b7-68e4-08da01223f14 X-MS-TrafficTypeDiagnostic: DM6PR12MB3163:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: vilGkCKKlxpBoJpYZFiMwJxykjoXB4odxhHwrjMjGXlTISi8p/Mokam994igYC2rhu3JCNo87bVanZ84z8/t8CdsUA+eXoTr6MhRs8vLbwzW1h/rPDAH340fP1T+RfdSnQQKcqNEJNzN5jiMYpVJ/ONGW/tdwOYm4eE+Q/XvVEmY0BicRWpvJcq3jlLDuZ0Tx/mX2n3IG0nyV47AHziFMHIo33RKGbgHlKmTwMlHc+MjsQ4mdUhjx6syogEnb8Z7TZohpu5iwCbFkfpTBynTc4hg5jsg70YJCPShVsOttKrrUNJJUQhquSOdnuAzvYnr5J6bk7TjG6AMogT9PDX7MvTzTK0V4GahszaaTCYsMjoRi/WdCQpr6ODhOPVzTZ29PIZ3R9fyWkEh6d6htQPzYfAKTmhHRO2J2M0AUtbXrP0+GaXZHloa5XpqwMgaQWNkfBEvvmfm9vEqEhtX8zSwa+1nWhaQ6gewA2i+8i4zlP4FH6PLdtFtigqUoxngBnou0JF/lwkJ+Km3yr/US/Ky4LJQgYa+TfGXO29XCHN7DoJMlKLfgegpAXtcSgOtPUEtSoV/qyYNT2k7GReeFtAM41SOhstocuD4UXWuRvv+KWKip3q4un1jpzyxo/S8InUFcRfnh5IkfnRSHUvz2wTTdiy50MYGOeEZom6J3w545G//OaV5/8V30qmjlVqxhSHwcPraFHYRVdZWf4rWQOJXG0YrXOPXHx/alSIu9olj+x8ovyWibZPAYoc6soZJNnqeBvluoo7eBHEITo6sJ3TiwGuiSS49JAsYqU81GWGW3zQ= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230001)(4636009)(40470700004)(46966006)(36840700001)(426003)(336012)(16526019)(6666004)(40460700003)(2906002)(36756003)(26005)(54906003)(110136005)(47076005)(186003)(2616005)(316002)(1076003)(81166007)(83380400001)(7696005)(86362001)(36860700001)(44832011)(8676002)(70586007)(82310400004)(4326008)(5660300002)(70206006)(356005)(8936002)(508600001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Mar 2022 16:39:42.4539 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5a7cc6a0-b9e4-44b7-68e4-08da01223f14 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT012.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3163 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Previously, with AVIC, guest needs to disable x2APIC capability and can only run in APIC mode to activate hardware-accelerated interrupt virtualization. With x2AVIC, guest can run in x2APIC mode. This feature is indicated by the CPUID Fn8000_000A EDX[14], and it can be activated by setting bit 31 (enable AVIC) and bit 30 (x2APIC mode) of VMCB offset 60h. The mode of interrupt virtualization can dynamically change during runtime. For example, when AVIC is enabled, the hypervisor currently keeps track of the AVIC activation and set the VMCB bit 31 accordingly. With x2AVIC, the guest OS can also switch between APIC and x2APIC modes during runtime. The kvm_amd driver needs to also keep track and set the VMCB bit 30 accordingly. Besides, for x2AVIC, kvm_amd driver needs to disable interception for the x2APIC MSR range to allow AVIC hardware to virtualize register accesses. Testing: * This series has been tested booting a Linux VM with x2APIC physical and logical modes upto 512 vCPUs. Regards, Suravee Change from RFCv1 (https://lkml.org/lkml/2022/2/20/435) * Mostly update the series based on review comments from Maxim. * Patch 2/12 is new to the series * Patch 3/12 removes unused helper function. * Patch 6/12 update commit message w/ the expected hardware behavior when writing to x2APIC LDR register to address a concern in the review comment. * Patch 7/12 has been redesigned to return proper error code and move the function definition to arch/x86/kvm/lapic.c. * Patch 9/12 moves logic into svm_set_virtual_apic_mode(). * Patch 11/12 separates the warning removal into a separate patch w/ detail description. * Remove non-x2AVIC related patches, which will be sent separately. Suravee Suthikulpanit (12): x86/cpufeatures: Introduce x2AVIC CPUID bit KVM: x86: lapic: Rename [GET/SET]_APIC_DEST_FIELD to [GET/SET]_XAPIC_DEST_FIELD KVM: SVM: Detect X2APIC virtualization (x2AVIC) support KVM: SVM: Update max number of vCPUs supported for x2AVIC mode KVM: SVM: Update avic_kick_target_vcpus to support 32-bit APIC ID KVM: SVM: Do not update logical APIC ID table when in x2APIC mode KVM: SVM: Introduce helper function kvm_get_apic_id KVM: SVM: Adding support for configuring x2APIC MSRs interception KVM: SVM: Refresh AVIC settings when changing APIC mode KVM: SVM: Introduce helper functions to (de)activate AVIC and x2AVIC KVM: SVM: Do not throw warning when calling avic_vcpu_load on a running vcpu KVM: SVM: Do not inhibit APICv when x2APIC is present arch/x86/hyperv/hv_apic.c | 2 +- arch/x86/include/asm/apicdef.h | 4 +- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/svm.h | 16 ++- arch/x86/kernel/apic/apic.c | 2 +- arch/x86/kernel/apic/ipi.c | 2 +- arch/x86/kvm/lapic.c | 25 ++++- arch/x86/kvm/lapic.h | 5 +- arch/x86/kvm/svm/avic.c | 171 ++++++++++++++++++++++++++--- arch/x86/kvm/svm/svm.c | 93 +++++++++------- arch/x86/kvm/svm/svm.h | 9 ++ 11 files changed, 262 insertions(+), 68 deletions(-) -- 2.25.1