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Wed, 09 Mar 2022 04:00:29 -0800 From: Bharat Kumar Gogada To: , , CC: , , , , Bharat Kumar Gogada Subject: [PATCH v3 0/2] Add support for Xilinx Versal CPM5 Root Port Date: Wed, 9 Mar 2022 17:30:23 +0530 Message-ID: <20220309120025.6721-1-bharat.kumar.gogada@xilinx.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 99e6a699-0c3d-4789-2300-08da01c46b32 X-MS-TrafficTypeDiagnostic: SA2PR02MB7562:EE_ X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ONqyR3gRO8kjOf1mcofUOIxvPguKy9AkkfCrcLhgvHYRry08go++Cx+lD3BKEZH0vQn6AeNkdZkLM5aLtLfICYBrBnvqDTVzdKcA6S0UIod+LKnCMlHetUVne7lIj413qDbW0aYWKThY8tWfQ6NnPG2vScpoWwsbvMeno8WaAgcwGXL804ftCEqjsFQD5K1CD3YpUrY+u4UtHETvdydoSZEKWzLMXiusNUm/AMTcBL993UqPw/G7BY2A5xIZZ5VbO1nEXYnSps8xV03KZwPzUXWFEIfYAzETUrYbXhqlkY855l6OafVdzoCmesQBa7RAknpZj2322fhrHoP3bDPhPars3Dbsfm+If5BLeSgShhyj+kaXjl8tQUlFosjPRxUpQCKQwIED8gi/QXqIadR5iuWLmikvQcQlNR/SCJIpTPNdy+9NQDS8eqCCpb96b7By7x+aHQ0uaiwD5CsyKXhJY7q5g9JAbWdmfM3Psbq7MpIsjRUrhpb2zW4aT0B0+cWmzHvtxlUSy71t5nwTHIlUsk+fZDCnzaoCvWAa6tisOnxszosP/KJ0x8uELVD9GCXZg6cn/PWu0r0CvBsuhqa5+yoq0P7uPVBFKr4N8SFsTc48kPLP70Ruj1flvLphyDwQ7insrOOdgU6cCUIxCl601cVWobgysonomTUvOkF9zxmBFjfgeDvQPPvYO4UlimmsH4rcV+ayRJ8EpwJvxcNzuA== X-Forefront-Antispam-Report: CIP:149.199.62.198;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:xsj-pvapexch01.xlnx.xilinx.com;PTR:unknown-62-198.xilinx.com;CAT:NONE;SFS:(13230001)(4636009)(40470700004)(36840700001)(46966006)(8676002)(70206006)(36756003)(83380400001)(40460700003)(103116003)(5660300002)(82310400004)(70586007)(4326008)(9786002)(4744005)(2906002)(110136005)(316002)(54906003)(8936002)(6666004)(7696005)(426003)(26005)(2616005)(186003)(107886003)(336012)(1076003)(7636003)(356005)(47076005)(36860700001)(508600001)(102446001);DIR:OUT;SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Mar 2022 12:00:34.9230 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 99e6a699-0c3d-4789-2300-08da01c46b32 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0033.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA2PR02MB7562 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Xilinx Versal Premium series has CPM5 block which supports Root Port functioning at Gen5 speed. Xilinx Versal CPM5 has few changes with existing CPM block. - CPM5 has dedicated register space for control and status registers. - CPM5 legacy interrupt handling needs additonal register bit to enable and handle legacy interrupts. Changes in v3: - consistency in is_cpm5 flag check expression. Bharat Kumar Gogada (2): dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port PCI: xilinx-cpm: Add support for Versal CPM5 Root Port .../bindings/pci/xilinx-versal-cpm.yaml | 47 ++++++++++++++++--- drivers/pci/controller/pcie-xilinx-cpm.c | 33 ++++++++++++- 2 files changed, 72 insertions(+), 8 deletions(-) -- 2.17.1