From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 39240C433EF for ; Wed, 9 Mar 2022 16:52:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1AAFD10E41E; Wed, 9 Mar 2022 16:52:34 +0000 (UTC) Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by gabe.freedesktop.org (Postfix) with ESMTPS id 718BB10E402 for ; Wed, 9 Mar 2022 16:52:32 +0000 (UTC) Received: by mail-yb1-xb49.google.com with SMTP id h8-20020a25e208000000b00628c0565607so2182765ybe.0 for ; Wed, 09 Mar 2022 08:52:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc:content-transfer-encoding; bh=x8m7SXGR83/SdOdqn7l1+FIZ1cxwPNd4HTN6OzKaqJk=; b=J9yUUK6ijZr6eIlL2BkUPNKezNNqJ7Usl7l5NfD4UexBDWRVHWzo2vGRPlARJ4lHvo 4uYgUvWM74wcdGxJ3HNGAbRITNE9V2gJbWuY8AXNQD9mUbg9OMwopeX+XM2CspXyjbUx KTAkX+QzE2yF1OB/IdQd8SiGEF22/Hb7Tn/8priJRWTDMnnKvFpslUhl6ZS1sRjtMuyk ms5lStmtJDChjDoxemZ4MHYvgS7/ztUsuap9pHbthk/R4at7QOLEDSwostK2OW3tPjvk RVrsobyQqAP/RQLUZyTdKdy9gn7B01mgiOcE/nZ9hRBnG1RosXrI8mDculT4ZVlfoDZ4 Yi8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc:content-transfer-encoding; bh=x8m7SXGR83/SdOdqn7l1+FIZ1cxwPNd4HTN6OzKaqJk=; b=g7C+KTIYLm5kLTyaq4cRKIj5TZjYfGZUCOFBkoYDH4SZdu0pXZFmpS0rleJyuaAEmQ VGps3/w29ZlQR5GuACJaBJ59G+98nHJO4yURcDVgT4fW4WCV892pIn2+An21lB+6hMxT jUbblszSi9bxTotaA7pSRkJbAInysFapjRhIDhP98u20ny5c6XUQDQwvJcpELQgTbSKE rWycZKb8hlK6zzNeQ1FyI6EwhFgMlkw6X/h97FFaV3paRN0xsdzaWpTmFo43oFG7LYSK Gtk6NeUX2lx46X6wRs8c0nvWst0HgDvhvHpqFoal932fvdvioL8ZJcPEYxZaRooGXexT 2f5Q== X-Gm-Message-State: AOAM533SAvE7xQUtzJB5IlyCiiiI2azhMS56R9PoRmQ2VMhc/RgORAct PquVPmCUdouzO4ICKBudnPVQvm23jqSk4Mw= X-Google-Smtp-Source: ABdhPJwhBefo0Jr5ct437h23DSuj+1FDWXw/dIZxPZqGgOkSXpfDO+Ep1nC/b2QBICxQ0J7BmZdbcopBhFv+RU4= X-Received: from tj2.c.googlers.com ([fda3:e722:ac3:cc00:20:ed76:c0a8:187]) (user=tjmercier job=sendgmr) by 2002:a81:90d:0:b0:2db:fc82:ef40 with SMTP id 13-20020a81090d000000b002dbfc82ef40mr592122ywj.384.1646844751396; Wed, 09 Mar 2022 08:52:31 -0800 (PST) Date: Wed, 9 Mar 2022 16:52:11 +0000 In-Reply-To: <20220309165222.2843651-1-tjmercier@google.com> Message-Id: <20220309165222.2843651-2-tjmercier@google.com> Mime-Version: 1.0 References: <20220309165222.2843651-1-tjmercier@google.com> X-Mailer: git-send-email 2.35.1.616.g0bdcbb4464-goog Subject: [RFC v3 1/8] gpu: rfc: Proposal for a GPU cgroup controller From: "T.J. Mercier" To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Jonathan Corbet , Greg Kroah-Hartman , "=?UTF-8?q?Arve=20Hj=C3=B8nnev=C3=A5g?=" , Todd Kjos , Martijn Coenen , Joel Fernandes , Christian Brauner , Hridya Valsaraju , Suren Baghdasaryan , Sumit Semwal , "=?UTF-8?q?Christian=20K=C3=B6nig?=" , Benjamin Gaignard , Liam Mark , Laura Abbott , Brian Starkey , John Stultz , Tejun Heo , Zefan Li , Johannes Weiner , Shuah Khan Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-doc@vger.kernel.org, Kenny.Ho@amd.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linaro-mm-sig@lists.linaro.org, linux-kselftest@vger.kernel.org, kaleshsingh@google.com, cgroups@vger.kernel.org, "T.J. Mercier" , linux-media@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Hridya Valsaraju This patch adds a proposal for a new GPU cgroup controller for accounting/limiting GPU and GPU-related memory allocations. The proposed controller is based on the DRM cgroup controller[1] and follows the design of the RDMA cgroup controller. The new cgroup controller would: * Allow setting per-cgroup limits on the total size of buffers charged to it. * Allow setting per-device limits on the total size of buffers allocated by device within a cgroup. * Expose a per-device/allocator breakdown of the buffers charged to a cgroup. The prototype in the following patches is only for memory accounting using the GPU cgroup controller and does not implement limit setting. [1]: https://lore.kernel.org/amd-gfx/20210126214626.16260-1-brian.welty@int= el.com/ Signed-off-by: Hridya Valsaraju Signed-off-by: T.J. Mercier --- v3 changes Remove Upstreaming Plan from gpu-cgroup.rst per John Stultz. Use more common dual author commit message format per John Stultz. --- Documentation/gpu/rfc/gpu-cgroup.rst | 183 +++++++++++++++++++++++++++ Documentation/gpu/rfc/index.rst | 4 + 2 files changed, 187 insertions(+) create mode 100644 Documentation/gpu/rfc/gpu-cgroup.rst diff --git a/Documentation/gpu/rfc/gpu-cgroup.rst b/Documentation/gpu/rfc/g= pu-cgroup.rst new file mode 100644 index 000000000000..5b40d5518a5e --- /dev/null +++ b/Documentation/gpu/rfc/gpu-cgroup.rst @@ -0,0 +1,183 @@ +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +GPU cgroup controller +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Goals +=3D=3D=3D=3D=3D +This document intends to outline a plan to create a cgroup v2 controller s= ubsystem +for the per-cgroup accounting of device and system memory allocated by the= GPU +and related subsystems. + +The new cgroup controller would: + +* Allow setting per-cgroup limits on the total size of buffers charged to = it. + +* Allow setting per-device limits on the total size of buffers allocated b= y a + device/allocator within a cgroup. + +* Expose a per-device/allocator breakdown of the buffers charged to a cgro= up. + +Alternatives Considered +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The following alternatives were considered: + +The memory cgroup controller +____________________________ + +1. As was noted in [1], memory accounting provided by the GPU cgroup +controller is not a good fit for integration into memcg due to the +differences in how accounting is performed. It implements a mechanism +for the allocator attribution of GPU and GPU-related memory by +charging each buffer to the cgroup of the process on behalf of which +the memory was allocated. The buffer stays charged to the cgroup until +it is freed regardless of whether the process retains any references +to it. On the other hand, the memory cgroup controller offers a more +fine-grained charging and uncharging behavior depending on the kind of +page being accounted. + +2. Memcg performs accounting in units of pages. In the DMA-BUF buffer shar= ing model, +a process takes a reference to the entire buffer(hence keeping it alive) e= ven if +it is only accessing parts of it. Therefore, per-page memory tracking for = DMA-BUF +memory accounting would only introduce additional overhead without any ben= efits. + +[1]: https://patchwork.kernel.org/project/dri-devel/cover/20190501140438.9= 506-1-brian.welty@intel.com/#22624705 + +Userspace service to keep track of buffer allocations and releases +__________________________________________________________________ + +1. There is no way for a userspace service to intercept all allocations an= d releases. +2. In case the process gets killed or restarted, we lose all accounting so= far. + +UAPI +=3D=3D=3D=3D +When enabled, the new cgroup controller would create the following files i= n every cgroup. + +:: + + gpu.memory.current (R) + gpu.memory.max (R/W) + +gpu.memory.current is a read-only file and would contain per-device memory= allocations +in a key-value format where key is a string representing the device name +and the value is the size of memory charged to the device in the cgroup in= bytes. + +For example: + +:: + + cat /sys/kernel/fs/cgroup1/gpu.memory.current + dev1 4194304 + dev2 4194304 + +The string key for each device is set by the device driver when the device= registers +with the GPU cgroup controller to participate in resource accounting(see s= ection +'Design and Implementation' for more details). + +gpu.memory.max is a read/write file. It would show the current total +size limits on memory usage for the cgroup and the limits on total memory = usage +for each allocator/device. + +Setting a total limit for a cgroup can be done as follows: + +:: + + echo =E2=80=9Ctotal 41943040=E2=80=9D > /sys/kernel/fs/cgroup1/gpu= .memory.max + +Setting a total limit for a particular device/allocator can be done as fol= lows: + +:: + + echo =E2=80=9Cdev1 4194304=E2=80=9D > /sys/kernel/fs/cgroup1/gpu.= memory.max + +In this example, 'dev1' is the string key set by the device driver during +registration. + +Design and Implementation +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + +The cgroup controller would closely follow the design of the RDMA cgroup c= ontroller +subsystem where each cgroup maintains a list of resource pools. +Each resource pool contains a struct device and the counter to track curre= nt total, +and the maximum limit set for the device. + +The below code block is a preliminary estimation on how the core kernel da= ta structures +and APIs would look like. + +.. code-block:: c + + /** + * The GPU cgroup controller data structure. + */ + struct gpucg { + struct cgroup_subsys_state css; + + /* list of all resource pools that belong to this cgroup *= / + struct list_head rpools; + }; + + struct gpucg_device { + /* + * list of various resource pools in various cgroups that= the device is + * part of. + */ + struct list_head rpools; + + /* list of all devices registered for GPU cgroup accountin= g */ + struct list_head dev_node; + + /* name to be used as identifier for accounting and limit = setting */ + const char *name; + }; + + struct gpucg_resource_pool { + /* The device whose resource usage is tracked by this reso= urce pool */ + struct gpucg_device *device; + + /* list of all resource pools for the cgroup */ + struct list_head cg_node; + + /* + * list maintained by the gpucg_device to keep track of it= s + * resource pools + */ + struct list_head dev_node; + + /* tracks memory usage of the resource pool */ + struct page_counter total; + }; + + /** + * gpucg_register_device - Registers a device for memory accountin= g using the + * GPU cgroup controller. + * + * @device: The device to register for memory accounting. Must rem= ain valid + * after registration. + * @name: Pointer to a string literal to denote the name of the de= vice. + */ + void gpucg_register_device(struct gpucg_device *gpucg_dev, const c= har *name); + + /** + * gpucg_try_charge - charge memory to the specified gpucg and gpu= cg_device. + * + * @gpucg: The gpu cgroup to charge the memory to. + * @device: The device to charge the memory to. + * @usage: size of memory to charge in bytes. + * + * Return: returns 0 if the charging is successful and otherwise r= eturns an + * error code. + */ + int gpucg_try_charge(struct gpucg *gpucg, struct gpucg_device *dev= ice, u64 usage); + + /** + * gpucg_uncharge - uncharge memory from the specified gpucg and g= pucg_device. + * + * @gpucg: The gpu cgroup to uncharge the memory from. + * @device: The device to charge the memory from. + * @usage: size of memory to uncharge in bytes. + */ + void gpucg_uncharge(struct gpucg *gpucg, struct gpucg_device *devi= ce, u64 usage); + +Future Work +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Additional GPU resources can be supported by adding new controller files. diff --git a/Documentation/gpu/rfc/index.rst b/Documentation/gpu/rfc/index.= rst index 91e93a705230..0a9bcd94e95d 100644 --- a/Documentation/gpu/rfc/index.rst +++ b/Documentation/gpu/rfc/index.rst @@ -23,3 +23,7 @@ host such documentation: .. toctree:: =20 i915_scheduler.rst + +.. toctree:: + + gpu-cgroup.rst --=20 2.35.1.616.g0bdcbb4464-goog From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C70CC433F5 for ; Wed, 9 Mar 2022 17:05:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237137AbiCIRGb (ORCPT ); Wed, 9 Mar 2022 12:06:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44752 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238803AbiCIREE (ORCPT ); Wed, 9 Mar 2022 12:04:04 -0500 Received: from mail-yw1-x114a.google.com (mail-yw1-x114a.google.com [IPv6:2607:f8b0:4864:20::114a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E42DFE869C for ; Wed, 9 Mar 2022 08:52:34 -0800 (PST) Received: by mail-yw1-x114a.google.com with SMTP id 00721157ae682-2dbf4238d6bso19404507b3.2 for ; Wed, 09 Mar 2022 08:52:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc:content-transfer-encoding; bh=x8m7SXGR83/SdOdqn7l1+FIZ1cxwPNd4HTN6OzKaqJk=; b=J9yUUK6ijZr6eIlL2BkUPNKezNNqJ7Usl7l5NfD4UexBDWRVHWzo2vGRPlARJ4lHvo 4uYgUvWM74wcdGxJ3HNGAbRITNE9V2gJbWuY8AXNQD9mUbg9OMwopeX+XM2CspXyjbUx KTAkX+QzE2yF1OB/IdQd8SiGEF22/Hb7Tn/8priJRWTDMnnKvFpslUhl6ZS1sRjtMuyk ms5lStmtJDChjDoxemZ4MHYvgS7/ztUsuap9pHbthk/R4at7QOLEDSwostK2OW3tPjvk RVrsobyQqAP/RQLUZyTdKdy9gn7B01mgiOcE/nZ9hRBnG1RosXrI8mDculT4ZVlfoDZ4 Yi8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc:content-transfer-encoding; bh=x8m7SXGR83/SdOdqn7l1+FIZ1cxwPNd4HTN6OzKaqJk=; b=A5xHK7M/nSYPfflq9/lhOVLdFHGc/Hl1Wsil/F0T5qs+puPLdPsrgKNhzNQqcRRs8z E3+X8QY7quzSXhEpCbPL1H1AAfhJsPoEJt+VamJVZJc3Bv7sjuh8incKjE9OtoNxqcsr wmNTlDldmCfj3AvsDLNzmWxXbH0yOgKsbr2ps9qzBBDxQp39sgT6FuxUHtgwTDi7L+5Y yqhjonAfjnCnsdlOjSaK/JQZAMClfE5oPkwZ8RRBH9gQqqy8T6IT8ixtemqfXzSlUi6M KdImBsY0ix3n31dvgshZ3Q57ZWehtyA93kr1cOkDCMGARdUg7+bGwOgGnojMyJdvM0TX HhTw== X-Gm-Message-State: AOAM530d2G0Ftf9Pfur7yHVhgqTCo34JrUKe7LP953iAF1uJH7pNqIlN 4q1jKOKt8fUUGZdI3eExWpgt/Bk968YmGtE= X-Google-Smtp-Source: ABdhPJwhBefo0Jr5ct437h23DSuj+1FDWXw/dIZxPZqGgOkSXpfDO+Ep1nC/b2QBICxQ0J7BmZdbcopBhFv+RU4= X-Received: from tj2.c.googlers.com ([fda3:e722:ac3:cc00:20:ed76:c0a8:187]) (user=tjmercier job=sendgmr) by 2002:a81:90d:0:b0:2db:fc82:ef40 with SMTP id 13-20020a81090d000000b002dbfc82ef40mr592122ywj.384.1646844751396; Wed, 09 Mar 2022 08:52:31 -0800 (PST) Date: Wed, 9 Mar 2022 16:52:11 +0000 In-Reply-To: <20220309165222.2843651-1-tjmercier@google.com> Message-Id: <20220309165222.2843651-2-tjmercier@google.com> Mime-Version: 1.0 References: <20220309165222.2843651-1-tjmercier@google.com> X-Mailer: git-send-email 2.35.1.616.g0bdcbb4464-goog Subject: [RFC v3 1/8] gpu: rfc: Proposal for a GPU cgroup controller From: "T.J. Mercier" To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Jonathan Corbet , Greg Kroah-Hartman , "=?UTF-8?q?Arve=20Hj=C3=B8nnev=C3=A5g?=" , Todd Kjos , Martijn Coenen , Joel Fernandes , Christian Brauner , Hridya Valsaraju , Suren Baghdasaryan , Sumit Semwal , "=?UTF-8?q?Christian=20K=C3=B6nig?=" , Benjamin Gaignard , Liam Mark , Laura Abbott , Brian Starkey , John Stultz , Tejun Heo , Zefan Li , Johannes Weiner , Shuah Khan Cc: kaleshsingh@google.com, Kenny.Ho@amd.com, "T.J. Mercier" , dri-devel@lists.freedesktop.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linaro-mm-sig@lists.linaro.org, cgroups@vger.kernel.org, linux-kselftest@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Hridya Valsaraju This patch adds a proposal for a new GPU cgroup controller for accounting/limiting GPU and GPU-related memory allocations. The proposed controller is based on the DRM cgroup controller[1] and follows the design of the RDMA cgroup controller. The new cgroup controller would: * Allow setting per-cgroup limits on the total size of buffers charged to it. * Allow setting per-device limits on the total size of buffers allocated by device within a cgroup. * Expose a per-device/allocator breakdown of the buffers charged to a cgroup. The prototype in the following patches is only for memory accounting using the GPU cgroup controller and does not implement limit setting. [1]: https://lore.kernel.org/amd-gfx/20210126214626.16260-1-brian.welty@int= el.com/ Signed-off-by: Hridya Valsaraju Signed-off-by: T.J. Mercier --- v3 changes Remove Upstreaming Plan from gpu-cgroup.rst per John Stultz. Use more common dual author commit message format per John Stultz. --- Documentation/gpu/rfc/gpu-cgroup.rst | 183 +++++++++++++++++++++++++++ Documentation/gpu/rfc/index.rst | 4 + 2 files changed, 187 insertions(+) create mode 100644 Documentation/gpu/rfc/gpu-cgroup.rst diff --git a/Documentation/gpu/rfc/gpu-cgroup.rst b/Documentation/gpu/rfc/g= pu-cgroup.rst new file mode 100644 index 000000000000..5b40d5518a5e --- /dev/null +++ b/Documentation/gpu/rfc/gpu-cgroup.rst @@ -0,0 +1,183 @@ +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +GPU cgroup controller +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Goals +=3D=3D=3D=3D=3D +This document intends to outline a plan to create a cgroup v2 controller s= ubsystem +for the per-cgroup accounting of device and system memory allocated by the= GPU +and related subsystems. + +The new cgroup controller would: + +* Allow setting per-cgroup limits on the total size of buffers charged to = it. + +* Allow setting per-device limits on the total size of buffers allocated b= y a + device/allocator within a cgroup. + +* Expose a per-device/allocator breakdown of the buffers charged to a cgro= up. + +Alternatives Considered +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The following alternatives were considered: + +The memory cgroup controller +____________________________ + +1. As was noted in [1], memory accounting provided by the GPU cgroup +controller is not a good fit for integration into memcg due to the +differences in how accounting is performed. It implements a mechanism +for the allocator attribution of GPU and GPU-related memory by +charging each buffer to the cgroup of the process on behalf of which +the memory was allocated. The buffer stays charged to the cgroup until +it is freed regardless of whether the process retains any references +to it. On the other hand, the memory cgroup controller offers a more +fine-grained charging and uncharging behavior depending on the kind of +page being accounted. + +2. Memcg performs accounting in units of pages. In the DMA-BUF buffer shar= ing model, +a process takes a reference to the entire buffer(hence keeping it alive) e= ven if +it is only accessing parts of it. Therefore, per-page memory tracking for = DMA-BUF +memory accounting would only introduce additional overhead without any ben= efits. + +[1]: https://patchwork.kernel.org/project/dri-devel/cover/20190501140438.9= 506-1-brian.welty@intel.com/#22624705 + +Userspace service to keep track of buffer allocations and releases +__________________________________________________________________ + +1. There is no way for a userspace service to intercept all allocations an= d releases. +2. In case the process gets killed or restarted, we lose all accounting so= far. + +UAPI +=3D=3D=3D=3D +When enabled, the new cgroup controller would create the following files i= n every cgroup. + +:: + + gpu.memory.current (R) + gpu.memory.max (R/W) + +gpu.memory.current is a read-only file and would contain per-device memory= allocations +in a key-value format where key is a string representing the device name +and the value is the size of memory charged to the device in the cgroup in= bytes. + +For example: + +:: + + cat /sys/kernel/fs/cgroup1/gpu.memory.current + dev1 4194304 + dev2 4194304 + +The string key for each device is set by the device driver when the device= registers +with the GPU cgroup controller to participate in resource accounting(see s= ection +'Design and Implementation' for more details). + +gpu.memory.max is a read/write file. It would show the current total +size limits on memory usage for the cgroup and the limits on total memory = usage +for each allocator/device. + +Setting a total limit for a cgroup can be done as follows: + +:: + + echo =E2=80=9Ctotal 41943040=E2=80=9D > /sys/kernel/fs/cgroup1/gpu= .memory.max + +Setting a total limit for a particular device/allocator can be done as fol= lows: + +:: + + echo =E2=80=9Cdev1 4194304=E2=80=9D > /sys/kernel/fs/cgroup1/gpu.= memory.max + +In this example, 'dev1' is the string key set by the device driver during +registration. + +Design and Implementation +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + +The cgroup controller would closely follow the design of the RDMA cgroup c= ontroller +subsystem where each cgroup maintains a list of resource pools. +Each resource pool contains a struct device and the counter to track curre= nt total, +and the maximum limit set for the device. + +The below code block is a preliminary estimation on how the core kernel da= ta structures +and APIs would look like. + +.. code-block:: c + + /** + * The GPU cgroup controller data structure. + */ + struct gpucg { + struct cgroup_subsys_state css; + + /* list of all resource pools that belong to this cgroup *= / + struct list_head rpools; + }; + + struct gpucg_device { + /* + * list of various resource pools in various cgroups that= the device is + * part of. + */ + struct list_head rpools; + + /* list of all devices registered for GPU cgroup accountin= g */ + struct list_head dev_node; + + /* name to be used as identifier for accounting and limit = setting */ + const char *name; + }; + + struct gpucg_resource_pool { + /* The device whose resource usage is tracked by this reso= urce pool */ + struct gpucg_device *device; + + /* list of all resource pools for the cgroup */ + struct list_head cg_node; + + /* + * list maintained by the gpucg_device to keep track of it= s + * resource pools + */ + struct list_head dev_node; + + /* tracks memory usage of the resource pool */ + struct page_counter total; + }; + + /** + * gpucg_register_device - Registers a device for memory accountin= g using the + * GPU cgroup controller. + * + * @device: The device to register for memory accounting. Must rem= ain valid + * after registration. + * @name: Pointer to a string literal to denote the name of the de= vice. + */ + void gpucg_register_device(struct gpucg_device *gpucg_dev, const c= har *name); + + /** + * gpucg_try_charge - charge memory to the specified gpucg and gpu= cg_device. + * + * @gpucg: The gpu cgroup to charge the memory to. + * @device: The device to charge the memory to. + * @usage: size of memory to charge in bytes. + * + * Return: returns 0 if the charging is successful and otherwise r= eturns an + * error code. + */ + int gpucg_try_charge(struct gpucg *gpucg, struct gpucg_device *dev= ice, u64 usage); + + /** + * gpucg_uncharge - uncharge memory from the specified gpucg and g= pucg_device. + * + * @gpucg: The gpu cgroup to uncharge the memory from. + * @device: The device to charge the memory from. + * @usage: size of memory to uncharge in bytes. + */ + void gpucg_uncharge(struct gpucg *gpucg, struct gpucg_device *devi= ce, u64 usage); + +Future Work +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Additional GPU resources can be supported by adding new controller files. diff --git a/Documentation/gpu/rfc/index.rst b/Documentation/gpu/rfc/index.= rst index 91e93a705230..0a9bcd94e95d 100644 --- a/Documentation/gpu/rfc/index.rst +++ b/Documentation/gpu/rfc/index.rst @@ -23,3 +23,7 @@ host such documentation: .. toctree:: =20 i915_scheduler.rst + +.. toctree:: + + gpu-cgroup.rst --=20 2.35.1.616.g0bdcbb4464-goog From mboxrd@z Thu Jan 1 00:00:00 1970 From: "T.J. Mercier" Subject: [RFC v3 1/8] gpu: rfc: Proposal for a GPU cgroup controller Date: Wed, 9 Mar 2022 16:52:11 +0000 Message-ID: <20220309165222.2843651-2-tjmercier@google.com> References: <20220309165222.2843651-1-tjmercier@google.com> Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Return-path: DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc:content-transfer-encoding; bh=x8m7SXGR83/SdOdqn7l1+FIZ1cxwPNd4HTN6OzKaqJk=; b=J9yUUK6ijZr6eIlL2BkUPNKezNNqJ7Usl7l5NfD4UexBDWRVHWzo2vGRPlARJ4lHvo 4uYgUvWM74wcdGxJ3HNGAbRITNE9V2gJbWuY8AXNQD9mUbg9OMwopeX+XM2CspXyjbUx KTAkX+QzE2yF1OB/IdQd8SiGEF22/Hb7Tn/8priJRWTDMnnKvFpslUhl6ZS1sRjtMuyk ms5lStmtJDChjDoxemZ4MHYvgS7/ztUsuap9pHbthk/R4at7QOLEDSwostK2OW3tPjvk RVrsobyQqAP/RQLUZyTdKdy9gn7B01mgiOcE/nZ9hRBnG1RosXrI8mDculT4ZVlfoDZ4 Yi8w== In-Reply-To: <20220309165222.2843651-1-tjmercier@google.com> List-ID: Content-Type: text/plain; charset="utf-8" To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Jonathan Corbet , Greg Kroah-Hartman , =?UTF-8?q?Arve=20Hj=C3=B8nnev=C3=A5g?= , Todd Kjos , Martijn Coenen , Joel Fernandes , Christian Brauner , Hridya Valsaraju , Suren Baghdasaryan , Sumit Semwal , =?UTF-8?q?Christian=20K=C3=B6nig?= , Benjamin Gaignard , Liam Mark Cc: kaleshsingh@google.com, Kenny.Ho@amd.com, "T.J. Mercier" , dri-devel@lists.freedesktop.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linaro-mm-sig@lists.linaro.org, cgroups@vger.kernel.org, linux-kselftest@vger.kernel.org From: Hridya Valsaraju This patch adds a proposal for a new GPU cgroup controller for accounting/limiting GPU and GPU-related memory allocations. The proposed controller is based on the DRM cgroup controller[1] and follows the design of the RDMA cgroup controller. The new cgroup controller would: * Allow setting per-cgroup limits on the total size of buffers charged to it. * Allow setting per-device limits on the total size of buffers allocated by device within a cgroup. * Expose a per-device/allocator breakdown of the buffers charged to a cgroup. The prototype in the following patches is only for memory accounting using the GPU cgroup controller and does not implement limit setting. [1]: https://lore.kernel.org/amd-gfx/20210126214626.16260-1-brian.welty@int= el.com/ Signed-off-by: Hridya Valsaraju Signed-off-by: T.J. Mercier --- v3 changes Remove Upstreaming Plan from gpu-cgroup.rst per John Stultz. Use more common dual author commit message format per John Stultz. --- Documentation/gpu/rfc/gpu-cgroup.rst | 183 +++++++++++++++++++++++++++ Documentation/gpu/rfc/index.rst | 4 + 2 files changed, 187 insertions(+) create mode 100644 Documentation/gpu/rfc/gpu-cgroup.rst diff --git a/Documentation/gpu/rfc/gpu-cgroup.rst b/Documentation/gpu/rfc/g= pu-cgroup.rst new file mode 100644 index 000000000000..5b40d5518a5e --- /dev/null +++ b/Documentation/gpu/rfc/gpu-cgroup.rst @@ -0,0 +1,183 @@ +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +GPU cgroup controller +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Goals +=3D=3D=3D=3D=3D +This document intends to outline a plan to create a cgroup v2 controller s= ubsystem +for the per-cgroup accounting of device and system memory allocated by the= GPU +and related subsystems. + +The new cgroup controller would: + +* Allow setting per-cgroup limits on the total size of buffers charged to = it. + +* Allow setting per-device limits on the total size of buffers allocated b= y a + device/allocator within a cgroup. + +* Expose a per-device/allocator breakdown of the buffers charged to a cgro= up. + +Alternatives Considered +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The following alternatives were considered: + +The memory cgroup controller +____________________________ + +1. As was noted in [1], memory accounting provided by the GPU cgroup +controller is not a good fit for integration into memcg due to the +differences in how accounting is performed. It implements a mechanism +for the allocator attribution of GPU and GPU-related memory by +charging each buffer to the cgroup of the process on behalf of which +the memory was allocated. The buffer stays charged to the cgroup until +it is freed regardless of whether the process retains any references +to it. On the other hand, the memory cgroup controller offers a more +fine-grained charging and uncharging behavior depending on the kind of +page being accounted. + +2. Memcg performs accounting in units of pages. In the DMA-BUF buffer shar= ing model, +a process takes a reference to the entire buffer(hence keeping it alive) e= ven if +it is only accessing parts of it. Therefore, per-page memory tracking for = DMA-BUF +memory accounting would only introduce additional overhead without any ben= efits. + +[1]: https://patchwork.kernel.org/project/dri-devel/cover/20190501140438.9= 506-1-brian.welty@intel.com/#22624705 + +Userspace service to keep track of buffer allocations and releases +__________________________________________________________________ + +1. There is no way for a userspace service to intercept all allocations an= d releases. +2. In case the process gets killed or restarted, we lose all accounting so= far. + +UAPI +=3D=3D=3D=3D +When enabled, the new cgroup controller would create the following files i= n every cgroup. + +:: + + gpu.memory.current (R) + gpu.memory.max (R/W) + +gpu.memory.current is a read-only file and would contain per-device memory= allocations +in a key-value format where key is a string representing the device name +and the value is the size of memory charged to the device in the cgroup in= bytes. + +For example: + +:: + + cat /sys/kernel/fs/cgroup1/gpu.memory.current + dev1 4194304 + dev2 4194304 + +The string key for each device is set by the device driver when the device= registers +with the GPU cgroup controller to participate in resource accounting(see s= ection +'Design and Implementation' for more details). + +gpu.memory.max is a read/write file. It would show the current total +size limits on memory usage for the cgroup and the limits on total memory = usage +for each allocator/device. + +Setting a total limit for a cgroup can be done as follows: + +:: + + echo =E2=80=9Ctotal 41943040=E2=80=9D > /sys/kernel/fs/cgroup1/gpu= .memory.max + +Setting a total limit for a particular device/allocator can be done as fol= lows: + +:: + + echo =E2=80=9Cdev1 4194304=E2=80=9D > /sys/kernel/fs/cgroup1/gpu.= memory.max + +In this example, 'dev1' is the string key set by the device driver during +registration. + +Design and Implementation +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + +The cgroup controller would closely follow the design of the RDMA cgroup c= ontroller +subsystem where each cgroup maintains a list of resource pools. +Each resource pool contains a struct device and the counter to track curre= nt total, +and the maximum limit set for the device. + +The below code block is a preliminary estimation on how the core kernel da= ta structures +and APIs would look like. + +.. code-block:: c + + /** + * The GPU cgroup controller data structure. + */ + struct gpucg { + struct cgroup_subsys_state css; + + /* list of all resource pools that belong to this cgroup *= / + struct list_head rpools; + }; + + struct gpucg_device { + /* + * list of various resource pools in various cgroups that= the device is + * part of. + */ + struct list_head rpools; + + /* list of all devices registered for GPU cgroup accountin= g */ + struct list_head dev_node; + + /* name to be used as identifier for accounting and limit = setting */ + const char *name; + }; + + struct gpucg_resource_pool { + /* The device whose resource usage is tracked by this reso= urce pool */ + struct gpucg_device *device; + + /* list of all resource pools for the cgroup */ + struct list_head cg_node; + + /* + * list maintained by the gpucg_device to keep track of it= s + * resource pools + */ + struct list_head dev_node; + + /* tracks memory usage of the resource pool */ + struct page_counter total; + }; + + /** + * gpucg_register_device - Registers a device for memory accountin= g using the + * GPU cgroup controller. + * + * @device: The device to register for memory accounting. Must rem= ain valid + * after registration. + * @name: Pointer to a string literal to denote the name of the de= vice. + */ + void gpucg_register_device(struct gpucg_device *gpucg_dev, const c= har *name); + + /** + * gpucg_try_charge - charge memory to the specified gpucg and gpu= cg_device. + * + * @gpucg: The gpu cgroup to charge the memory to. + * @device: The device to charge the memory to. + * @usage: size of memory to charge in bytes. + * + * Return: returns 0 if the charging is successful and otherwise r= eturns an + * error code. + */ + int gpucg_try_charge(struct gpucg *gpucg, struct gpucg_device *dev= ice, u64 usage); + + /** + * gpucg_uncharge - uncharge memory from the specified gpucg and g= pucg_device. + * + * @gpucg: The gpu cgroup to uncharge the memory from. + * @device: The device to charge the memory from. + * @usage: size of memory to uncharge in bytes. + */ + void gpucg_uncharge(struct gpucg *gpucg, struct gpucg_device *devi= ce, u64 usage); + +Future Work +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Additional GPU resources can be supported by adding new controller files. diff --git a/Documentation/gpu/rfc/index.rst b/Documentation/gpu/rfc/index.= rst index 91e93a705230..0a9bcd94e95d 100644 --- a/Documentation/gpu/rfc/index.rst +++ b/Documentation/gpu/rfc/index.rst @@ -23,3 +23,7 @@ host such documentation: .. toctree:: =20 i915_scheduler.rst + +.. toctree:: + + gpu-cgroup.rst --=20 2.35.1.616.g0bdcbb4464-goog