From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B42BBC433EF for ; Wed, 9 Mar 2022 18:59:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235046AbiCITAh (ORCPT ); Wed, 9 Mar 2022 14:00:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44282 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232102AbiCITAg (ORCPT ); Wed, 9 Mar 2022 14:00:36 -0500 Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 623709E57D for ; Wed, 9 Mar 2022 10:59:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646852377; x=1678388377; h=date:from:to:cc:subject:message-id:references: mime-version:content-transfer-encoding:in-reply-to; bh=p/eiDETu/mTqfvyDVjzbt5AGoIF2xiYOgPu8BrcsE8U=; b=OwLS3eX+eSFWRiWE9KqAiZqLNLdOFjcZXU8Icd6TjQjkQW2rxJwHE86S wGwLENNvKLLloXN5Jbffl7YsOUXNBpKP5KleEIx5e/D+19gQeGz0v2b0e fEK7EE8uV0eezoy5pSkjVJ7L8oIAc/hKcPrwC496ov9v0cREOIAtp7NzS p1eHr0+6WiX8MB/lZKNjxy35lev/g9giPY7mpHvxHrZ3Haa/W5BN3Ii6Z u2JAfi+hqi5ahVGHxmbKVMBWwl+Qs/x8ZMA9GesJfFYiQ38n7XFqhaueT x0G5P7INEBSBKgIblEzRfe/ejDJ5jdbYFgQ5enX3yaCgQ8SFocbYkPven w==; X-IronPort-AV: E=McAfee;i="6200,9189,10281"; a="315781998" X-IronPort-AV: E=Sophos;i="5.90,168,1643702400"; d="scan'208";a="315781998" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Mar 2022 10:59:36 -0800 X-IronPort-AV: E=Sophos;i="5.90,168,1643702400"; d="scan'208";a="554249784" Received: from unknown (HELO intel.com) ([10.237.72.65]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Mar 2022 10:59:35 -0800 Date: Wed, 9 Mar 2022 20:59:59 +0200 From: "Lisovskiy, Stanislav" To: Ville Syrjala Cc: intel-gfx@lists.freedesktop.org, stable@vger.kernel.org Subject: Re: [PATCH v2 6/8] drm/i915: Fix PSF GV point mask when SAGV is not possible Message-ID: <20220309185959.GA9439@intel.com> References: <20220309164948.10671-1-ville.syrjala@linux.intel.com> <20220309164948.10671-7-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20220309164948.10671-7-ville.syrjala@linux.intel.com> User-Agent: Mutt/1.9.4 (2018-02-28) Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org On Wed, Mar 09, 2022 at 06:49:46PM +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > Don't just mask off all the PSF GV points when SAGV gets disabled. > This should in fact cause the Pcode to reject the request since > at least one PSF point must remain enabled at all times. Good point, however I think this is not the full fix: BSpec says: "At least one GV point of each type must always remain unmasked." and "The GV point of each type providing the highest bandwidth for display must always remain unmasked." So I guess we should then also choose thr PSF GV point with the highest bandwidth as well. Stan > > Cc: stable@vger.kernel.org > Cc: Stanislav Lisovskiy > Fixes: 192fbfb76744 ("drm/i915: Implement PSF GV point support") > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/display/intel_bw.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c > index ad1564ca7269..adf58c58513b 100644 > --- a/drivers/gpu/drm/i915/display/intel_bw.c > +++ b/drivers/gpu/drm/i915/display/intel_bw.c > @@ -992,7 +992,8 @@ int intel_bw_atomic_check(struct intel_atomic_state *state) > * cause. > */ > if (!intel_can_enable_sagv(dev_priv, new_bw_state)) { > - allowed_points = BIT(max_bw_point); > + allowed_points &= ADLS_PSF_PT_MASK; > + allowed_points |= BIT(max_bw_point); > drm_dbg_kms(&dev_priv->drm, "No SAGV, using single QGV point %d\n", > max_bw_point); > } > -- > 2.34.1 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0F178C433FE for ; Wed, 9 Mar 2022 18:59:43 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6B3AE10E3AF; Wed, 9 Mar 2022 18:59:42 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 838E710E3E4 for ; Wed, 9 Mar 2022 18:59:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646852380; x=1678388380; h=date:from:to:cc:subject:message-id:references: mime-version:content-transfer-encoding:in-reply-to; bh=p/eiDETu/mTqfvyDVjzbt5AGoIF2xiYOgPu8BrcsE8U=; b=OW+Cl1Fz+8qwW90FPcPz0iCjR4fMXOQEtNHasNlLq5Lo4KQ3vWLWw8vt 0psXJ7tr2+QLbOotPsW6DfcGOzLBk6EgYrMcgqF8Z1CoWOK/MY/tvDOYr v5A+H7tCoWEBTBPACY/LviVueLfnCxj63fVg99WAeOdP4Gkbig8rEIcpm c1p+bKNn2Ygrs3tZUdDzhgD7+exZjbF/Q1twIbf+MsT9YTlJGHo99fYFO 0zH6KfGHNripbdhWrN9hiNp0RgSrkg0bYP75WSPll9VrJAhJCFgSaMfAt sTWknoZC+xTTXDQUrD9piG0vQJlqWFRLuwASkoTDUtqSihPfLeqkQJ12u w==; X-IronPort-AV: E=McAfee;i="6200,9189,10281"; a="242507749" X-IronPort-AV: E=Sophos;i="5.90,168,1643702400"; d="scan'208";a="242507749" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Mar 2022 10:59:40 -0800 X-IronPort-AV: E=Sophos;i="5.90,168,1643702400"; d="scan'208";a="554249784" Received: from unknown (HELO intel.com) ([10.237.72.65]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Mar 2022 10:59:35 -0800 Date: Wed, 9 Mar 2022 20:59:59 +0200 From: "Lisovskiy, Stanislav" To: Ville Syrjala Message-ID: <20220309185959.GA9439@intel.com> References: <20220309164948.10671-1-ville.syrjala@linux.intel.com> <20220309164948.10671-7-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20220309164948.10671-7-ville.syrjala@linux.intel.com> User-Agent: Mutt/1.9.4 (2018-02-28) Subject: Re: [Intel-gfx] [PATCH v2 6/8] drm/i915: Fix PSF GV point mask when SAGV is not possible X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, stable@vger.kernel.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Wed, Mar 09, 2022 at 06:49:46PM +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > Don't just mask off all the PSF GV points when SAGV gets disabled. > This should in fact cause the Pcode to reject the request since > at least one PSF point must remain enabled at all times. Good point, however I think this is not the full fix: BSpec says: "At least one GV point of each type must always remain unmasked." and "The GV point of each type providing the highest bandwidth for display must always remain unmasked." So I guess we should then also choose thr PSF GV point with the highest bandwidth as well. Stan > > Cc: stable@vger.kernel.org > Cc: Stanislav Lisovskiy > Fixes: 192fbfb76744 ("drm/i915: Implement PSF GV point support") > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/display/intel_bw.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c > index ad1564ca7269..adf58c58513b 100644 > --- a/drivers/gpu/drm/i915/display/intel_bw.c > +++ b/drivers/gpu/drm/i915/display/intel_bw.c > @@ -992,7 +992,8 @@ int intel_bw_atomic_check(struct intel_atomic_state *state) > * cause. > */ > if (!intel_can_enable_sagv(dev_priv, new_bw_state)) { > - allowed_points = BIT(max_bw_point); > + allowed_points &= ADLS_PSF_PT_MASK; > + allowed_points |= BIT(max_bw_point); > drm_dbg_kms(&dev_priv->drm, "No SAGV, using single QGV point %d\n", > max_bw_point); > } > -- > 2.34.1 >