From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CCA00C433F5 for ; Thu, 10 Mar 2022 17:21:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244611AbiCJRWO (ORCPT ); Thu, 10 Mar 2022 12:22:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52772 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244545AbiCJRWA (ORCPT ); Thu, 10 Mar 2022 12:22:00 -0500 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B3926190B4D for ; Thu, 10 Mar 2022 09:20:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646932859; x=1678468859; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rq/FeN2nuKAZ1KCoQdgO+h7HjUaX0XwjPfHzXcRVt6g=; b=eHi7yCOAkeC6Aqn9ddAlpF24sL4Ii3JLL8x5oTavk2PnpfvzC4d+fWhp J5jChDMgHfJG2dtzMqgOGxoazZe4/IsZIR9TfDRPYzbYO8StWlCYHE9eX InZMu8KpHHxdeDme+15wWjo2YoywSLFfkVusBFHJfJOC6eJh1oe9ikM6F TMpo3xAohstN3j9NjIGsgutf1mc6VxpWZHm24m2oY0s+bX900HApohbHk 2YvzM7gITqU05zEdUsD5Izr5zABFIBM3k9JWZyQexJEGfrYb+871/hvMG jNAYG0GwhT0wG892EltFXtWR0gy9Iuhv02+hjE/smL3zOBU+3NbXL1bB+ Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10282"; a="235261361" X-IronPort-AV: E=Sophos;i="5.90,171,1643702400"; d="scan'208";a="235261361" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Mar 2022 09:20:41 -0800 X-IronPort-AV: E=Sophos;i="5.90,171,1643702400"; d="scan'208";a="642639204" Received: from gdavids1-mobl.amr.corp.intel.com (HELO localhost) ([10.212.65.108]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Mar 2022 09:20:41 -0800 From: ira.weiny@intel.com To: Dave Hansen , "H. Peter Anvin" , Dan Williams Cc: Ira Weiny , Fenghua Yu , Rick Edgecombe , "Shankar, Ravi V" , linux-kernel@vger.kernel.org Subject: [PATCH V9 07/45] x86/pkeys: Add PKS CPU feature bit Date: Thu, 10 Mar 2022 09:19:41 -0800 Message-Id: <20220310172019.850939-8-ira.weiny@intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220310172019.850939-1-ira.weiny@intel.com> References: <20220310172019.850939-1-ira.weiny@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ira Weiny Memory Protection Keys (pkeys) provides a mechanism for enforcing page-based protections, but without requiring modification of the page tables when an application changes protection domains. The supervisor support for memory protection keys is referred to as PKS (Protection Keys Supervisor). Add the defines for the CPU support bit and the boilerplate disable infrastructure predicated on the new ARCH_ENABLE_SUPERVISOR_PKEYS Kconfig option. Signed-off-by: Ira Weiny --- Changes for V9 Dave Hansen New commit message Changes for V8 Split this out into it's own patch --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/disabled-features.h | 8 +++++++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 65d147974f8d..cb529b824a96 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -370,6 +370,7 @@ #define X86_FEATURE_MOVDIR64B (16*32+28) /* MOVDIR64B instruction */ #define X86_FEATURE_ENQCMD (16*32+29) /* ENQCMD and ENQCMDS instructions */ #define X86_FEATURE_SGX_LC (16*32+30) /* Software Guard Extensions Launch Control */ +#define X86_FEATURE_PKS (16*32+31) /* Protection Keys for Supervisor pages */ /* AMD-defined CPU features, CPUID level 0x80000007 (EBX), word 17 */ #define X86_FEATURE_OVERFLOW_RECOV (17*32+ 0) /* MCA overflow recovery support */ diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/asm/disabled-features.h index 8f28fafa98b3..66fdad8f3941 100644 --- a/arch/x86/include/asm/disabled-features.h +++ b/arch/x86/include/asm/disabled-features.h @@ -44,6 +44,12 @@ # define DISABLE_OSPKE (1<<(X86_FEATURE_OSPKE & 31)) #endif /* CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS */ +#ifdef CONFIG_ARCH_ENABLE_SUPERVISOR_PKEYS +# define DISABLE_PKS 0 +#else +# define DISABLE_PKS (1<<(X86_FEATURE_PKS & 31)) +#endif + #ifdef CONFIG_X86_5LEVEL # define DISABLE_LA57 0 #else @@ -85,7 +91,7 @@ #define DISABLED_MASK14 0 #define DISABLED_MASK15 0 #define DISABLED_MASK16 (DISABLE_PKU|DISABLE_OSPKE|DISABLE_LA57|DISABLE_UMIP| \ - DISABLE_ENQCMD) + DISABLE_ENQCMD|DISABLE_PKS) #define DISABLED_MASK17 0 #define DISABLED_MASK18 0 #define DISABLED_MASK19 0 -- 2.35.1