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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT007.mail.protection.outlook.com (10.13.177.109) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5061.24 via Frontend Transport; Sun, 13 Mar 2022 05:29:42 +0000 Received: from dapowell-ubuntu-200400-1.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Sat, 12 Mar 2022 23:29:41 -0600 From: Darren Powell To: Subject: [PATCH v1 0/2] amdgpu/pm: Implement parallel sysfs_emit solution for vega10 Date: Sun, 13 Mar 2022 00:28:37 -0500 Message-ID: <20220313052839.5777-1-darren.powell@amd.com> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c830e3e4-bbb9-43e9-73be-08da04b27a6d X-MS-TrafficTypeDiagnostic: DM6PR12MB4337:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Mar 2022 05:29:42.7436 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c830e3e4-bbb9-43e9-73be-08da04b27a6d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT007.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4337 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Darren Powell Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" == Description == Scnprintf use within the kernel is not recommended, but simple sysfs_emit replacement has not been successful due to the page alignment requirement of the function. This patch set implements a new api "emit_clock_levels" to facilitate passing both the base and offset to the device rather than just the write pointer. The emit_clock_levels API for amdgpu_dpm has been duplicated to pp_dpm, based on the patch commit 7f36948c92b2 ("amdgpu/pm: Implement new API function "emit" that accepts buffer base and write offset") and vega10_emit_clock_levels has been implemented with sysfs_emit based on vega10_print_clock_levels == Patch Summary == linux: (git@gitlab.freedesktop.org:agd5f) origin/amd-staging-drm-next @ 6b6b9c625004 + e94021f6c08c amdgpu/pm: Add new hwmgr API function "emit_clock_levels" + d83131987718 amdgpu/pm: Implement emit_clk_levels for vega10 == System Summary == * DESKTOP(AMD FX-8350 + VEGA10(687f/c3), BIOS: F2) + ISO(Ubuntu 20.04.4 LTS) + Kernel(5.16.0-20220307-fdoagd5f-g6b6b9c625004) + Overdrive Enabled(amdgpu.ppfeaturemask |= 0x4000) == Test == AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1` AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | awk '{print $9}'` HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON} lspci -nn | grep "VGA\|Display" > $LOGFILE printf 'OD enabled = %X\n' "$(( `cat /sys/module/amdgpu/parameters/ppfeaturemask` & 0x4000 ))" >> $LOGFILE FILES="pp_od_clk_voltage pp_dpm_sclk pp_dpm_mclk pp_dpm_pcie pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_vclk pp_dpm_dclk " for f in $FILES do echo === $f === >> $LOGFILE cat $HWMON_DIR/device/$f >> $LOGFILE done cat $LOGFILE Darren Powell (2): amdgpu/pm: Add new hwmgr API function "emit_clock_levels" amdgpu/pm: Implement emit_clk_levels for vega10 .../gpu/drm/amd/pm/powerplay/amd_powerplay.c | 17 ++ .../drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c | 147 ++++++++++++++++++ drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h | 2 + 3 files changed, 166 insertions(+) base-commit: 6b6b9c625004e07e000ca1918cadcb64439eb498 -- 2.35.1