From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 73A49C433F5 for ; Tue, 15 Mar 2022 17:47:00 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 46E8083C06; Tue, 15 Mar 2022 18:46:58 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="fNnmRoAu"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id D54BD83BEB; Tue, 15 Mar 2022 18:46:55 +0100 (CET) Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id A22CE83BB6 for ; Tue, 15 Mar 2022 18:46:52 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=alpernebiyasak@gmail.com Received: by mail-wm1-x32a.google.com with SMTP id l1-20020a05600c4f0100b00389645443d2so62309wmq.2 for ; Tue, 15 Mar 2022 10:46:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=qebeThaJ+zM4dQed3IdIuOBhzVKRpq/WHHMFo4WDc4w=; b=fNnmRoAukrDNWN5HjAsa+dwd+b9PrAoQpmKv7U91extZ1bq/bELwnSNizsGPsGBV2y U2M8f2no8NTQsSj0VyOIlu0vCzzg/6AM+zNUBTcPUjqj9NM/XN1Wq/z4NV3YNtVemPXi vDbGawsX3nF69Mt348mxsDUfBzCYvGSgUQ+7OlqiTPWB44i82woIoZniI6xwK4t2d880 qhVs32NndJRo+zYyHmMGQmyVqEY/0T21nj9JDduENXk/M/3st/BNq8ippzyISaHx0T4c bG15JyVXML7ryd5UJXpuNON1T5OeR4pkbWkmWIjkoz8QEjtqpjq3EGjvYsb4qdx7ZCoh AYXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=qebeThaJ+zM4dQed3IdIuOBhzVKRpq/WHHMFo4WDc4w=; b=JFm3brnu9AZGqf0rPhrWm1oDHs3+pVgRRPPGEhpiThz4+xUhy8Tf4JGcxsI3vWoGEc 7oOXoUuqmaBRXK5Kr/5qEmWyCptRfPz1LaxdjWZeqEq+YUiIDlMPTtqwLLuTo4uUmhAC +/8o1tUqsz6C0/ptMM3QinBHcKnIFcMDTz70GXbbY4WpkPUFgnn3mOlFED+2ORoSrCgs HQk+EprOMpuMCvxumYvfE9hPW87ii7JwUiri7tfgTAQV9vI10GmOMt5BrAeWxnjbBRkM BT+mjnvGKrAVPF4H79D7b2z5XbDaWrDC68llvt/dY/VWNK/zLyHTqRuRe2iUlIFyPnoq kvOg== X-Gm-Message-State: AOAM533p/koFyyK83nVWh5ylGkNvr9T4yZvU4R+UCpHkYuk2UvvzLhJf fddOojUSlSf6Bi9Hg6lys1k0irzxHxIsIw== X-Google-Smtp-Source: ABdhPJwnhTsAnpoWmFKle0Lzi/e4S5LUW+x8AnoTbN1Dhzs0wwbhu7PLmkXQQokHgnKZCNNy3Efajw== X-Received: by 2002:a1c:ed01:0:b0:38b:5a39:220c with SMTP id l1-20020a1ced01000000b0038b5a39220cmr3743973wmh.167.1647366412068; Tue, 15 Mar 2022 10:46:52 -0700 (PDT) Received: from localhost.localdomain ([178.233.26.119]) by smtp.gmail.com with ESMTPSA id p4-20020a05600c358400b00389f61bce7csm4578374wmq.32.2022.03.15.10.46.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Mar 2022 10:46:51 -0700 (PDT) From: Alper Nebi Yasak To: u-boot@lists.denx.de Cc: Faiz Abbas , Jaehoon Chung , Philipp Tomsich , Peter Robinson , Peng Fan , Peter Geis , Jagan Teki , Samuel Dionne-Riel , Simon Glass , Kever Yang , Ashok Reddy Soma , Aswath Govindraju , Jack Mitchell , Heinrich Schuchardt , Yifeng Zhao , Michal Simek , Stephen Carlson , Alper Nebi Yasak Subject: [PATCH v5 0/3] rockchip: sdhci: Add HS400 Enhanced Strobe support Date: Tue, 15 Mar 2022 20:46:25 +0300 Message-Id: <20220315174629.7467-1-alpernebiyasak@gmail.com> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean This series implements support for the HS400 Enhanced Strobe mode on the Rockchip SDHCI driver, for both RK3399 and RK3568. To test, I'm building for chromebook_kevin with the following configs enabled: +CONFIG_MMC_SPEED_MODE_SET=y [...] CONFIG_MMC_PWRSEQ=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y and running roughly: $ mmc rescan [0|1|3|10|11|12] $ mmc info $ mmc part $ load mmc 0:1 0xd0000000 256MiB.bin $ load mmc 0:1 0xd0000000 16MiB.bin $ load mmc 0:1 0xd0000000 8MiB.bin Here's the differences in info and speeds I get with this: Mode | Bus Speed | Bus Width -----------------------+--------------+-------------- MMC Legacy | 25000000 | 8-bit MMC High Speed (26MHz) | 26000000 | 8-bit MMC High Speed (52MHz) | 52000000 | 8-bit HS200 (200MHz) | 200000000 | 8-bit HS400 (200MHz) | 200000000 | 8-bit DDR HS400ES (200MHz) | 200000000 | 8-bit DDR Mode | 256 MiB Load | 16 MiB Load | 8 MiB Load -----------------------+--------------+--------------+-------------- MMC Legacy | ~22.1 MiB/s | ~21.9 MiB/s | ~21.6 MiB/s MMC High Speed (26MHz) | ~22.1 MiB/s | ~21.9 MiB/s | ~21.6 MiB/s MMC High Speed (52MHz) | ~43.7 MiB/s | ~42.8 MiB/s | ~41.7 MiB/s HS200 (200MHz) | ~161.2 MiB/s | ~149.5 MiB/s | ~137.9 MiB/s HS400 (200MHz) | ~254.5 MiB/s | ~235.3 MiB/s | ~216.2 MiB/s HS400ES (200MHz) | ~254.7 MiB/s | ~238.8 MiB/s | ~216.2 MiB/s Hope I haven't missed anything. Enabling the configs above for each board is left to board maintainers as I can't test on those boards. Changes in v5: - Incorporate RK3568 HS400ES fixes from Yifeng Zhao: - Use DWCMSHC_CTRL_HS400 = 0x7, instead of SDHCI_CTRL_HS400 = 0x5 - Configure DWCMSHC_CARD_IS_EMMC in rk3568_sdhci_set_ios_post() - Configure DLL_STRBIN and DLL_TXCLK for HS400. - Drop re-init fix already merged to master v4: https://patchwork.ozlabs.org/project/uboot/list/?series=283482&state=* Changes in v4: - Add comment for SDHCI set_enhanced_strobe() operation - Add comment for Rockchip SDHCI set_enhanced_strobe() driver data op v3: https://patchwork.ozlabs.org/project/uboot/list/?series=281327&state=* Changes in v3: - Set DWCMSHC_CARD_IS_EMMC bit in rk3568_emmc_phy_init() v2: https://patchwork.ozlabs.org/project/uboot/list/?series=280494&state=* Changes in v2: - Unset ES bit in rk3399 set_control_reg() to fix a reinit issue - Don't use unnecessary & for function pointer in ops struct - Rename rk3399_set_enhanced_strobe -> rk3399_sdhci_set_enhanced_strobe - Rename rk3568_set_enhanced_strobe -> rk3568_sdhci_set_enhanced_strobe - Let set_enhanced_strobe() unset the ES bit if mode is not HS400_ES - Rewrote cover letter v1: https://patchwork.ozlabs.org/project/uboot/list/?series=269768&state=* Alper Nebi Yasak (3): mmc: sdhci: Add HS400 Enhanced Strobe support rockchip: sdhci: Add HS400 Enhanced Strobe support for RK3399 rockchip: sdhci: Add HS400 Enhanced Strobe support for RK3568 drivers/mmc/rockchip_sdhci.c | 117 +++++++++++++++++++++++++++++++++-- drivers/mmc/sdhci.c | 18 ++++++ include/sdhci.h | 12 ++++ 3 files changed, 141 insertions(+), 6 deletions(-) -- 2.35.1