From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D125CC433F5 for ; Tue, 15 Mar 2022 17:47:48 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 03D1B83C3C; Tue, 15 Mar 2022 18:47:26 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="kovMAd1q"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 7C28383C28; Tue, 15 Mar 2022 18:47:12 +0100 (CET) Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 57B4A83BF7 for ; Tue, 15 Mar 2022 18:47:06 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=alpernebiyasak@gmail.com Received: by mail-wr1-x436.google.com with SMTP id d7so3133609wrb.7 for ; Tue, 15 Mar 2022 10:47:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=f8hycbdZ8zYFgNQKFIOPCBrN8MLSs+eW62yy/PZyyq8=; b=kovMAd1qQ4VcHyfWFVW/lWgcTRdIcjnyK0+9N4aDf4uzabSk83KB8i7FZB/LQVTxb9 YKbwum6eVLg1OycemJWfveQHJ/Ll/th1h4HBmbVv/Jw5qCbB+7OG7AAJIH7UoD7hjF3Y OMFOtnDHGHUkaBPER9mtbPjb7KRV5e+1VMrDaXRNt0eSY48FcwiFCB4HOaxubB5DV77m DK7iG+acyvl6g8lGAY3vt5MKi1P6nY/8Bnn8ExKf9PQCyi/QannW1knXZesvt2sEv56T laWO5VCWT/6qhCPf0L4wcwdTFKZo8ofDqMS01PCoxvEGUU/r3M29OGzlDMRweh/IEg9H N8gg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=f8hycbdZ8zYFgNQKFIOPCBrN8MLSs+eW62yy/PZyyq8=; b=HLgDnWDOZvTBRvVXvXRRKz+BOWHLPsqiYMtPmmh9lON5ikXa355iLjoiuTJwo+bjxT gALS8yDx0r8d9mnk8QixHpd/dxc3W69YiF5tvEpmT8v4Ot7NvLmtQ84AxXi7kmsmBdy0 +6rRsMUcDF+DVhIyTGs2/VWjICXQRXrS8WLp39e//ign7/cehinJyDfD3JpPj6Z7pKCy ev99OFnO95/1CtBMjUs3Vh0xHTZF77a9obj/8jnwCGzg7BfARzyDReCRMqyztl83oRDx eAa7pJKkYHdppAD57cv4Y3PZmMDlX0mojbSM/X7Hcfk9QlOvU4bDGXElN0/n7btItbpy PDGw== X-Gm-Message-State: AOAM530l/QV7c+zzzkC6ybRce0Yo9WCB4om8dTIYMmWRvSBrcYUkvt4T YGKqEzblBCCuSa75E3F5KGEQBpCrb7zAKw== X-Google-Smtp-Source: ABdhPJx8vSEiONlr3MC5NxEZxJOGW/dzyjbPsqSjNID6HUwGuDuxLtopxVe2tlL03Yxn6Mk9OxJ+6g== X-Received: by 2002:a5d:5308:0:b0:1f0:6300:f1d0 with SMTP id e8-20020a5d5308000000b001f06300f1d0mr21710927wrv.278.1647366425813; Tue, 15 Mar 2022 10:47:05 -0700 (PDT) Received: from localhost.localdomain ([178.233.26.119]) by smtp.gmail.com with ESMTPSA id p4-20020a05600c358400b00389f61bce7csm4578374wmq.32.2022.03.15.10.47.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Mar 2022 10:47:05 -0700 (PDT) From: Alper Nebi Yasak To: u-boot@lists.denx.de Cc: Faiz Abbas , Jaehoon Chung , Philipp Tomsich , Peter Robinson , Peng Fan , Peter Geis , Jagan Teki , Samuel Dionne-Riel , Simon Glass , Kever Yang , Ashok Reddy Soma , Aswath Govindraju , Jack Mitchell , Heinrich Schuchardt , Yifeng Zhao , Michal Simek , Stephen Carlson , Alper Nebi Yasak Subject: [PATCH v5 3/3] rockchip: sdhci: Add HS400 Enhanced Strobe support for RK3568 Date: Tue, 15 Mar 2022 20:46:28 +0300 Message-Id: <20220315174629.7467-4-alpernebiyasak@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220315174629.7467-1-alpernebiyasak@gmail.com> References: <20220315174629.7467-1-alpernebiyasak@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean On RK3568, a register bit must be set to enable Enhanced Strobe. However, it appears that the address of this register may differ from vendor to vendor and should be read from the underlying MMC IP. Let the Rockchip SDHCI driver read this address and set the relevant bit when Enhanced Strobe configuration is requested. The IP uses a custom mode select value (0x7) for HS400, use that instead of the common but non-standard SDHCI_CTRL_HS400 value (0x5). Also add some necessary DLL_STRBIN and DLL_TXCLK configuration for HS400. Additionally, a bit signifying that the connected hardware is an eMMC chip must be set to enable Data Strobe for HS400 and HS400ES modes. Also make the driver set this bit as appropriate. This is partly ported from Linux's Synopsys DWC MSHC driver which happens to be the underlying IP. (drivers/mmc/host/sdhci-of-dwcmshc.c in Linux tree). Co-developed-by: Yifeng Zhao Signed-off-by: Yifeng Zhao Signed-off-by: Alper Nebi Yasak --- This is a fixed version I received off-list from Yifeng. I didn't modify the diff, but added a paragraph in the commit message mentioning their changes and adjusted the signoffs in the end. Didn't add the Reviewed-by tag due to changes. Changes in v5: - Incorporate RK3568 HS400ES fixes from Yifeng Zhao: - Use DWCMSHC_CTRL_HS400 = 0x7, instead of SDHCI_CTRL_HS400 = 0x5 - Configure DWCMSHC_CARD_IS_EMMC in rk3568_sdhci_set_ios_post() - Configure DLL_STRBIN and DLL_TXCLK for HS400. Changes in v3: - Set DWCMSHC_CARD_IS_EMMC bit in rk3568_emmc_phy_init() Changes in v2: - Rename rk3568_set_enhanced_strobe -> rk3568_sdhci_set_enhanced_strobe - Let set_enhanced_strobe() unset the ES bit if mode is not HS400_ES drivers/mmc/rockchip_sdhci.c | 64 ++++++++++++++++++++++++++++++++---- 1 file changed, 58 insertions(+), 6 deletions(-) diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c index f4d5a59036a2..f3f9d83ba36f 100644 --- a/drivers/mmc/rockchip_sdhci.c +++ b/drivers/mmc/rockchip_sdhci.c @@ -22,6 +22,8 @@ #include #include +/* DWCMSHC specific Mode Select value */ +#define DWCMSHC_CTRL_HS400 0x7 /* 400KHz is max freq for card ID etc. Use that as min */ #define EMMC_MIN_FREQ 400000 #define KHz (1000) @@ -45,6 +47,14 @@ #define ARASAN_VENDOR_REGISTER 0x78 #define ARASAN_VENDOR_ENHANCED_STROBE BIT(0) +/* DWC IP vendor area 1 pointer */ +#define DWCMSHC_P_VENDOR_AREA1 0xe8 +#define DWCMSHC_AREA1_MASK GENMASK(11, 0) +/* Offset inside the vendor area 1 */ +#define DWCMSHC_EMMC_CONTROL 0x2c +#define DWCMSHC_CARD_IS_EMMC BIT(0) +#define DWCMSHC_ENHANCED_STROBE BIT(8) + /* Rockchip specific Registers */ #define DWCMSHC_EMMC_DLL_CTRL 0x800 #define DWCMSHC_EMMC_DLL_CTRL_RESET BIT(1) @@ -60,8 +70,14 @@ #define DWCMSHC_EMMC_DLL_INC_VALUE 2 #define DWCMSHC_EMMC_DLL_INC 8 #define DWCMSHC_EMMC_DLL_DLYENA BIT(27) -#define DLL_TXCLK_TAPNUM_DEFAULT 0x10 -#define DLL_STRBIN_TAPNUM_DEFAULT 0x3 +#define DLL_TXCLK_TAPNUM_DEFAULT 0xA + +#define DLL_STRBIN_TAPNUM_DEFAULT 0x8 +#define DLL_STRBIN_TAPNUM_FROM_SW BIT(24) +#define DLL_STRBIN_DELAY_NUM_SEL BIT(26) +#define DLL_STRBIN_DELAY_NUM_OFFSET 16 +#define DLL_STRBIN_DELAY_NUM_DEFAULT 0x16 + #define DLL_TXCLK_TAPNUM_FROM_SW BIT(24) #define DWCMSHC_EMMC_DLL_LOCKED BIT(8) #define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9) @@ -327,7 +343,8 @@ static int rk3568_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clo sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK); extra = DWCMSHC_EMMC_DLL_DLYENA | - DLL_STRBIN_TAPNUM_DEFAULT; + DLL_STRBIN_TAPNUM_DEFAULT | + DLL_STRBIN_TAPNUM_FROM_SW; sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN); } else { /* reset the clock phase when the frequency is lower than 100MHz */ @@ -335,7 +352,15 @@ static int rk3568_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clo extra = DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL; sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK); sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK); - sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN); + /* + * Before switching to hs400es mode, the driver will enable + * enhanced strobe first. PHY needs to configure the parameters + * of enhanced strobe first. + */ + extra = DWCMSHC_EMMC_DLL_DLYENA | + DLL_STRBIN_DELAY_NUM_SEL | + DLL_STRBIN_DELAY_NUM_DEFAULT << DLL_STRBIN_DELAY_NUM_OFFSET; + sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN); } return 0; @@ -346,11 +371,30 @@ static int rk3568_emmc_get_phy(struct udevice *dev) return 0; } +static int rk3568_sdhci_set_enhanced_strobe(struct sdhci_host *host) +{ + struct mmc *mmc = host->mmc; + u32 vendor; + int reg; + + reg = (sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK) + + DWCMSHC_EMMC_CONTROL; + + vendor = sdhci_readl(host, reg); + if (mmc->selected_mode == MMC_HS_400_ES) + vendor |= DWCMSHC_ENHANCED_STROBE; + else + vendor &= ~DWCMSHC_ENHANCED_STROBE; + sdhci_writel(host, vendor, reg); + + return 0; +} + static int rk3568_sdhci_set_ios_post(struct sdhci_host *host) { struct mmc *mmc = host->mmc; uint clock = mmc->tran_speed; - u32 reg; + u32 reg, vendor_reg; if (!clock) clock = mmc->clock; @@ -360,8 +404,15 @@ static int rk3568_sdhci_set_ios_post(struct sdhci_host *host) if (mmc->selected_mode == MMC_HS_400 || mmc->selected_mode == MMC_HS_400_ES) { reg = sdhci_readw(host, SDHCI_HOST_CONTROL2); reg &= ~SDHCI_CTRL_UHS_MASK; - reg |= SDHCI_CTRL_HS400; + reg |= DWCMSHC_CTRL_HS400; sdhci_writew(host, reg, SDHCI_HOST_CONTROL2); + + vendor_reg = (sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK) + + DWCMSHC_EMMC_CONTROL; + /* set CARD_IS_EMMC bit to enable Data Strobe for HS400 */ + reg = sdhci_readw(host, vendor_reg); + reg |= DWCMSHC_CARD_IS_EMMC; + sdhci_writew(host, reg, vendor_reg); } else { sdhci_set_uhs_timing(host); } @@ -554,6 +605,7 @@ static const struct sdhci_data rk3568_data = { .get_phy = rk3568_emmc_get_phy, .emmc_phy_init = rk3568_emmc_phy_init, .set_ios_post = rk3568_sdhci_set_ios_post, + .set_enhanced_strobe = rk3568_sdhci_set_enhanced_strobe, }; static const struct udevice_id sdhci_ids[] = { -- 2.35.1