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[188.217.56.61]) by smtp.gmail.com with ESMTPSA id c5-20020a170906d18500b006ce371f09d4sm2302796ejz.57.2022.03.17.05.38.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Mar 2022 05:38:21 -0700 (PDT) Date: Thu, 17 Mar 2022 13:38:18 +0100 From: Tommaso Merciai To: Marek Vasut Cc: Stefano Babic , Fabio Estevam , "NXP i.MX U-Boot Team" , Peng Fan , Ye Li , Alice Guo , Andrey Zhizhikin , Marek =?iso-8859-1?Q?Beh=FAn?= , u-boot@lists.denx.de Subject: Re: [PATCH v2 4/9] arm: imx: imx8mm: add enable_pwm_clk function Message-ID: <20220317123818.GE29139@tom-ThinkPad-T14s-Gen-2i> References: <20220316152746.47768-1-tommaso.merciai@amarulasolutions.com> <20220316152746.47768-5-tommaso.merciai@amarulasolutions.com> <1225773a-10e9-d90b-d1b1-0b749c96129d@denx.de> <20220317073927.GC29139@tom-ThinkPad-T14s-Gen-2i> <1ed2f6d2-1bd7-4737-dcd5-10d7b6eb9542@denx.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1ed2f6d2-1bd7-4737-dcd5-10d7b6eb9542@denx.de> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean On Thu, Mar 17, 2022 at 12:58:31PM +0100, Marek Vasut wrote: > On 3/17/22 08:39, Tommaso Merciai wrote: > > On Wed, Mar 16, 2022 at 09:54:34PM +0100, Marek Vasut wrote: > > > On 3/16/22 16:27, Tommaso Merciai wrote: > > > > Add function enable_pwm_clk into in clock_imx8mm.c. This > > > > function first configure, then enable pwm clock from clock control > > > > register. The following configuration is used: > > > > > > > > source(0) -> 24 MHz ref clock > > > > div(0) -> no division for this clock > > > > > > > > References: > > > > - iMX8MMRM.pdf p 303 > > > > > > > > Signed-off-by: Tommaso Merciai > > > > --- > > > > Changes since v1: > > > > - Fix enable_pwm_clk function implementation. Now is generic for all pwm clks > > > > > > > > arch/arm/mach-imx/imx8m/clock_imx8mm.c | 53 ++++++++++++++++++++++++++ > > > > 1 file changed, 53 insertions(+) > > > > > > Why is this not in drivers/clk/imx/ DM driver ? > > > > Hi Marek, > > All function that enable/configure clk from CCGR are in arch/arm/mach-imx/imx8m/clock_imx8mm.c. > > These seems to be CCGR: > > $ grep -C 2 '0x4[0-9a-f]\{3\}' drivers/clk/imx/clk-imx8mm.c | sed "s@^.@@" > > clk_dm(IMX8MM_CLK_ECSPI1_ROOT, > imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0)); > clk_dm(IMX8MM_CLK_ECSPI2_ROOT, > imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0)); > clk_dm(IMX8MM_CLK_ECSPI3_ROOT, > imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0)); > clk_dm(IMX8MM_CLK_I2C1_ROOT, > imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0)); > clk_dm(IMX8MM_CLK_I2C2_ROOT, > imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0)); > clk_dm(IMX8MM_CLK_I2C3_ROOT, > imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0)); > clk_dm(IMX8MM_CLK_I2C4_ROOT, > imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0)); > clk_dm(IMX8MM_CLK_OCOTP_ROOT, > imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0)); > clk_dm(IMX8MM_CLK_USDHC1_ROOT, > imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0)); > clk_dm(IMX8MM_CLK_USDHC2_ROOT, > imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0)); > clk_dm(IMX8MM_CLK_WDOG1_ROOT, > imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0)); > clk_dm(IMX8MM_CLK_WDOG2_ROOT, > imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0)); > clk_dm(IMX8MM_CLK_WDOG3_ROOT, > imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0)); > clk_dm(IMX8MM_CLK_USDHC3_ROOT, > imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0)); > clk_dm(IMX8MM_CLK_QSPI_ROOT, > imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0)); > clk_dm(IMX8MM_CLK_USB1_CTRL_ROOT, > imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0)); > > /* clks not needed in SPL stage */ > - > clk_dm(IMX8MM_CLK_ENET1_ROOT, > imx_clk_gate4("enet1_root_clk", "enet_axi", > base + 0x40a0, 0)); > endif > > > For that I continue to put here the implementation. After we can port > > the clk dm part to manipulate clock in drivers/clk/imx/ DM driver. > > What do you think about? Let me know. > > Seems like the clk_dm part is already in place and all you have to do is > extend it. Hi Marek, I'll try also this way and let you know. Thanks, Tommaso -- Tommaso Merciai Embedded Linux Engineer tommaso.merciai@amarulasolutions.com __________________________________ Amarula Solutions SRL Via Le Canevare 30, 31100 Treviso, Veneto, IT T. +39 042 243 5310 info@amarulasolutions.com www.amarulasolutions.com