From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0601C433EF for ; Mon, 21 Mar 2022 14:40:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349514AbiCUOlZ (ORCPT ); Mon, 21 Mar 2022 10:41:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39760 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349457AbiCUOlW (ORCPT ); Mon, 21 Mar 2022 10:41:22 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AE65F1890CD; Mon, 21 Mar 2022 07:39:56 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 3759660C73; Mon, 21 Mar 2022 14:39:56 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 06D4EC340E8; Mon, 21 Mar 2022 14:39:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1647873595; bh=DvATwoHTxnArnbHtADD5Mg71Fi3pHjfQ9J9ORoxi+UI=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=NYmgDU7FL+wbRjIgi+f4VRnRmFWuAVTkl7g3kOamPyLk64U7Ax14VO3SKbCcdbC0W Bu9cW7deMtVw3T9rWU9seP7toK06zScpQrc2iTe/0KTcA24G/CBgcGsaI2DXLcBtSS ofo0rT/LwpSJdn0mJVwpa2dzNYgcP03+DZc32HeKsxMcy4TvJk7IWLgPLjvLaDUWBQ bAUN+fbbDqXv/lYRyuXk/5NpPINOtFu8yiE1SLqeC5w3HqTeDdltRxgES82G62Oo0R qpOpLHCTH3K/Egvs2irmRYrKOdTEosWJmRJXwzhj0xH6E7NYv0RvaKXlvX642pbZ0x jNQ9DhNE8HAsQ== Date: Mon, 21 Mar 2022 14:39:44 +0000 From: Will Deacon To: Catalin Marinas Cc: David Hildenbrand , linux-kernel@vger.kernel.org, Andrew Morton , Hugh Dickins , Linus Torvalds , David Rientjes , Shakeel Butt , John Hubbard , Jason Gunthorpe , Mike Kravetz , Mike Rapoport , Yang Shi , "Kirill A . Shutemov" , Matthew Wilcox , Vlastimil Babka , Jann Horn , Michal Hocko , Nadav Amit , Rik van Riel , Roman Gushchin , Andrea Arcangeli , Peter Xu , Donald Dutile , Christoph Hellwig , Oleg Nesterov , Jan Kara , Liang Zhang , Pedro Gomes , Oded Gabbay , Michael Ellerman , Benjamin Herrenschmidt , Paul Mackerras , Heiko Carstens , Vasily Gorbik , Alexander Gordeev , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , linux-mm@kvack.org, x86@kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org Subject: Re: [PATCH v1 4/7] arm64/pgtable: support __HAVE_ARCH_PTE_SWP_EXCLUSIVE Message-ID: <20220321143944.GD11145@willie-the-truck> References: <20220315141837.137118-1-david@redhat.com> <20220315141837.137118-5-david@redhat.com> <20220321143802.GC11145@willie-the-truck> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220321143802.GC11145@willie-the-truck> User-Agent: Mutt/1.10.1 (2018-07-13) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Mar 21, 2022 at 02:38:02PM +0000, Will Deacon wrote: > On Wed, Mar 16, 2022 at 06:27:01PM +0000, Catalin Marinas wrote: > > On Tue, Mar 15, 2022 at 03:18:34PM +0100, David Hildenbrand wrote: > > > diff --git a/arch/arm64/include/asm/pgtable-prot.h b/arch/arm64/include/asm/pgtable-prot.h > > > index b1e1b74d993c..62e0ebeed720 100644 > > > --- a/arch/arm64/include/asm/pgtable-prot.h > > > +++ b/arch/arm64/include/asm/pgtable-prot.h > > > @@ -14,6 +14,7 @@ > > > * Software defined PTE bits definition. > > > */ > > > #define PTE_WRITE (PTE_DBM) /* same as DBM (51) */ > > > +#define PTE_SWP_EXCLUSIVE (_AT(pteval_t, 1) << 2) /* only for swp ptes */ > > > > I think we can use bit 1 here. > > > > > @@ -909,12 +925,13 @@ static inline pmd_t pmdp_establish(struct vm_area_struct *vma, > > > /* > > > * Encode and decode a swap entry: > > > * bits 0-1: present (must be zero) > > > - * bits 2-7: swap type > > > + * bits 2: remember PG_anon_exclusive > > > + * bits 3-7: swap type > > > * bits 8-57: swap offset > > > * bit 58: PTE_PROT_NONE (must be zero) > > > > I don't remember exactly why we reserved bits 0 and 1 when, from the > > hardware perspective, it's sufficient for bit 0 to be 0 and the whole > > pte becomes invalid. We use bit 1 as the 'table' bit (when 0 at pmd > > level, it's a huge page) but we shouldn't check for this on a swap > > entry. > > I'm a little worried that when we're dealing with huge mappings at the > PMD level we might lose the ability to distinguish them from a pte-level > mapping with this new flag set if we use bit 1. A similar issue to this > was fixed a long time ago by 59911ca4325d ("ARM64: mm: Move PTE_PROT_NONE > bit") when we used to use bit 1 for PTE_PROT_NONE. > > Is something like: > > pmd_to_swp_entry(swp_entry_to_pmd(pmd)); > > supposed to preserve the original pmd? I'm not sure that's guaranteed > after this change if bit 1 can be cleared in the process -- we could end > up with a pte, which the hardware would interpret as a table entry and > end up with really bad things happening. (I got this back to front: having the bit set rather than cleared would be an issue, but the overall point remains). Will From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4BBF7C433F5 for ; Mon, 21 Mar 2022 14:40:34 +0000 (UTC) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4KMcjX5MFnz3bN8 for ; Tue, 22 Mar 2022 01:40:32 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=NYmgDU7F; dkim-atps=neutral Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=kernel.org (client-ip=145.40.68.75; helo=ams.source.kernel.org; envelope-from=will@kernel.org; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=NYmgDU7F; dkim-atps=neutral Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4KMchv1PFvz2yxV for ; Tue, 22 Mar 2022 01:39:59 +1100 (AEDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id CD73FB8170E; Mon, 21 Mar 2022 14:39:56 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 06D4EC340E8; Mon, 21 Mar 2022 14:39:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1647873595; bh=DvATwoHTxnArnbHtADD5Mg71Fi3pHjfQ9J9ORoxi+UI=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=NYmgDU7FL+wbRjIgi+f4VRnRmFWuAVTkl7g3kOamPyLk64U7Ax14VO3SKbCcdbC0W Bu9cW7deMtVw3T9rWU9seP7toK06zScpQrc2iTe/0KTcA24G/CBgcGsaI2DXLcBtSS ofo0rT/LwpSJdn0mJVwpa2dzNYgcP03+DZc32HeKsxMcy4TvJk7IWLgPLjvLaDUWBQ bAUN+fbbDqXv/lYRyuXk/5NpPINOtFu8yiE1SLqeC5w3HqTeDdltRxgES82G62Oo0R qpOpLHCTH3K/Egvs2irmRYrKOdTEosWJmRJXwzhj0xH6E7NYv0RvaKXlvX642pbZ0x jNQ9DhNE8HAsQ== Date: Mon, 21 Mar 2022 14:39:44 +0000 From: Will Deacon To: Catalin Marinas Subject: Re: [PATCH v1 4/7] arm64/pgtable: support __HAVE_ARCH_PTE_SWP_EXCLUSIVE Message-ID: <20220321143944.GD11145@willie-the-truck> References: <20220315141837.137118-1-david@redhat.com> <20220315141837.137118-5-david@redhat.com> <20220321143802.GC11145@willie-the-truck> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220321143802.GC11145@willie-the-truck> User-Agent: Mutt/1.10.1 (2018-07-13) X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: x86@kernel.org, Jan Kara , David Hildenbrand , Yang Shi , Dave Hansen , Peter Xu , Michal Hocko , linux-mm@kvack.org, Nadav Amit , Liang Zhang , Borislav Petkov , Alexander Gordeev , Christoph Hellwig , Paul Mackerras , Andrea Arcangeli , linux-s390@vger.kernel.org, Vasily Gorbik , Jann Horn , Hugh Dickins , Matthew Wilcox , Mike Rapoport , Ingo Molnar , linux-arm-kernel@lists.infradead.org, Jason Gunthorpe , David Rientjes , Pedro Gomes , Rik van Riel , John Hubbard , Heiko Carstens , Shakeel Butt , Oleg Nesterov , Thomas Gleixner , Vlastimil Babka , Oded Gabbay , linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Donald Dutile , Andrew Morton , Linus Torvalds , Roman Gushchin , "Kirill A . Shutemov" , Mike Kravetz Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Mon, Mar 21, 2022 at 02:38:02PM +0000, Will Deacon wrote: > On Wed, Mar 16, 2022 at 06:27:01PM +0000, Catalin Marinas wrote: > > On Tue, Mar 15, 2022 at 03:18:34PM +0100, David Hildenbrand wrote: > > > diff --git a/arch/arm64/include/asm/pgtable-prot.h b/arch/arm64/include/asm/pgtable-prot.h > > > index b1e1b74d993c..62e0ebeed720 100644 > > > --- a/arch/arm64/include/asm/pgtable-prot.h > > > +++ b/arch/arm64/include/asm/pgtable-prot.h > > > @@ -14,6 +14,7 @@ > > > * Software defined PTE bits definition. > > > */ > > > #define PTE_WRITE (PTE_DBM) /* same as DBM (51) */ > > > +#define PTE_SWP_EXCLUSIVE (_AT(pteval_t, 1) << 2) /* only for swp ptes */ > > > > I think we can use bit 1 here. > > > > > @@ -909,12 +925,13 @@ static inline pmd_t pmdp_establish(struct vm_area_struct *vma, > > > /* > > > * Encode and decode a swap entry: > > > * bits 0-1: present (must be zero) > > > - * bits 2-7: swap type > > > + * bits 2: remember PG_anon_exclusive > > > + * bits 3-7: swap type > > > * bits 8-57: swap offset > > > * bit 58: PTE_PROT_NONE (must be zero) > > > > I don't remember exactly why we reserved bits 0 and 1 when, from the > > hardware perspective, it's sufficient for bit 0 to be 0 and the whole > > pte becomes invalid. We use bit 1 as the 'table' bit (when 0 at pmd > > level, it's a huge page) but we shouldn't check for this on a swap > > entry. > > I'm a little worried that when we're dealing with huge mappings at the > PMD level we might lose the ability to distinguish them from a pte-level > mapping with this new flag set if we use bit 1. A similar issue to this > was fixed a long time ago by 59911ca4325d ("ARM64: mm: Move PTE_PROT_NONE > bit") when we used to use bit 1 for PTE_PROT_NONE. > > Is something like: > > pmd_to_swp_entry(swp_entry_to_pmd(pmd)); > > supposed to preserve the original pmd? I'm not sure that's guaranteed > after this change if bit 1 can be cleared in the process -- we could end > up with a pte, which the hardware would interpret as a table entry and > end up with really bad things happening. (I got this back to front: having the bit set rather than cleared would be an issue, but the overall point remains). Will From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 83466C433EF for ; Mon, 21 Mar 2022 14:41:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=zXxdPogfMq07z7HMGRwG4tPb/PF4Fli3hrvkxkXCyuY=; b=alNeBMYDMIWMdf sI7SVElz2q+CZBSdfz9TETriU8vwuzlSXY/cPVu4w+NJDhkg+3yacsCs1Q5aza2hywLL1Lc/f+GjZ oaNjVxygWjSZMT9c7rKBdYycvDtjMHapXDoo05oa4dy8Hkqmr8Xem+30fxYOHfL1ZhOy1IYZcTitE q0zItbPmDUgUys45TPUvBzSfApF9oExZ5IQccz1kQHSW4ZYaZS+PD4fe96JryIi7rJh8CvISV4ZX8 u9P4xybgb/BVUP7zN72BSvZ70GQFBT1Mf4smP7zpREWYtJWKlgUdTmXPDXZxxLsYQ0PdkTSKWOdnz hIXCpm/W/+46QRS9ZZYw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nWJCU-00845F-Ex; Mon, 21 Mar 2022 14:40:02 +0000 Received: from ams.source.kernel.org ([2604:1380:4601:e00::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nWJCQ-00843V-4l for linux-arm-kernel@lists.infradead.org; Mon, 21 Mar 2022 14:39:59 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id CD73FB8170E; Mon, 21 Mar 2022 14:39:56 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 06D4EC340E8; Mon, 21 Mar 2022 14:39:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1647873595; bh=DvATwoHTxnArnbHtADD5Mg71Fi3pHjfQ9J9ORoxi+UI=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=NYmgDU7FL+wbRjIgi+f4VRnRmFWuAVTkl7g3kOamPyLk64U7Ax14VO3SKbCcdbC0W Bu9cW7deMtVw3T9rWU9seP7toK06zScpQrc2iTe/0KTcA24G/CBgcGsaI2DXLcBtSS ofo0rT/LwpSJdn0mJVwpa2dzNYgcP03+DZc32HeKsxMcy4TvJk7IWLgPLjvLaDUWBQ bAUN+fbbDqXv/lYRyuXk/5NpPINOtFu8yiE1SLqeC5w3HqTeDdltRxgES82G62Oo0R qpOpLHCTH3K/Egvs2irmRYrKOdTEosWJmRJXwzhj0xH6E7NYv0RvaKXlvX642pbZ0x jNQ9DhNE8HAsQ== Date: Mon, 21 Mar 2022 14:39:44 +0000 From: Will Deacon To: Catalin Marinas Cc: David Hildenbrand , linux-kernel@vger.kernel.org, Andrew Morton , Hugh Dickins , Linus Torvalds , David Rientjes , Shakeel Butt , John Hubbard , Jason Gunthorpe , Mike Kravetz , Mike Rapoport , Yang Shi , "Kirill A . Shutemov" , Matthew Wilcox , Vlastimil Babka , Jann Horn , Michal Hocko , Nadav Amit , Rik van Riel , Roman Gushchin , Andrea Arcangeli , Peter Xu , Donald Dutile , Christoph Hellwig , Oleg Nesterov , Jan Kara , Liang Zhang , Pedro Gomes , Oded Gabbay , Michael Ellerman , Benjamin Herrenschmidt , Paul Mackerras , Heiko Carstens , Vasily Gorbik , Alexander Gordeev , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , linux-mm@kvack.org, x86@kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org Subject: Re: [PATCH v1 4/7] arm64/pgtable: support __HAVE_ARCH_PTE_SWP_EXCLUSIVE Message-ID: <20220321143944.GD11145@willie-the-truck> References: <20220315141837.137118-1-david@redhat.com> <20220315141837.137118-5-david@redhat.com> <20220321143802.GC11145@willie-the-truck> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220321143802.GC11145@willie-the-truck> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220321_073958_489273_FB35632D X-CRM114-Status: GOOD ( 30.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Mar 21, 2022 at 02:38:02PM +0000, Will Deacon wrote: > On Wed, Mar 16, 2022 at 06:27:01PM +0000, Catalin Marinas wrote: > > On Tue, Mar 15, 2022 at 03:18:34PM +0100, David Hildenbrand wrote: > > > diff --git a/arch/arm64/include/asm/pgtable-prot.h b/arch/arm64/include/asm/pgtable-prot.h > > > index b1e1b74d993c..62e0ebeed720 100644 > > > --- a/arch/arm64/include/asm/pgtable-prot.h > > > +++ b/arch/arm64/include/asm/pgtable-prot.h > > > @@ -14,6 +14,7 @@ > > > * Software defined PTE bits definition. > > > */ > > > #define PTE_WRITE (PTE_DBM) /* same as DBM (51) */ > > > +#define PTE_SWP_EXCLUSIVE (_AT(pteval_t, 1) << 2) /* only for swp ptes */ > > > > I think we can use bit 1 here. > > > > > @@ -909,12 +925,13 @@ static inline pmd_t pmdp_establish(struct vm_area_struct *vma, > > > /* > > > * Encode and decode a swap entry: > > > * bits 0-1: present (must be zero) > > > - * bits 2-7: swap type > > > + * bits 2: remember PG_anon_exclusive > > > + * bits 3-7: swap type > > > * bits 8-57: swap offset > > > * bit 58: PTE_PROT_NONE (must be zero) > > > > I don't remember exactly why we reserved bits 0 and 1 when, from the > > hardware perspective, it's sufficient for bit 0 to be 0 and the whole > > pte becomes invalid. We use bit 1 as the 'table' bit (when 0 at pmd > > level, it's a huge page) but we shouldn't check for this on a swap > > entry. > > I'm a little worried that when we're dealing with huge mappings at the > PMD level we might lose the ability to distinguish them from a pte-level > mapping with this new flag set if we use bit 1. A similar issue to this > was fixed a long time ago by 59911ca4325d ("ARM64: mm: Move PTE_PROT_NONE > bit") when we used to use bit 1 for PTE_PROT_NONE. > > Is something like: > > pmd_to_swp_entry(swp_entry_to_pmd(pmd)); > > supposed to preserve the original pmd? I'm not sure that's guaranteed > after this change if bit 1 can be cleared in the process -- we could end > up with a pte, which the hardware would interpret as a table entry and > end up with really bad things happening. (I got this back to front: having the bit set rather than cleared would be an issue, but the overall point remains). Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel