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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id i15-20020a63b30f000000b003803aee35a2sm15342644pgf.31.2022.03.21.08.27.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 08:27:22 -0700 (PDT) From: Andy Chiu To: radhey.shyam.pandey@xilinx.com, robert.hancock@calian.com, michal.simek@xilinx.com Cc: davem@davemloft.net, kuba@kernel.org, pabeni@redhat.com, robh+dt@kernel.org, linux@armlinux.org.uk, andrew@lunn.ch, netdev@vger.kernel.org, devicetree@vger.kernel.org, Andy Chiu , Greentime Hu Subject: [PATCH v4 3/4] dt-bindings: net: xilinx_axienet: add pcs-handle attribute Date: Mon, 21 Mar 2022 23:25:14 +0800 Message-Id: <20220321152515.287119-3-andy.chiu@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220321152515.287119-1-andy.chiu@sifive.com> References: <20220321152515.287119-1-andy.chiu@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Document the new pcs-handle attribute to support connecting to an external PHY in SGMII or 1000Base-X modes through the internal PCS/PMA PHY. Signed-off-by: Andy Chiu Reviewed-by: Greentime Hu --- Documentation/devicetree/bindings/net/xilinx_axienet.txt | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/net/xilinx_axienet.txt b/Documentation/devicetree/bindings/net/xilinx_axienet.txt index b8e4894bc634..ba720a2ea5fc 100644 --- a/Documentation/devicetree/bindings/net/xilinx_axienet.txt +++ b/Documentation/devicetree/bindings/net/xilinx_axienet.txt @@ -26,7 +26,8 @@ Required properties: specified, the TX/RX DMA interrupts should be on that node instead, and only the Ethernet core interrupt is optionally specified here. -- phy-handle : Should point to the external phy device. +- phy-handle : Should point to the external phy device if exists. Pointing + this to the PCS/PMA PHY is deprecated and should be avoided. See ethernet.txt file in the same directory. - xlnx,rxmem : Set to allocated memory buffer for Rx/Tx in the hardware @@ -68,6 +69,11 @@ Optional properties: required through the core's MDIO interface (i.e. always, unless the PHY is accessed through a different bus). + - pcs-handle: Phandle to the internal PCS/PMA PHY in SGMII or 1000Base-X + modes, where "pcs-handle" should be preferably used to point + to the PCS/PMA PHY, and "phy-handle" should point to an + external PHY if exists. + Example: axi_ethernet_eth: ethernet@40c00000 { compatible = "xlnx,axi-ethernet-1.00.a"; -- 2.34.1