All of lore.kernel.org
 help / color / mirror / Atom feed
From: Gaurav Jain <gaurav.jain@nxp.com>
To: u-boot@lists.denx.de, Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>, Peng Fan <peng.fan@nxp.com>,
	Simon Glass <sjg@chromium.org>, Michael Walle <michael@walle.cc>,
	Priyanka Jain <priyanka.jain@nxp.com>, Ye Li <ye.li@nxp.com>,
	Horia Geanta <horia.geanta@nxp.com>, Ji Luo <ji.luo@nxp.com>,
	Franck Lenormand <franck.lenormand@nxp.com>,
	Silvano Di Ninno <silvano.dininno@nxp.com>,
	Sahil malhotra <sahil.malhotra@nxp.com>,
	Pankaj Gupta <pankaj.gupta@nxp.com>,
	Varun Sethi <V.Sethi@nxp.com>,
	"NXP i . MX U-Boot Team" <uboot-imx@nxp.com>,
	Shengzhou Liu <Shengzhou.Liu@nxp.com>,
	Mingkai Hu <mingkai.hu@nxp.com>,
	Rajesh Bhagat <rajesh.bhagat@nxp.com>,
	Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>,
	Wasim Khan <wasim.khan@nxp.com>,
	Alison Wang <alison.wang@nxp.com>,
	Pramod Kumar <pramod.kumar_1@nxp.com>,
	Tang Yuantian <andy.tang@nxp.com>,
	Adrian Alonso <adrian.alonso@nxp.com>,
	Vladimir Oltean <olteanv@gmail.com>,
	ZHIZHIKIN Andrey <andrey.zhizhikin@leica-geosystems.com>,
	Michael Trimarchi <michael@amarulasolutions.com>,
	Gaurav Jain <gaurav.jain@nxp.com>
Subject: [PATCH v11 08/14] i.MX8: Add crypto node in device tree
Date: Thu, 24 Mar 2022 11:50:32 +0530	[thread overview]
Message-ID: <20220324062038.2187-9-gaurav.jain@nxp.com> (raw)
In-Reply-To: <20220324062038.2187-1-gaurav.jain@nxp.com>

i.MX8(QM/QXP) - updated device tree for supporting DM in SPL.

disabled use of JR1 in SPL and uboot, as JR1 is reserved
for SECO FW.

Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
---
 arch/arm/dts/fsl-imx8dx.dtsi             | 61 +++++++++++++++++++++++-
 arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi  | 34 ++++++++++++-
 arch/arm/dts/fsl-imx8qm.dtsi             | 61 +++++++++++++++++++++++-
 arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi | 34 ++++++++++++-
 4 files changed, 186 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/fsl-imx8dx.dtsi b/arch/arm/dts/fsl-imx8dx.dtsi
index 7d95cf0b7d..63a56699b5 100644
--- a/arch/arm/dts/fsl-imx8dx.dtsi
+++ b/arch/arm/dts/fsl-imx8dx.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -261,6 +261,30 @@
 				power-domains = <&pd_dma>;
 			};
 		};
+
+		pd_caam: PD_CAAM {
+			compatible = "nxp,imx8-pd";
+			reg = <SC_R_NONE>;
+			#power-domain-cells = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pd_caam_jr1: PD_CAAM_JR1 {
+				reg = <SC_R_CAAM_JR1>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_caam>;
+			};
+			pd_caam_jr2: PD_CAAM_JR2 {
+				reg = <SC_R_CAAM_JR2>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_caam>;
+			};
+			pd_caam_jr3: PD_CAAM_JR3 {
+				reg = <SC_R_CAAM_JR3>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_caam>;
+			};
+		};
 	};
 
 	i2c0: i2c@5a800000 {
@@ -609,6 +633,41 @@
 			};
 		};
 	};
+
+	crypto: caam@0x31400000 {
+		compatible = "fsl,sec-v4.0";
+		reg = <0 0x31400000 0 0x400000>;
+		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0 0x31400000 0x400000>;
+		fsl,first-jr-index = <2>;
+		fsl,sec-era = <9>;
+
+		sec_jr1: jr1@0x20000 {
+			compatible = "fsl,sec-v4.0-job-ring";
+			reg = <0x20000 0x1000>;
+			interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&pd_caam_jr1>;
+			status = "disabled";
+		};
+
+		sec_jr2: jr2@30000 {
+			compatible = "fsl,sec-v4.0-job-ring";
+			reg = <0x30000 0x1000>;
+			interrupts = <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&pd_caam_jr2>;
+			status = "okay";
+		};
+
+		sec_jr3: jr3@40000 {
+			compatible = "fsl,sec-v4.0-job-ring";
+			reg = <0x40000 0x1000>;
+			interrupts = <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&pd_caam_jr3>;
+			status = "okay";
+		};
+	};
 };
 
 &A35_0 {
diff --git a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
index 9e0d264b71..a95209e141 100644
--- a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
+++ b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
  */
 
 &{/imx8qm-pm} {
@@ -80,6 +80,22 @@
 	u-boot,dm-spl;
 };
 
+&pd_caam {
+	u-boot,dm-spl;
+};
+
+&pd_caam_jr1 {
+	u-boot,dm-spl;
+};
+
+&pd_caam_jr2 {
+	u-boot,dm-spl;
+};
+
+&pd_caam_jr3 {
+	u-boot,dm-spl;
+};
+
 &gpio0 {
 	u-boot,dm-spl;
 };
@@ -126,3 +142,19 @@
 	sd-uhs-sdr104;
 	sd-uhs-ddr50;
 };
+
+&crypto {
+	u-boot,dm-spl;
+};
+
+&sec_jr1 {
+	u-boot,dm-spl;
+};
+
+&sec_jr2 {
+	u-boot,dm-spl;
+};
+
+&sec_jr3 {
+	u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/fsl-imx8qm.dtsi b/arch/arm/dts/fsl-imx8qm.dtsi
index 88aeaf65b3..517fb13cad 100644
--- a/arch/arm/dts/fsl-imx8qm.dtsi
+++ b/arch/arm/dts/fsl-imx8qm.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -235,6 +235,30 @@
 				wakeup-irq = <349>;
 			};
 		};
+
+		pd_caam: PD_CAAM {
+			compatible = "nxp,imx8-pd";
+			reg = <SC_R_NONE>;
+			#power-domain-cells = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pd_caam_jr1: PD_CAAM_JR1 {
+				reg = <SC_R_CAAM_JR1>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_caam>;
+			};
+			pd_caam_jr2: PD_CAAM_JR2 {
+				reg = <SC_R_CAAM_JR2>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_caam>;
+			};
+			pd_caam_jr3: PD_CAAM_JR3 {
+				reg = <SC_R_CAAM_JR3>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_caam>;
+			};
+		};
 	};
 
 	i2c0: i2c@5a800000 {
@@ -556,6 +580,41 @@
 		power-domains = <&pd_conn_enet1>;
 		status = "disabled";
 	};
+
+	crypto: caam@0x31400000 {
+		compatible = "fsl,sec-v4.0";
+		reg = <0 0x31400000 0 0x400000>;
+		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0 0x31400000 0x400000>;
+		fsl,first-jr-index = <2>;
+		fsl,sec-era = <9>;
+
+		sec_jr1: jr1@0x20000 {
+			compatible = "fsl,sec-v4.0-job-ring";
+			reg = <0x20000 0x1000>;
+			interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&pd_caam_jr1>;
+			status = "disabled";
+		};
+
+		sec_jr2: jr2@30000 {
+			compatible = "fsl,sec-v4.0-job-ring";
+			reg = <0x30000 0x1000>;
+			interrupts = <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&pd_caam_jr2>;
+			status = "okay";
+		};
+
+		sec_jr3: jr3@40000 {
+			compatible = "fsl,sec-v4.0-job-ring";
+			reg = <0x40000 0x1000>;
+			interrupts = <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&pd_caam_jr3>;
+			status = "okay";
+		};
+	};
 };
 
 &A53_0 {
diff --git a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
index 701af4434d..ae037c7550 100644
--- a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
+++ b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
  */
 
 &{/imx8qx-pm} {
@@ -80,6 +80,22 @@
 	u-boot,dm-spl;
 };
 
+&pd_caam {
+	u-boot,dm-spl;
+};
+
+&pd_caam_jr1 {
+	u-boot,dm-spl;
+};
+
+&pd_caam_jr2 {
+	u-boot,dm-spl;
+};
+
+&pd_caam_jr3 {
+	u-boot,dm-spl;
+};
+
 &gpio0 {
 	u-boot,dm-spl;
 };
@@ -126,3 +142,19 @@
 	sd-uhs-sdr104;
 	sd-uhs-ddr50;
 };
+
+&crypto {
+	u-boot,dm-spl;
+};
+
+&sec_jr1 {
+	u-boot,dm-spl;
+};
+
+&sec_jr2 {
+	u-boot,dm-spl;
+};
+
+&sec_jr3 {
+	u-boot,dm-spl;
+};
-- 
2.17.1


  parent reply	other threads:[~2022-03-24  6:23 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-24  6:20 [PATCH v11 00/14] Add CAAM driver model support Gaurav Jain
2022-03-24  6:20 ` [PATCH v11 01/14] crypto/fsl: Add support for CAAM Job ring driver model Gaurav Jain
2022-03-28  8:36   ` Gaurav Jain
2022-03-28 13:52     ` Michael Nazzareno Trimarchi
2022-04-11 18:43   ` Stefano Babic
2022-04-12  7:20     ` [EXT] " Gaurav Jain
2022-04-12  7:34       ` Stefano Babic
2022-04-12 13:34   ` sbabic
     [not found]   ` <7d0648b0-338d-4b01-9da5-269c7cea0031@VE1EUR01FT051.eop-EUR01.prod.protection.outlook.com>
2022-04-13  5:35     ` [EXT] " Gaurav Jain
2022-04-13  6:57       ` Stefano Babic
2022-03-24  6:20 ` [PATCH v11 02/14] i.MX8M: crypto: updated device tree for supporting DM in SPL Gaurav Jain
2022-04-12 13:34   ` sbabic
2022-03-24  6:20 ` [PATCH v11 03/14] crypto/fsl: i.MX8M: Enable Job ring driver model Gaurav Jain
2022-04-12 13:34   ` sbabic
2022-03-24  6:20 ` [PATCH v11 04/14] mx6sabre: Remove unnecessary SPL configs Gaurav Jain
2022-04-12 13:33   ` sbabic
2022-03-24  6:20 ` [PATCH v11 05/14] i.MX6: Enable Job ring driver model Gaurav Jain
2022-04-12 13:34   ` sbabic
2022-03-24  6:20 ` [PATCH v11 06/14] i.MX7: " Gaurav Jain
2022-04-12 13:34   ` sbabic
2022-03-24  6:20 ` [PATCH v11 07/14] i.MX7ULP: " Gaurav Jain
2022-04-12 13:34   ` sbabic
2022-03-24  6:20 ` Gaurav Jain [this message]
2022-04-12 13:34   ` [PATCH v11 08/14] i.MX8: Add crypto node in device tree sbabic
2022-03-24  6:20 ` [PATCH v11 09/14] crypto/fsl: i.MX8: Enable Job ring driver model Gaurav Jain
2022-04-12 13:34   ` sbabic
2022-03-24  6:20 ` [PATCH v11 10/14] Layerscape: Add crypto node in device tree Gaurav Jain
2022-04-12 13:34   ` sbabic
2022-03-24  6:20 ` [PATCH v11 11/14] Layerscape: Enable Job ring driver model Gaurav Jain
2022-04-12 13:34   ` sbabic
2022-03-24  6:20 ` [PATCH v11 12/14] PPC: Add crypto node in device tree Gaurav Jain
2022-04-12 13:34   ` sbabic
2022-03-24  6:20 ` [PATCH v11 13/14] PPC: Enable Job ring driver model Gaurav Jain
2022-04-12 13:34   ` sbabic
2022-03-24  6:20 ` [PATCH v11 14/14] update CAAM MAINTAINER Gaurav Jain
2022-04-12 13:34   ` sbabic

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20220324062038.2187-9-gaurav.jain@nxp.com \
    --to=gaurav.jain@nxp.com \
    --cc=Shengzhou.Liu@nxp.com \
    --cc=V.Sethi@nxp.com \
    --cc=adrian.alonso@nxp.com \
    --cc=alison.wang@nxp.com \
    --cc=andrey.zhizhikin@leica-geosystems.com \
    --cc=andy.tang@nxp.com \
    --cc=festevam@gmail.com \
    --cc=franck.lenormand@nxp.com \
    --cc=horia.geanta@nxp.com \
    --cc=ji.luo@nxp.com \
    --cc=meenakshi.aggarwal@nxp.com \
    --cc=michael@amarulasolutions.com \
    --cc=michael@walle.cc \
    --cc=mingkai.hu@nxp.com \
    --cc=olteanv@gmail.com \
    --cc=pankaj.gupta@nxp.com \
    --cc=peng.fan@nxp.com \
    --cc=pramod.kumar_1@nxp.com \
    --cc=priyanka.jain@nxp.com \
    --cc=rajesh.bhagat@nxp.com \
    --cc=sahil.malhotra@nxp.com \
    --cc=sbabic@denx.de \
    --cc=silvano.dininno@nxp.com \
    --cc=sjg@chromium.org \
    --cc=u-boot@lists.denx.de \
    --cc=uboot-imx@nxp.com \
    --cc=wasim.khan@nxp.com \
    --cc=ye.li@nxp.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.