* [PATCH v5 0/2] phy: mediatek: Add PCIe PHY driver
@ 2022-03-26 2:27 ` Jianjun Wang
0 siblings, 0 replies; 32+ messages in thread
From: Jianjun Wang @ 2022-03-26 2:27 UTC (permalink / raw)
To: Chunfeng Yun, Kishon Vijay Abraham I, Vinod Koul, Rob Herring,
Matthias Brugger, Chen-Yu Tsai, AngeloGioacchino Del Regno,
Krzysztof Kozlowski
Cc: Wei-Shun Chang, Jianjun Wang, linux-arm-kernel, linux-mediatek,
linux-phy, devicetree, linux-kernel, rex-bc.chen, randy.wu,
jieyy.yang, chuanjia.liu, qizhong.cheng, jian.yang
These series patches add support for PCIe PHY driver on MediaTek chipsets.
Changes in v5:
1. Fix typo in kerneldoc: "eFues" => "eFuse".
Changes in v4:
1. Fix no return when calling dev_err_probe.
Changes in v3:
1. Add introductions for structure members;
2. Add SoC dependent data;
3. Dynamically allocate efuse data;
4. Check return value if it's an -EPROBE_DEFER.
Changes in v2:
1. Add specific compatible name;
2. Read NVMEM data at probe time;
3. Fix typos.
Jianjun Wang (2):
dt-bindings: phy: mediatek: Add YAML schema for PCIe PHY
phy: mediatek: Add PCIe PHY driver
.../bindings/phy/mediatek,pcie-phy.yaml | 75 +++++
drivers/phy/mediatek/Kconfig | 11 +
drivers/phy/mediatek/Makefile | 1 +
drivers/phy/mediatek/phy-mtk-pcie.c | 272 ++++++++++++++++++
4 files changed, 359 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml
create mode 100644 drivers/phy/mediatek/phy-mtk-pcie.c
--
2.18.0
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v5 0/2] phy: mediatek: Add PCIe PHY driver
@ 2022-03-26 2:27 ` Jianjun Wang
0 siblings, 0 replies; 32+ messages in thread
From: Jianjun Wang @ 2022-03-26 2:27 UTC (permalink / raw)
To: Chunfeng Yun, Kishon Vijay Abraham I, Vinod Koul, Rob Herring,
Matthias Brugger, Chen-Yu Tsai, AngeloGioacchino Del Regno,
Krzysztof Kozlowski
Cc: Wei-Shun Chang, Jianjun Wang, linux-arm-kernel, linux-mediatek,
linux-phy, devicetree, linux-kernel, rex-bc.chen, randy.wu,
jieyy.yang, chuanjia.liu, qizhong.cheng, jian.yang
These series patches add support for PCIe PHY driver on MediaTek chipsets.
Changes in v5:
1. Fix typo in kerneldoc: "eFues" => "eFuse".
Changes in v4:
1. Fix no return when calling dev_err_probe.
Changes in v3:
1. Add introductions for structure members;
2. Add SoC dependent data;
3. Dynamically allocate efuse data;
4. Check return value if it's an -EPROBE_DEFER.
Changes in v2:
1. Add specific compatible name;
2. Read NVMEM data at probe time;
3. Fix typos.
Jianjun Wang (2):
dt-bindings: phy: mediatek: Add YAML schema for PCIe PHY
phy: mediatek: Add PCIe PHY driver
.../bindings/phy/mediatek,pcie-phy.yaml | 75 +++++
drivers/phy/mediatek/Kconfig | 11 +
drivers/phy/mediatek/Makefile | 1 +
drivers/phy/mediatek/phy-mtk-pcie.c | 272 ++++++++++++++++++
4 files changed, 359 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml
create mode 100644 drivers/phy/mediatek/phy-mtk-pcie.c
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v5 0/2] phy: mediatek: Add PCIe PHY driver
@ 2022-03-26 2:27 ` Jianjun Wang
0 siblings, 0 replies; 32+ messages in thread
From: Jianjun Wang @ 2022-03-26 2:27 UTC (permalink / raw)
To: Chunfeng Yun, Kishon Vijay Abraham I, Vinod Koul, Rob Herring,
Matthias Brugger, Chen-Yu Tsai, AngeloGioacchino Del Regno,
Krzysztof Kozlowski
Cc: Wei-Shun Chang, Jianjun Wang, linux-arm-kernel, linux-mediatek,
linux-phy, devicetree, linux-kernel, rex-bc.chen, randy.wu,
jieyy.yang, chuanjia.liu, qizhong.cheng, jian.yang
These series patches add support for PCIe PHY driver on MediaTek chipsets.
Changes in v5:
1. Fix typo in kerneldoc: "eFues" => "eFuse".
Changes in v4:
1. Fix no return when calling dev_err_probe.
Changes in v3:
1. Add introductions for structure members;
2. Add SoC dependent data;
3. Dynamically allocate efuse data;
4. Check return value if it's an -EPROBE_DEFER.
Changes in v2:
1. Add specific compatible name;
2. Read NVMEM data at probe time;
3. Fix typos.
Jianjun Wang (2):
dt-bindings: phy: mediatek: Add YAML schema for PCIe PHY
phy: mediatek: Add PCIe PHY driver
.../bindings/phy/mediatek,pcie-phy.yaml | 75 +++++
drivers/phy/mediatek/Kconfig | 11 +
drivers/phy/mediatek/Makefile | 1 +
drivers/phy/mediatek/phy-mtk-pcie.c | 272 ++++++++++++++++++
4 files changed, 359 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml
create mode 100644 drivers/phy/mediatek/phy-mtk-pcie.c
--
2.18.0
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v5 0/2] phy: mediatek: Add PCIe PHY driver
@ 2022-03-26 2:27 ` Jianjun Wang
0 siblings, 0 replies; 32+ messages in thread
From: Jianjun Wang @ 2022-03-26 2:27 UTC (permalink / raw)
To: Chunfeng Yun, Kishon Vijay Abraham I, Vinod Koul, Rob Herring,
Matthias Brugger, Chen-Yu Tsai, AngeloGioacchino Del Regno,
Krzysztof Kozlowski
Cc: Wei-Shun Chang, Jianjun Wang, linux-arm-kernel, linux-mediatek,
linux-phy, devicetree, linux-kernel, rex-bc.chen, randy.wu,
jieyy.yang, chuanjia.liu, qizhong.cheng, jian.yang
These series patches add support for PCIe PHY driver on MediaTek chipsets.
Changes in v5:
1. Fix typo in kerneldoc: "eFues" => "eFuse".
Changes in v4:
1. Fix no return when calling dev_err_probe.
Changes in v3:
1. Add introductions for structure members;
2. Add SoC dependent data;
3. Dynamically allocate efuse data;
4. Check return value if it's an -EPROBE_DEFER.
Changes in v2:
1. Add specific compatible name;
2. Read NVMEM data at probe time;
3. Fix typos.
Jianjun Wang (2):
dt-bindings: phy: mediatek: Add YAML schema for PCIe PHY
phy: mediatek: Add PCIe PHY driver
.../bindings/phy/mediatek,pcie-phy.yaml | 75 +++++
drivers/phy/mediatek/Kconfig | 11 +
drivers/phy/mediatek/Makefile | 1 +
drivers/phy/mediatek/phy-mtk-pcie.c | 272 ++++++++++++++++++
4 files changed, 359 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml
create mode 100644 drivers/phy/mediatek/phy-mtk-pcie.c
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v5 1/2] dt-bindings: phy: mediatek: Add YAML schema for PCIe PHY
2022-03-26 2:27 ` Jianjun Wang
(?)
(?)
@ 2022-03-26 2:27 ` Jianjun Wang
-1 siblings, 0 replies; 32+ messages in thread
From: Jianjun Wang @ 2022-03-26 2:27 UTC (permalink / raw)
To: Chunfeng Yun, Kishon Vijay Abraham I, Vinod Koul, Rob Herring,
Matthias Brugger, Chen-Yu Tsai, AngeloGioacchino Del Regno,
Krzysztof Kozlowski
Cc: Wei-Shun Chang, Jianjun Wang, linux-arm-kernel, linux-mediatek,
linux-phy, devicetree, linux-kernel, rex-bc.chen, randy.wu,
jieyy.yang, chuanjia.liu, qizhong.cheng, jian.yang
Add YAML schema documentation for PCIe PHY on MediaTek chipsets.
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
---
.../bindings/phy/mediatek,pcie-phy.yaml | 75 +++++++++++++++++++
1 file changed, 75 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml
new file mode 100644
index 000000000000..422750cc4121
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/mediatek,pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek PCIe PHY
+
+maintainers:
+ - Jianjun Wang <jianjun.wang@mediatek.com>
+
+description: |
+ The PCIe PHY supports physical layer functionality for PCIe Gen3 port.
+
+properties:
+ compatible:
+ const: mediatek,mt8195-pcie-phy
+
+ reg:
+ maxItems: 1
+
+ reg-names:
+ items:
+ - const: sif
+
+ "#phy-cells":
+ const: 0
+
+ nvmem-cells:
+ maxItems: 7
+ description:
+ Phandles to nvmem cell that contains the efuse data, if unspecified,
+ default value is used.
+
+ nvmem-cell-names:
+ items:
+ - const: glb_intr
+ - const: tx_ln0_pmos
+ - const: tx_ln0_nmos
+ - const: rx_ln0
+ - const: tx_ln1_pmos
+ - const: tx_ln1_nmos
+ - const: rx_ln1
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ phy@11e80000 {
+ compatible = "mediatek,mt8195-pcie-phy";
+ #phy-cells = <0>;
+ reg = <0x11e80000 0x10000>;
+ reg-names = "sif";
+ nvmem-cells = <&pciephy_glb_intr>,
+ <&pciephy_tx_ln0_pmos>,
+ <&pciephy_tx_ln0_nmos>,
+ <&pciephy_rx_ln0>,
+ <&pciephy_tx_ln1_pmos>,
+ <&pciephy_tx_ln1_nmos>,
+ <&pciephy_rx_ln1>;
+ nvmem-cell-names = "glb_intr", "tx_ln0_pmos",
+ "tx_ln0_nmos", "rx_ln0",
+ "tx_ln1_pmos", "tx_ln1_nmos",
+ "rx_ln1";
+ power-domains = <&spm 2>;
+ };
--
2.18.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v5 1/2] dt-bindings: phy: mediatek: Add YAML schema for PCIe PHY
@ 2022-03-26 2:27 ` Jianjun Wang
0 siblings, 0 replies; 32+ messages in thread
From: Jianjun Wang @ 2022-03-26 2:27 UTC (permalink / raw)
To: Chunfeng Yun, Kishon Vijay Abraham I, Vinod Koul, Rob Herring,
Matthias Brugger, Chen-Yu Tsai, AngeloGioacchino Del Regno,
Krzysztof Kozlowski
Cc: Wei-Shun Chang, Jianjun Wang, linux-arm-kernel, linux-mediatek,
linux-phy, devicetree, linux-kernel, rex-bc.chen, randy.wu,
jieyy.yang, chuanjia.liu, qizhong.cheng, jian.yang
Add YAML schema documentation for PCIe PHY on MediaTek chipsets.
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
---
.../bindings/phy/mediatek,pcie-phy.yaml | 75 +++++++++++++++++++
1 file changed, 75 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml
new file mode 100644
index 000000000000..422750cc4121
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/mediatek,pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek PCIe PHY
+
+maintainers:
+ - Jianjun Wang <jianjun.wang@mediatek.com>
+
+description: |
+ The PCIe PHY supports physical layer functionality for PCIe Gen3 port.
+
+properties:
+ compatible:
+ const: mediatek,mt8195-pcie-phy
+
+ reg:
+ maxItems: 1
+
+ reg-names:
+ items:
+ - const: sif
+
+ "#phy-cells":
+ const: 0
+
+ nvmem-cells:
+ maxItems: 7
+ description:
+ Phandles to nvmem cell that contains the efuse data, if unspecified,
+ default value is used.
+
+ nvmem-cell-names:
+ items:
+ - const: glb_intr
+ - const: tx_ln0_pmos
+ - const: tx_ln0_nmos
+ - const: rx_ln0
+ - const: tx_ln1_pmos
+ - const: tx_ln1_nmos
+ - const: rx_ln1
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ phy@11e80000 {
+ compatible = "mediatek,mt8195-pcie-phy";
+ #phy-cells = <0>;
+ reg = <0x11e80000 0x10000>;
+ reg-names = "sif";
+ nvmem-cells = <&pciephy_glb_intr>,
+ <&pciephy_tx_ln0_pmos>,
+ <&pciephy_tx_ln0_nmos>,
+ <&pciephy_rx_ln0>,
+ <&pciephy_tx_ln1_pmos>,
+ <&pciephy_tx_ln1_nmos>,
+ <&pciephy_rx_ln1>;
+ nvmem-cell-names = "glb_intr", "tx_ln0_pmos",
+ "tx_ln0_nmos", "rx_ln0",
+ "tx_ln1_pmos", "tx_ln1_nmos",
+ "rx_ln1";
+ power-domains = <&spm 2>;
+ };
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v5 1/2] dt-bindings: phy: mediatek: Add YAML schema for PCIe PHY
@ 2022-03-26 2:27 ` Jianjun Wang
0 siblings, 0 replies; 32+ messages in thread
From: Jianjun Wang @ 2022-03-26 2:27 UTC (permalink / raw)
To: Chunfeng Yun, Kishon Vijay Abraham I, Vinod Koul, Rob Herring,
Matthias Brugger, Chen-Yu Tsai, AngeloGioacchino Del Regno,
Krzysztof Kozlowski
Cc: Wei-Shun Chang, Jianjun Wang, linux-arm-kernel, linux-mediatek,
linux-phy, devicetree, linux-kernel, rex-bc.chen, randy.wu,
jieyy.yang, chuanjia.liu, qizhong.cheng, jian.yang
Add YAML schema documentation for PCIe PHY on MediaTek chipsets.
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
---
.../bindings/phy/mediatek,pcie-phy.yaml | 75 +++++++++++++++++++
1 file changed, 75 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml
new file mode 100644
index 000000000000..422750cc4121
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/mediatek,pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek PCIe PHY
+
+maintainers:
+ - Jianjun Wang <jianjun.wang@mediatek.com>
+
+description: |
+ The PCIe PHY supports physical layer functionality for PCIe Gen3 port.
+
+properties:
+ compatible:
+ const: mediatek,mt8195-pcie-phy
+
+ reg:
+ maxItems: 1
+
+ reg-names:
+ items:
+ - const: sif
+
+ "#phy-cells":
+ const: 0
+
+ nvmem-cells:
+ maxItems: 7
+ description:
+ Phandles to nvmem cell that contains the efuse data, if unspecified,
+ default value is used.
+
+ nvmem-cell-names:
+ items:
+ - const: glb_intr
+ - const: tx_ln0_pmos
+ - const: tx_ln0_nmos
+ - const: rx_ln0
+ - const: tx_ln1_pmos
+ - const: tx_ln1_nmos
+ - const: rx_ln1
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ phy@11e80000 {
+ compatible = "mediatek,mt8195-pcie-phy";
+ #phy-cells = <0>;
+ reg = <0x11e80000 0x10000>;
+ reg-names = "sif";
+ nvmem-cells = <&pciephy_glb_intr>,
+ <&pciephy_tx_ln0_pmos>,
+ <&pciephy_tx_ln0_nmos>,
+ <&pciephy_rx_ln0>,
+ <&pciephy_tx_ln1_pmos>,
+ <&pciephy_tx_ln1_nmos>,
+ <&pciephy_rx_ln1>;
+ nvmem-cell-names = "glb_intr", "tx_ln0_pmos",
+ "tx_ln0_nmos", "rx_ln0",
+ "tx_ln1_pmos", "tx_ln1_nmos",
+ "rx_ln1";
+ power-domains = <&spm 2>;
+ };
--
2.18.0
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v5 1/2] dt-bindings: phy: mediatek: Add YAML schema for PCIe PHY
@ 2022-03-26 2:27 ` Jianjun Wang
0 siblings, 0 replies; 32+ messages in thread
From: Jianjun Wang @ 2022-03-26 2:27 UTC (permalink / raw)
To: Chunfeng Yun, Kishon Vijay Abraham I, Vinod Koul, Rob Herring,
Matthias Brugger, Chen-Yu Tsai, AngeloGioacchino Del Regno,
Krzysztof Kozlowski
Cc: Wei-Shun Chang, Jianjun Wang, linux-arm-kernel, linux-mediatek,
linux-phy, devicetree, linux-kernel, rex-bc.chen, randy.wu,
jieyy.yang, chuanjia.liu, qizhong.cheng, jian.yang
Add YAML schema documentation for PCIe PHY on MediaTek chipsets.
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
---
.../bindings/phy/mediatek,pcie-phy.yaml | 75 +++++++++++++++++++
1 file changed, 75 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml
new file mode 100644
index 000000000000..422750cc4121
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/mediatek,pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek PCIe PHY
+
+maintainers:
+ - Jianjun Wang <jianjun.wang@mediatek.com>
+
+description: |
+ The PCIe PHY supports physical layer functionality for PCIe Gen3 port.
+
+properties:
+ compatible:
+ const: mediatek,mt8195-pcie-phy
+
+ reg:
+ maxItems: 1
+
+ reg-names:
+ items:
+ - const: sif
+
+ "#phy-cells":
+ const: 0
+
+ nvmem-cells:
+ maxItems: 7
+ description:
+ Phandles to nvmem cell that contains the efuse data, if unspecified,
+ default value is used.
+
+ nvmem-cell-names:
+ items:
+ - const: glb_intr
+ - const: tx_ln0_pmos
+ - const: tx_ln0_nmos
+ - const: rx_ln0
+ - const: tx_ln1_pmos
+ - const: tx_ln1_nmos
+ - const: rx_ln1
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ phy@11e80000 {
+ compatible = "mediatek,mt8195-pcie-phy";
+ #phy-cells = <0>;
+ reg = <0x11e80000 0x10000>;
+ reg-names = "sif";
+ nvmem-cells = <&pciephy_glb_intr>,
+ <&pciephy_tx_ln0_pmos>,
+ <&pciephy_tx_ln0_nmos>,
+ <&pciephy_rx_ln0>,
+ <&pciephy_tx_ln1_pmos>,
+ <&pciephy_tx_ln1_nmos>,
+ <&pciephy_rx_ln1>;
+ nvmem-cell-names = "glb_intr", "tx_ln0_pmos",
+ "tx_ln0_nmos", "rx_ln0",
+ "tx_ln1_pmos", "tx_ln1_nmos",
+ "rx_ln1";
+ power-domains = <&spm 2>;
+ };
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v5 2/2] phy: mediatek: Add PCIe PHY driver
2022-03-26 2:27 ` Jianjun Wang
(?)
(?)
@ 2022-03-26 2:27 ` Jianjun Wang
-1 siblings, 0 replies; 32+ messages in thread
From: Jianjun Wang @ 2022-03-26 2:27 UTC (permalink / raw)
To: Chunfeng Yun, Kishon Vijay Abraham I, Vinod Koul, Rob Herring,
Matthias Brugger, Chen-Yu Tsai, AngeloGioacchino Del Regno,
Krzysztof Kozlowski
Cc: Wei-Shun Chang, Jianjun Wang, linux-arm-kernel, linux-mediatek,
linux-phy, devicetree, linux-kernel, rex-bc.chen, randy.wu,
jieyy.yang, chuanjia.liu, qizhong.cheng, jian.yang
Add PCIe GEN3 PHY driver support on MediaTek chipsets.
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/phy/mediatek/Kconfig | 11 ++
drivers/phy/mediatek/Makefile | 1 +
drivers/phy/mediatek/phy-mtk-pcie.c | 272 ++++++++++++++++++++++++++++
3 files changed, 284 insertions(+)
create mode 100644 drivers/phy/mediatek/phy-mtk-pcie.c
diff --git a/drivers/phy/mediatek/Kconfig b/drivers/phy/mediatek/Kconfig
index 55f8e6c048ab..387ed1b3f2cc 100644
--- a/drivers/phy/mediatek/Kconfig
+++ b/drivers/phy/mediatek/Kconfig
@@ -55,3 +55,14 @@ config PHY_MTK_MIPI_DSI
select GENERIC_PHY
help
Support MIPI DSI for Mediatek SoCs.
+
+config PHY_MTK_PCIE
+ tristate "MediaTek PCIe-PHY Driver"
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+ depends on OF
+ select GENERIC_PHY
+ help
+ Say 'Y' here to add support for MediaTek PCIe PHY driver.
+ This driver create the basic PHY instance and provides initialize
+ callback for PCIe GEN3 port, it supports software efuse
+ initialization.
diff --git a/drivers/phy/mediatek/Makefile b/drivers/phy/mediatek/Makefile
index ace660fbed3a..788c13147f63 100644
--- a/drivers/phy/mediatek/Makefile
+++ b/drivers/phy/mediatek/Makefile
@@ -6,6 +6,7 @@
obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
obj-$(CONFIG_PHY_MTK_UFS) += phy-mtk-ufs.o
obj-$(CONFIG_PHY_MTK_XSPHY) += phy-mtk-xsphy.o
+obj-$(CONFIG_PHY_MTK_PCIE) += phy-mtk-pcie.o
phy-mtk-hdmi-drv-y := phy-mtk-hdmi.o
phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt2701.o
diff --git a/drivers/phy/mediatek/phy-mtk-pcie.c b/drivers/phy/mediatek/phy-mtk-pcie.c
new file mode 100644
index 000000000000..d288655b6cff
--- /dev/null
+++ b/drivers/phy/mediatek/phy-mtk-pcie.c
@@ -0,0 +1,272 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ * Author: Jianjun Wang <jianjun.wang@mediatek.com>
+ */
+
+#include <linux/bits.h>
+#include <linux/compiler_types.h>
+#include <linux/module.h>
+#include <linux/nvmem-consumer.h>
+#include <linux/of_device.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include "phy-mtk-io.h"
+
+#define PEXTP_ANA_GLB_00_REG 0x9000
+#define PEXTP_ANA_LN0_TRX_REG 0xa000
+#define PEXTP_ANA_TX_OFFSET 0x04
+#define PEXTP_ANA_RX_OFFSET 0x3c
+#define PEXTP_ANA_LANE_OFFSET 0x100
+
+/* PEXTP_GLB_00_REG[28:24] Internal Resistor Selection of TX Bias Current */
+#define EFUSE_GLB_INTR_SEL GENMASK(28, 24)
+#define EFUSE_GLB_INTR_VAL(x) ((0x1f & (x)) << 24)
+
+/* PEXTP_ANA_LN_RX_REG[3:0] RX impedance selection */
+#define EFUSE_LN_RX_SEL GENMASK(3, 0)
+#define EFUSE_LN_RX_VAL(x) (0xf & (x))
+
+/* PEXTP_ANA_LN_TX_REG[5:2] TX PMOS impedance selection */
+#define EFUSE_LN_TX_PMOS_SEL GENMASK(5, 2)
+#define EFUSE_LN_TX_PMOS_VAL(x) ((0xf & (x)) << 2)
+
+/* PEXTP_ANA_LN_TX_REG[11:8] TX NMOS impedance selection */
+#define EFUSE_LN_TX_NMOS_SEL GENMASK(11, 8)
+#define EFUSE_LN_TX_NMOS_VAL(x) ((0xf & (x)) << 8)
+
+/**
+ * struct mtk_pcie_lane_efuse - eFuse data for each lane
+ * @tx_pmos: TX PMOS impedance selection data
+ * @tx_nmos: TX NMOS impedance selection data
+ * @rx_data: RX impedance selection data
+ * @lane_efuse_supported: software eFuse data is supported for this lane
+ */
+struct mtk_pcie_lane_efuse {
+ u32 tx_pmos;
+ u32 tx_nmos;
+ u32 rx_data;
+ bool lane_efuse_supported;
+};
+
+/**
+ * struct mtk_pcie_phy_data - phy data for each SoC
+ * @num_lanes: supported lane numbers
+ * @sw_efuse_supported: support software to load eFuse data
+ */
+struct mtk_pcie_phy_data {
+ int num_lanes;
+ bool sw_efuse_supported;
+};
+
+/**
+ * struct mtk_pcie_phy - PCIe phy driver main structure
+ * @dev: pointer to device
+ * @phy: pointer to generic phy
+ * @sif_base: IO mapped register base address of system interface
+ * @data: pointer to SoC dependent data
+ * @sw_efuse_en: software eFuse enable status
+ * @efuse_glb_intr: internal resistor selection of TX bias current data
+ * @efuse: pointer to eFuse data for each lane
+ */
+struct mtk_pcie_phy {
+ struct device *dev;
+ struct phy *phy;
+ void __iomem *sif_base;
+ const struct mtk_pcie_phy_data *data;
+
+ bool sw_efuse_en;
+ u32 efuse_glb_intr;
+ struct mtk_pcie_lane_efuse *efuse;
+};
+
+static void mtk_pcie_efuse_set_lane(struct mtk_pcie_phy *pcie_phy,
+ unsigned int lane)
+{
+ struct mtk_pcie_lane_efuse *data = &pcie_phy->efuse[lane];
+ void __iomem *addr;
+
+ if (!data->lane_efuse_supported)
+ return;
+
+ addr = pcie_phy->sif_base + PEXTP_ANA_LN0_TRX_REG +
+ lane * PEXTP_ANA_LANE_OFFSET;
+
+ mtk_phy_update_bits(addr + PEXTP_ANA_TX_OFFSET, EFUSE_LN_TX_PMOS_SEL,
+ EFUSE_LN_TX_PMOS_VAL(data->tx_pmos));
+
+ mtk_phy_update_bits(addr + PEXTP_ANA_TX_OFFSET, EFUSE_LN_TX_NMOS_SEL,
+ EFUSE_LN_TX_NMOS_VAL(data->tx_nmos));
+
+ mtk_phy_update_bits(addr + PEXTP_ANA_RX_OFFSET, EFUSE_LN_RX_SEL,
+ EFUSE_LN_RX_VAL(data->rx_data));
+}
+
+/**
+ * mtk_pcie_phy_init() - Initialize the phy
+ * @phy: the phy to be initialized
+ *
+ * Initialize the phy by setting the efuse data.
+ * The hardware settings will be reset during suspend, it should be
+ * reinitialized when the consumer calls phy_init() again on resume.
+ */
+static int mtk_pcie_phy_init(struct phy *phy)
+{
+ struct mtk_pcie_phy *pcie_phy = phy_get_drvdata(phy);
+ int i;
+
+ if (!pcie_phy->sw_efuse_en)
+ return 0;
+
+ /* Set global data */
+ mtk_phy_update_bits(pcie_phy->sif_base + PEXTP_ANA_GLB_00_REG,
+ EFUSE_GLB_INTR_SEL,
+ EFUSE_GLB_INTR_VAL(pcie_phy->efuse_glb_intr));
+
+ for (i = 0; i < pcie_phy->data->num_lanes; i++)
+ mtk_pcie_efuse_set_lane(pcie_phy, i);
+
+ return 0;
+}
+
+static const struct phy_ops mtk_pcie_phy_ops = {
+ .init = mtk_pcie_phy_init,
+ .owner = THIS_MODULE,
+};
+
+static int mtk_pcie_efuse_read_for_lane(struct mtk_pcie_phy *pcie_phy,
+ unsigned int lane)
+{
+ struct mtk_pcie_lane_efuse *efuse = &pcie_phy->efuse[lane];
+ struct device *dev = pcie_phy->dev;
+ char efuse_id[16];
+ int ret;
+
+ snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_pmos", lane);
+ ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse->tx_pmos);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to read %s\n", efuse_id);
+
+ snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_nmos", lane);
+ ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse->tx_nmos);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to read %s\n", efuse_id);
+
+ snprintf(efuse_id, sizeof(efuse_id), "rx_ln%d", lane);
+ ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse->rx_data);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to read %s\n", efuse_id);
+
+ if (!(efuse->tx_pmos || efuse->tx_nmos || efuse->rx_data))
+ return dev_err_probe(dev, -EINVAL,
+ "No eFuse data found for lane%d, but dts enable it\n",
+ lane);
+
+ efuse->lane_efuse_supported = true;
+
+ return 0;
+}
+
+static int mtk_pcie_read_efuse(struct mtk_pcie_phy *pcie_phy)
+{
+ struct device *dev = pcie_phy->dev;
+ bool nvmem_enabled;
+ int ret, i;
+
+ /* nvmem data is optional */
+ nvmem_enabled = device_property_read_bool(dev, "nvmem-cells");
+ if (!nvmem_enabled)
+ return 0;
+
+ ret = nvmem_cell_read_variable_le_u32(dev, "glb_intr",
+ &pcie_phy->efuse_glb_intr);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to read glb_intr\n");
+
+ pcie_phy->sw_efuse_en = true;
+
+ pcie_phy->efuse = devm_kzalloc(dev, pcie_phy->data->num_lanes *
+ sizeof(*pcie_phy->efuse), GFP_KERNEL);
+ if (!pcie_phy->efuse)
+ return -ENOMEM;
+
+ for (i = 0; i < pcie_phy->data->num_lanes; i++) {
+ ret = mtk_pcie_efuse_read_for_lane(pcie_phy, i);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int mtk_pcie_phy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct phy_provider *provider;
+ struct mtk_pcie_phy *pcie_phy;
+ int ret;
+
+ pcie_phy = devm_kzalloc(dev, sizeof(*pcie_phy), GFP_KERNEL);
+ if (!pcie_phy)
+ return -ENOMEM;
+
+ pcie_phy->sif_base = devm_platform_ioremap_resource_byname(pdev, "sif");
+ if (IS_ERR(pcie_phy->sif_base))
+ return dev_err_probe(dev, PTR_ERR(pcie_phy->sif_base),
+ "Failed to map phy-sif base\n");
+
+ pcie_phy->phy = devm_phy_create(dev, dev->of_node, &mtk_pcie_phy_ops);
+ if (IS_ERR(pcie_phy->phy))
+ return dev_err_probe(dev, PTR_ERR(pcie_phy->phy),
+ "Failed to create PCIe phy\n");
+
+ pcie_phy->dev = dev;
+ pcie_phy->data = of_device_get_match_data(dev);
+ if (!pcie_phy->data)
+ return dev_err_probe(dev, -EINVAL, "Failed to get phy data\n");
+
+ if (pcie_phy->data->sw_efuse_supported) {
+ /*
+ * Failed to read the efuse data is not a fatal problem,
+ * ignore the failure and keep going.
+ */
+ ret = mtk_pcie_read_efuse(pcie_phy);
+ if (ret == -EPROBE_DEFER)
+ return ret;
+ }
+
+ phy_set_drvdata(pcie_phy->phy, pcie_phy);
+
+ provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+ if (IS_ERR(provider))
+ return dev_err_probe(dev, PTR_ERR(provider),
+ "PCIe phy probe failed\n");
+
+ return 0;
+}
+
+static const struct mtk_pcie_phy_data mt8195_data = {
+ .num_lanes = 2,
+ .sw_efuse_supported = true,
+};
+
+static const struct of_device_id mtk_pcie_phy_of_match[] = {
+ { .compatible = "mediatek,mt8195-pcie-phy", .data = &mt8195_data },
+ { },
+};
+MODULE_DEVICE_TABLE(of, mtk_pcie_phy_of_match);
+
+static struct platform_driver mtk_pcie_phy_driver = {
+ .probe = mtk_pcie_phy_probe,
+ .driver = {
+ .name = "mtk-pcie-phy",
+ .of_match_table = mtk_pcie_phy_of_match,
+ },
+};
+module_platform_driver(mtk_pcie_phy_driver);
+
+MODULE_DESCRIPTION("MediaTek PCIe PHY driver");
+MODULE_AUTHOR("Jianjun Wang <jianjun.wang@mediatek.com>");
+MODULE_LICENSE("GPL v2");
--
2.18.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v5 2/2] phy: mediatek: Add PCIe PHY driver
@ 2022-03-26 2:27 ` Jianjun Wang
0 siblings, 0 replies; 32+ messages in thread
From: Jianjun Wang @ 2022-03-26 2:27 UTC (permalink / raw)
To: Chunfeng Yun, Kishon Vijay Abraham I, Vinod Koul, Rob Herring,
Matthias Brugger, Chen-Yu Tsai, AngeloGioacchino Del Regno,
Krzysztof Kozlowski
Cc: Wei-Shun Chang, Jianjun Wang, linux-arm-kernel, linux-mediatek,
linux-phy, devicetree, linux-kernel, rex-bc.chen, randy.wu,
jieyy.yang, chuanjia.liu, qizhong.cheng, jian.yang
Add PCIe GEN3 PHY driver support on MediaTek chipsets.
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/phy/mediatek/Kconfig | 11 ++
drivers/phy/mediatek/Makefile | 1 +
drivers/phy/mediatek/phy-mtk-pcie.c | 272 ++++++++++++++++++++++++++++
3 files changed, 284 insertions(+)
create mode 100644 drivers/phy/mediatek/phy-mtk-pcie.c
diff --git a/drivers/phy/mediatek/Kconfig b/drivers/phy/mediatek/Kconfig
index 55f8e6c048ab..387ed1b3f2cc 100644
--- a/drivers/phy/mediatek/Kconfig
+++ b/drivers/phy/mediatek/Kconfig
@@ -55,3 +55,14 @@ config PHY_MTK_MIPI_DSI
select GENERIC_PHY
help
Support MIPI DSI for Mediatek SoCs.
+
+config PHY_MTK_PCIE
+ tristate "MediaTek PCIe-PHY Driver"
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+ depends on OF
+ select GENERIC_PHY
+ help
+ Say 'Y' here to add support for MediaTek PCIe PHY driver.
+ This driver create the basic PHY instance and provides initialize
+ callback for PCIe GEN3 port, it supports software efuse
+ initialization.
diff --git a/drivers/phy/mediatek/Makefile b/drivers/phy/mediatek/Makefile
index ace660fbed3a..788c13147f63 100644
--- a/drivers/phy/mediatek/Makefile
+++ b/drivers/phy/mediatek/Makefile
@@ -6,6 +6,7 @@
obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
obj-$(CONFIG_PHY_MTK_UFS) += phy-mtk-ufs.o
obj-$(CONFIG_PHY_MTK_XSPHY) += phy-mtk-xsphy.o
+obj-$(CONFIG_PHY_MTK_PCIE) += phy-mtk-pcie.o
phy-mtk-hdmi-drv-y := phy-mtk-hdmi.o
phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt2701.o
diff --git a/drivers/phy/mediatek/phy-mtk-pcie.c b/drivers/phy/mediatek/phy-mtk-pcie.c
new file mode 100644
index 000000000000..d288655b6cff
--- /dev/null
+++ b/drivers/phy/mediatek/phy-mtk-pcie.c
@@ -0,0 +1,272 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ * Author: Jianjun Wang <jianjun.wang@mediatek.com>
+ */
+
+#include <linux/bits.h>
+#include <linux/compiler_types.h>
+#include <linux/module.h>
+#include <linux/nvmem-consumer.h>
+#include <linux/of_device.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include "phy-mtk-io.h"
+
+#define PEXTP_ANA_GLB_00_REG 0x9000
+#define PEXTP_ANA_LN0_TRX_REG 0xa000
+#define PEXTP_ANA_TX_OFFSET 0x04
+#define PEXTP_ANA_RX_OFFSET 0x3c
+#define PEXTP_ANA_LANE_OFFSET 0x100
+
+/* PEXTP_GLB_00_REG[28:24] Internal Resistor Selection of TX Bias Current */
+#define EFUSE_GLB_INTR_SEL GENMASK(28, 24)
+#define EFUSE_GLB_INTR_VAL(x) ((0x1f & (x)) << 24)
+
+/* PEXTP_ANA_LN_RX_REG[3:0] RX impedance selection */
+#define EFUSE_LN_RX_SEL GENMASK(3, 0)
+#define EFUSE_LN_RX_VAL(x) (0xf & (x))
+
+/* PEXTP_ANA_LN_TX_REG[5:2] TX PMOS impedance selection */
+#define EFUSE_LN_TX_PMOS_SEL GENMASK(5, 2)
+#define EFUSE_LN_TX_PMOS_VAL(x) ((0xf & (x)) << 2)
+
+/* PEXTP_ANA_LN_TX_REG[11:8] TX NMOS impedance selection */
+#define EFUSE_LN_TX_NMOS_SEL GENMASK(11, 8)
+#define EFUSE_LN_TX_NMOS_VAL(x) ((0xf & (x)) << 8)
+
+/**
+ * struct mtk_pcie_lane_efuse - eFuse data for each lane
+ * @tx_pmos: TX PMOS impedance selection data
+ * @tx_nmos: TX NMOS impedance selection data
+ * @rx_data: RX impedance selection data
+ * @lane_efuse_supported: software eFuse data is supported for this lane
+ */
+struct mtk_pcie_lane_efuse {
+ u32 tx_pmos;
+ u32 tx_nmos;
+ u32 rx_data;
+ bool lane_efuse_supported;
+};
+
+/**
+ * struct mtk_pcie_phy_data - phy data for each SoC
+ * @num_lanes: supported lane numbers
+ * @sw_efuse_supported: support software to load eFuse data
+ */
+struct mtk_pcie_phy_data {
+ int num_lanes;
+ bool sw_efuse_supported;
+};
+
+/**
+ * struct mtk_pcie_phy - PCIe phy driver main structure
+ * @dev: pointer to device
+ * @phy: pointer to generic phy
+ * @sif_base: IO mapped register base address of system interface
+ * @data: pointer to SoC dependent data
+ * @sw_efuse_en: software eFuse enable status
+ * @efuse_glb_intr: internal resistor selection of TX bias current data
+ * @efuse: pointer to eFuse data for each lane
+ */
+struct mtk_pcie_phy {
+ struct device *dev;
+ struct phy *phy;
+ void __iomem *sif_base;
+ const struct mtk_pcie_phy_data *data;
+
+ bool sw_efuse_en;
+ u32 efuse_glb_intr;
+ struct mtk_pcie_lane_efuse *efuse;
+};
+
+static void mtk_pcie_efuse_set_lane(struct mtk_pcie_phy *pcie_phy,
+ unsigned int lane)
+{
+ struct mtk_pcie_lane_efuse *data = &pcie_phy->efuse[lane];
+ void __iomem *addr;
+
+ if (!data->lane_efuse_supported)
+ return;
+
+ addr = pcie_phy->sif_base + PEXTP_ANA_LN0_TRX_REG +
+ lane * PEXTP_ANA_LANE_OFFSET;
+
+ mtk_phy_update_bits(addr + PEXTP_ANA_TX_OFFSET, EFUSE_LN_TX_PMOS_SEL,
+ EFUSE_LN_TX_PMOS_VAL(data->tx_pmos));
+
+ mtk_phy_update_bits(addr + PEXTP_ANA_TX_OFFSET, EFUSE_LN_TX_NMOS_SEL,
+ EFUSE_LN_TX_NMOS_VAL(data->tx_nmos));
+
+ mtk_phy_update_bits(addr + PEXTP_ANA_RX_OFFSET, EFUSE_LN_RX_SEL,
+ EFUSE_LN_RX_VAL(data->rx_data));
+}
+
+/**
+ * mtk_pcie_phy_init() - Initialize the phy
+ * @phy: the phy to be initialized
+ *
+ * Initialize the phy by setting the efuse data.
+ * The hardware settings will be reset during suspend, it should be
+ * reinitialized when the consumer calls phy_init() again on resume.
+ */
+static int mtk_pcie_phy_init(struct phy *phy)
+{
+ struct mtk_pcie_phy *pcie_phy = phy_get_drvdata(phy);
+ int i;
+
+ if (!pcie_phy->sw_efuse_en)
+ return 0;
+
+ /* Set global data */
+ mtk_phy_update_bits(pcie_phy->sif_base + PEXTP_ANA_GLB_00_REG,
+ EFUSE_GLB_INTR_SEL,
+ EFUSE_GLB_INTR_VAL(pcie_phy->efuse_glb_intr));
+
+ for (i = 0; i < pcie_phy->data->num_lanes; i++)
+ mtk_pcie_efuse_set_lane(pcie_phy, i);
+
+ return 0;
+}
+
+static const struct phy_ops mtk_pcie_phy_ops = {
+ .init = mtk_pcie_phy_init,
+ .owner = THIS_MODULE,
+};
+
+static int mtk_pcie_efuse_read_for_lane(struct mtk_pcie_phy *pcie_phy,
+ unsigned int lane)
+{
+ struct mtk_pcie_lane_efuse *efuse = &pcie_phy->efuse[lane];
+ struct device *dev = pcie_phy->dev;
+ char efuse_id[16];
+ int ret;
+
+ snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_pmos", lane);
+ ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse->tx_pmos);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to read %s\n", efuse_id);
+
+ snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_nmos", lane);
+ ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse->tx_nmos);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to read %s\n", efuse_id);
+
+ snprintf(efuse_id, sizeof(efuse_id), "rx_ln%d", lane);
+ ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse->rx_data);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to read %s\n", efuse_id);
+
+ if (!(efuse->tx_pmos || efuse->tx_nmos || efuse->rx_data))
+ return dev_err_probe(dev, -EINVAL,
+ "No eFuse data found for lane%d, but dts enable it\n",
+ lane);
+
+ efuse->lane_efuse_supported = true;
+
+ return 0;
+}
+
+static int mtk_pcie_read_efuse(struct mtk_pcie_phy *pcie_phy)
+{
+ struct device *dev = pcie_phy->dev;
+ bool nvmem_enabled;
+ int ret, i;
+
+ /* nvmem data is optional */
+ nvmem_enabled = device_property_read_bool(dev, "nvmem-cells");
+ if (!nvmem_enabled)
+ return 0;
+
+ ret = nvmem_cell_read_variable_le_u32(dev, "glb_intr",
+ &pcie_phy->efuse_glb_intr);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to read glb_intr\n");
+
+ pcie_phy->sw_efuse_en = true;
+
+ pcie_phy->efuse = devm_kzalloc(dev, pcie_phy->data->num_lanes *
+ sizeof(*pcie_phy->efuse), GFP_KERNEL);
+ if (!pcie_phy->efuse)
+ return -ENOMEM;
+
+ for (i = 0; i < pcie_phy->data->num_lanes; i++) {
+ ret = mtk_pcie_efuse_read_for_lane(pcie_phy, i);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int mtk_pcie_phy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct phy_provider *provider;
+ struct mtk_pcie_phy *pcie_phy;
+ int ret;
+
+ pcie_phy = devm_kzalloc(dev, sizeof(*pcie_phy), GFP_KERNEL);
+ if (!pcie_phy)
+ return -ENOMEM;
+
+ pcie_phy->sif_base = devm_platform_ioremap_resource_byname(pdev, "sif");
+ if (IS_ERR(pcie_phy->sif_base))
+ return dev_err_probe(dev, PTR_ERR(pcie_phy->sif_base),
+ "Failed to map phy-sif base\n");
+
+ pcie_phy->phy = devm_phy_create(dev, dev->of_node, &mtk_pcie_phy_ops);
+ if (IS_ERR(pcie_phy->phy))
+ return dev_err_probe(dev, PTR_ERR(pcie_phy->phy),
+ "Failed to create PCIe phy\n");
+
+ pcie_phy->dev = dev;
+ pcie_phy->data = of_device_get_match_data(dev);
+ if (!pcie_phy->data)
+ return dev_err_probe(dev, -EINVAL, "Failed to get phy data\n");
+
+ if (pcie_phy->data->sw_efuse_supported) {
+ /*
+ * Failed to read the efuse data is not a fatal problem,
+ * ignore the failure and keep going.
+ */
+ ret = mtk_pcie_read_efuse(pcie_phy);
+ if (ret == -EPROBE_DEFER)
+ return ret;
+ }
+
+ phy_set_drvdata(pcie_phy->phy, pcie_phy);
+
+ provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+ if (IS_ERR(provider))
+ return dev_err_probe(dev, PTR_ERR(provider),
+ "PCIe phy probe failed\n");
+
+ return 0;
+}
+
+static const struct mtk_pcie_phy_data mt8195_data = {
+ .num_lanes = 2,
+ .sw_efuse_supported = true,
+};
+
+static const struct of_device_id mtk_pcie_phy_of_match[] = {
+ { .compatible = "mediatek,mt8195-pcie-phy", .data = &mt8195_data },
+ { },
+};
+MODULE_DEVICE_TABLE(of, mtk_pcie_phy_of_match);
+
+static struct platform_driver mtk_pcie_phy_driver = {
+ .probe = mtk_pcie_phy_probe,
+ .driver = {
+ .name = "mtk-pcie-phy",
+ .of_match_table = mtk_pcie_phy_of_match,
+ },
+};
+module_platform_driver(mtk_pcie_phy_driver);
+
+MODULE_DESCRIPTION("MediaTek PCIe PHY driver");
+MODULE_AUTHOR("Jianjun Wang <jianjun.wang@mediatek.com>");
+MODULE_LICENSE("GPL v2");
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v5 2/2] phy: mediatek: Add PCIe PHY driver
@ 2022-03-26 2:27 ` Jianjun Wang
0 siblings, 0 replies; 32+ messages in thread
From: Jianjun Wang @ 2022-03-26 2:27 UTC (permalink / raw)
To: Chunfeng Yun, Kishon Vijay Abraham I, Vinod Koul, Rob Herring,
Matthias Brugger, Chen-Yu Tsai, AngeloGioacchino Del Regno,
Krzysztof Kozlowski
Cc: Wei-Shun Chang, Jianjun Wang, linux-arm-kernel, linux-mediatek,
linux-phy, devicetree, linux-kernel, rex-bc.chen, randy.wu,
jieyy.yang, chuanjia.liu, qizhong.cheng, jian.yang
Add PCIe GEN3 PHY driver support on MediaTek chipsets.
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/phy/mediatek/Kconfig | 11 ++
drivers/phy/mediatek/Makefile | 1 +
drivers/phy/mediatek/phy-mtk-pcie.c | 272 ++++++++++++++++++++++++++++
3 files changed, 284 insertions(+)
create mode 100644 drivers/phy/mediatek/phy-mtk-pcie.c
diff --git a/drivers/phy/mediatek/Kconfig b/drivers/phy/mediatek/Kconfig
index 55f8e6c048ab..387ed1b3f2cc 100644
--- a/drivers/phy/mediatek/Kconfig
+++ b/drivers/phy/mediatek/Kconfig
@@ -55,3 +55,14 @@ config PHY_MTK_MIPI_DSI
select GENERIC_PHY
help
Support MIPI DSI for Mediatek SoCs.
+
+config PHY_MTK_PCIE
+ tristate "MediaTek PCIe-PHY Driver"
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+ depends on OF
+ select GENERIC_PHY
+ help
+ Say 'Y' here to add support for MediaTek PCIe PHY driver.
+ This driver create the basic PHY instance and provides initialize
+ callback for PCIe GEN3 port, it supports software efuse
+ initialization.
diff --git a/drivers/phy/mediatek/Makefile b/drivers/phy/mediatek/Makefile
index ace660fbed3a..788c13147f63 100644
--- a/drivers/phy/mediatek/Makefile
+++ b/drivers/phy/mediatek/Makefile
@@ -6,6 +6,7 @@
obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
obj-$(CONFIG_PHY_MTK_UFS) += phy-mtk-ufs.o
obj-$(CONFIG_PHY_MTK_XSPHY) += phy-mtk-xsphy.o
+obj-$(CONFIG_PHY_MTK_PCIE) += phy-mtk-pcie.o
phy-mtk-hdmi-drv-y := phy-mtk-hdmi.o
phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt2701.o
diff --git a/drivers/phy/mediatek/phy-mtk-pcie.c b/drivers/phy/mediatek/phy-mtk-pcie.c
new file mode 100644
index 000000000000..d288655b6cff
--- /dev/null
+++ b/drivers/phy/mediatek/phy-mtk-pcie.c
@@ -0,0 +1,272 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ * Author: Jianjun Wang <jianjun.wang@mediatek.com>
+ */
+
+#include <linux/bits.h>
+#include <linux/compiler_types.h>
+#include <linux/module.h>
+#include <linux/nvmem-consumer.h>
+#include <linux/of_device.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include "phy-mtk-io.h"
+
+#define PEXTP_ANA_GLB_00_REG 0x9000
+#define PEXTP_ANA_LN0_TRX_REG 0xa000
+#define PEXTP_ANA_TX_OFFSET 0x04
+#define PEXTP_ANA_RX_OFFSET 0x3c
+#define PEXTP_ANA_LANE_OFFSET 0x100
+
+/* PEXTP_GLB_00_REG[28:24] Internal Resistor Selection of TX Bias Current */
+#define EFUSE_GLB_INTR_SEL GENMASK(28, 24)
+#define EFUSE_GLB_INTR_VAL(x) ((0x1f & (x)) << 24)
+
+/* PEXTP_ANA_LN_RX_REG[3:0] RX impedance selection */
+#define EFUSE_LN_RX_SEL GENMASK(3, 0)
+#define EFUSE_LN_RX_VAL(x) (0xf & (x))
+
+/* PEXTP_ANA_LN_TX_REG[5:2] TX PMOS impedance selection */
+#define EFUSE_LN_TX_PMOS_SEL GENMASK(5, 2)
+#define EFUSE_LN_TX_PMOS_VAL(x) ((0xf & (x)) << 2)
+
+/* PEXTP_ANA_LN_TX_REG[11:8] TX NMOS impedance selection */
+#define EFUSE_LN_TX_NMOS_SEL GENMASK(11, 8)
+#define EFUSE_LN_TX_NMOS_VAL(x) ((0xf & (x)) << 8)
+
+/**
+ * struct mtk_pcie_lane_efuse - eFuse data for each lane
+ * @tx_pmos: TX PMOS impedance selection data
+ * @tx_nmos: TX NMOS impedance selection data
+ * @rx_data: RX impedance selection data
+ * @lane_efuse_supported: software eFuse data is supported for this lane
+ */
+struct mtk_pcie_lane_efuse {
+ u32 tx_pmos;
+ u32 tx_nmos;
+ u32 rx_data;
+ bool lane_efuse_supported;
+};
+
+/**
+ * struct mtk_pcie_phy_data - phy data for each SoC
+ * @num_lanes: supported lane numbers
+ * @sw_efuse_supported: support software to load eFuse data
+ */
+struct mtk_pcie_phy_data {
+ int num_lanes;
+ bool sw_efuse_supported;
+};
+
+/**
+ * struct mtk_pcie_phy - PCIe phy driver main structure
+ * @dev: pointer to device
+ * @phy: pointer to generic phy
+ * @sif_base: IO mapped register base address of system interface
+ * @data: pointer to SoC dependent data
+ * @sw_efuse_en: software eFuse enable status
+ * @efuse_glb_intr: internal resistor selection of TX bias current data
+ * @efuse: pointer to eFuse data for each lane
+ */
+struct mtk_pcie_phy {
+ struct device *dev;
+ struct phy *phy;
+ void __iomem *sif_base;
+ const struct mtk_pcie_phy_data *data;
+
+ bool sw_efuse_en;
+ u32 efuse_glb_intr;
+ struct mtk_pcie_lane_efuse *efuse;
+};
+
+static void mtk_pcie_efuse_set_lane(struct mtk_pcie_phy *pcie_phy,
+ unsigned int lane)
+{
+ struct mtk_pcie_lane_efuse *data = &pcie_phy->efuse[lane];
+ void __iomem *addr;
+
+ if (!data->lane_efuse_supported)
+ return;
+
+ addr = pcie_phy->sif_base + PEXTP_ANA_LN0_TRX_REG +
+ lane * PEXTP_ANA_LANE_OFFSET;
+
+ mtk_phy_update_bits(addr + PEXTP_ANA_TX_OFFSET, EFUSE_LN_TX_PMOS_SEL,
+ EFUSE_LN_TX_PMOS_VAL(data->tx_pmos));
+
+ mtk_phy_update_bits(addr + PEXTP_ANA_TX_OFFSET, EFUSE_LN_TX_NMOS_SEL,
+ EFUSE_LN_TX_NMOS_VAL(data->tx_nmos));
+
+ mtk_phy_update_bits(addr + PEXTP_ANA_RX_OFFSET, EFUSE_LN_RX_SEL,
+ EFUSE_LN_RX_VAL(data->rx_data));
+}
+
+/**
+ * mtk_pcie_phy_init() - Initialize the phy
+ * @phy: the phy to be initialized
+ *
+ * Initialize the phy by setting the efuse data.
+ * The hardware settings will be reset during suspend, it should be
+ * reinitialized when the consumer calls phy_init() again on resume.
+ */
+static int mtk_pcie_phy_init(struct phy *phy)
+{
+ struct mtk_pcie_phy *pcie_phy = phy_get_drvdata(phy);
+ int i;
+
+ if (!pcie_phy->sw_efuse_en)
+ return 0;
+
+ /* Set global data */
+ mtk_phy_update_bits(pcie_phy->sif_base + PEXTP_ANA_GLB_00_REG,
+ EFUSE_GLB_INTR_SEL,
+ EFUSE_GLB_INTR_VAL(pcie_phy->efuse_glb_intr));
+
+ for (i = 0; i < pcie_phy->data->num_lanes; i++)
+ mtk_pcie_efuse_set_lane(pcie_phy, i);
+
+ return 0;
+}
+
+static const struct phy_ops mtk_pcie_phy_ops = {
+ .init = mtk_pcie_phy_init,
+ .owner = THIS_MODULE,
+};
+
+static int mtk_pcie_efuse_read_for_lane(struct mtk_pcie_phy *pcie_phy,
+ unsigned int lane)
+{
+ struct mtk_pcie_lane_efuse *efuse = &pcie_phy->efuse[lane];
+ struct device *dev = pcie_phy->dev;
+ char efuse_id[16];
+ int ret;
+
+ snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_pmos", lane);
+ ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse->tx_pmos);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to read %s\n", efuse_id);
+
+ snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_nmos", lane);
+ ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse->tx_nmos);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to read %s\n", efuse_id);
+
+ snprintf(efuse_id, sizeof(efuse_id), "rx_ln%d", lane);
+ ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse->rx_data);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to read %s\n", efuse_id);
+
+ if (!(efuse->tx_pmos || efuse->tx_nmos || efuse->rx_data))
+ return dev_err_probe(dev, -EINVAL,
+ "No eFuse data found for lane%d, but dts enable it\n",
+ lane);
+
+ efuse->lane_efuse_supported = true;
+
+ return 0;
+}
+
+static int mtk_pcie_read_efuse(struct mtk_pcie_phy *pcie_phy)
+{
+ struct device *dev = pcie_phy->dev;
+ bool nvmem_enabled;
+ int ret, i;
+
+ /* nvmem data is optional */
+ nvmem_enabled = device_property_read_bool(dev, "nvmem-cells");
+ if (!nvmem_enabled)
+ return 0;
+
+ ret = nvmem_cell_read_variable_le_u32(dev, "glb_intr",
+ &pcie_phy->efuse_glb_intr);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to read glb_intr\n");
+
+ pcie_phy->sw_efuse_en = true;
+
+ pcie_phy->efuse = devm_kzalloc(dev, pcie_phy->data->num_lanes *
+ sizeof(*pcie_phy->efuse), GFP_KERNEL);
+ if (!pcie_phy->efuse)
+ return -ENOMEM;
+
+ for (i = 0; i < pcie_phy->data->num_lanes; i++) {
+ ret = mtk_pcie_efuse_read_for_lane(pcie_phy, i);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int mtk_pcie_phy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct phy_provider *provider;
+ struct mtk_pcie_phy *pcie_phy;
+ int ret;
+
+ pcie_phy = devm_kzalloc(dev, sizeof(*pcie_phy), GFP_KERNEL);
+ if (!pcie_phy)
+ return -ENOMEM;
+
+ pcie_phy->sif_base = devm_platform_ioremap_resource_byname(pdev, "sif");
+ if (IS_ERR(pcie_phy->sif_base))
+ return dev_err_probe(dev, PTR_ERR(pcie_phy->sif_base),
+ "Failed to map phy-sif base\n");
+
+ pcie_phy->phy = devm_phy_create(dev, dev->of_node, &mtk_pcie_phy_ops);
+ if (IS_ERR(pcie_phy->phy))
+ return dev_err_probe(dev, PTR_ERR(pcie_phy->phy),
+ "Failed to create PCIe phy\n");
+
+ pcie_phy->dev = dev;
+ pcie_phy->data = of_device_get_match_data(dev);
+ if (!pcie_phy->data)
+ return dev_err_probe(dev, -EINVAL, "Failed to get phy data\n");
+
+ if (pcie_phy->data->sw_efuse_supported) {
+ /*
+ * Failed to read the efuse data is not a fatal problem,
+ * ignore the failure and keep going.
+ */
+ ret = mtk_pcie_read_efuse(pcie_phy);
+ if (ret == -EPROBE_DEFER)
+ return ret;
+ }
+
+ phy_set_drvdata(pcie_phy->phy, pcie_phy);
+
+ provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+ if (IS_ERR(provider))
+ return dev_err_probe(dev, PTR_ERR(provider),
+ "PCIe phy probe failed\n");
+
+ return 0;
+}
+
+static const struct mtk_pcie_phy_data mt8195_data = {
+ .num_lanes = 2,
+ .sw_efuse_supported = true,
+};
+
+static const struct of_device_id mtk_pcie_phy_of_match[] = {
+ { .compatible = "mediatek,mt8195-pcie-phy", .data = &mt8195_data },
+ { },
+};
+MODULE_DEVICE_TABLE(of, mtk_pcie_phy_of_match);
+
+static struct platform_driver mtk_pcie_phy_driver = {
+ .probe = mtk_pcie_phy_probe,
+ .driver = {
+ .name = "mtk-pcie-phy",
+ .of_match_table = mtk_pcie_phy_of_match,
+ },
+};
+module_platform_driver(mtk_pcie_phy_driver);
+
+MODULE_DESCRIPTION("MediaTek PCIe PHY driver");
+MODULE_AUTHOR("Jianjun Wang <jianjun.wang@mediatek.com>");
+MODULE_LICENSE("GPL v2");
--
2.18.0
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v5 2/2] phy: mediatek: Add PCIe PHY driver
@ 2022-03-26 2:27 ` Jianjun Wang
0 siblings, 0 replies; 32+ messages in thread
From: Jianjun Wang @ 2022-03-26 2:27 UTC (permalink / raw)
To: Chunfeng Yun, Kishon Vijay Abraham I, Vinod Koul, Rob Herring,
Matthias Brugger, Chen-Yu Tsai, AngeloGioacchino Del Regno,
Krzysztof Kozlowski
Cc: Wei-Shun Chang, Jianjun Wang, linux-arm-kernel, linux-mediatek,
linux-phy, devicetree, linux-kernel, rex-bc.chen, randy.wu,
jieyy.yang, chuanjia.liu, qizhong.cheng, jian.yang
Add PCIe GEN3 PHY driver support on MediaTek chipsets.
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/phy/mediatek/Kconfig | 11 ++
drivers/phy/mediatek/Makefile | 1 +
drivers/phy/mediatek/phy-mtk-pcie.c | 272 ++++++++++++++++++++++++++++
3 files changed, 284 insertions(+)
create mode 100644 drivers/phy/mediatek/phy-mtk-pcie.c
diff --git a/drivers/phy/mediatek/Kconfig b/drivers/phy/mediatek/Kconfig
index 55f8e6c048ab..387ed1b3f2cc 100644
--- a/drivers/phy/mediatek/Kconfig
+++ b/drivers/phy/mediatek/Kconfig
@@ -55,3 +55,14 @@ config PHY_MTK_MIPI_DSI
select GENERIC_PHY
help
Support MIPI DSI for Mediatek SoCs.
+
+config PHY_MTK_PCIE
+ tristate "MediaTek PCIe-PHY Driver"
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+ depends on OF
+ select GENERIC_PHY
+ help
+ Say 'Y' here to add support for MediaTek PCIe PHY driver.
+ This driver create the basic PHY instance and provides initialize
+ callback for PCIe GEN3 port, it supports software efuse
+ initialization.
diff --git a/drivers/phy/mediatek/Makefile b/drivers/phy/mediatek/Makefile
index ace660fbed3a..788c13147f63 100644
--- a/drivers/phy/mediatek/Makefile
+++ b/drivers/phy/mediatek/Makefile
@@ -6,6 +6,7 @@
obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
obj-$(CONFIG_PHY_MTK_UFS) += phy-mtk-ufs.o
obj-$(CONFIG_PHY_MTK_XSPHY) += phy-mtk-xsphy.o
+obj-$(CONFIG_PHY_MTK_PCIE) += phy-mtk-pcie.o
phy-mtk-hdmi-drv-y := phy-mtk-hdmi.o
phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt2701.o
diff --git a/drivers/phy/mediatek/phy-mtk-pcie.c b/drivers/phy/mediatek/phy-mtk-pcie.c
new file mode 100644
index 000000000000..d288655b6cff
--- /dev/null
+++ b/drivers/phy/mediatek/phy-mtk-pcie.c
@@ -0,0 +1,272 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ * Author: Jianjun Wang <jianjun.wang@mediatek.com>
+ */
+
+#include <linux/bits.h>
+#include <linux/compiler_types.h>
+#include <linux/module.h>
+#include <linux/nvmem-consumer.h>
+#include <linux/of_device.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include "phy-mtk-io.h"
+
+#define PEXTP_ANA_GLB_00_REG 0x9000
+#define PEXTP_ANA_LN0_TRX_REG 0xa000
+#define PEXTP_ANA_TX_OFFSET 0x04
+#define PEXTP_ANA_RX_OFFSET 0x3c
+#define PEXTP_ANA_LANE_OFFSET 0x100
+
+/* PEXTP_GLB_00_REG[28:24] Internal Resistor Selection of TX Bias Current */
+#define EFUSE_GLB_INTR_SEL GENMASK(28, 24)
+#define EFUSE_GLB_INTR_VAL(x) ((0x1f & (x)) << 24)
+
+/* PEXTP_ANA_LN_RX_REG[3:0] RX impedance selection */
+#define EFUSE_LN_RX_SEL GENMASK(3, 0)
+#define EFUSE_LN_RX_VAL(x) (0xf & (x))
+
+/* PEXTP_ANA_LN_TX_REG[5:2] TX PMOS impedance selection */
+#define EFUSE_LN_TX_PMOS_SEL GENMASK(5, 2)
+#define EFUSE_LN_TX_PMOS_VAL(x) ((0xf & (x)) << 2)
+
+/* PEXTP_ANA_LN_TX_REG[11:8] TX NMOS impedance selection */
+#define EFUSE_LN_TX_NMOS_SEL GENMASK(11, 8)
+#define EFUSE_LN_TX_NMOS_VAL(x) ((0xf & (x)) << 8)
+
+/**
+ * struct mtk_pcie_lane_efuse - eFuse data for each lane
+ * @tx_pmos: TX PMOS impedance selection data
+ * @tx_nmos: TX NMOS impedance selection data
+ * @rx_data: RX impedance selection data
+ * @lane_efuse_supported: software eFuse data is supported for this lane
+ */
+struct mtk_pcie_lane_efuse {
+ u32 tx_pmos;
+ u32 tx_nmos;
+ u32 rx_data;
+ bool lane_efuse_supported;
+};
+
+/**
+ * struct mtk_pcie_phy_data - phy data for each SoC
+ * @num_lanes: supported lane numbers
+ * @sw_efuse_supported: support software to load eFuse data
+ */
+struct mtk_pcie_phy_data {
+ int num_lanes;
+ bool sw_efuse_supported;
+};
+
+/**
+ * struct mtk_pcie_phy - PCIe phy driver main structure
+ * @dev: pointer to device
+ * @phy: pointer to generic phy
+ * @sif_base: IO mapped register base address of system interface
+ * @data: pointer to SoC dependent data
+ * @sw_efuse_en: software eFuse enable status
+ * @efuse_glb_intr: internal resistor selection of TX bias current data
+ * @efuse: pointer to eFuse data for each lane
+ */
+struct mtk_pcie_phy {
+ struct device *dev;
+ struct phy *phy;
+ void __iomem *sif_base;
+ const struct mtk_pcie_phy_data *data;
+
+ bool sw_efuse_en;
+ u32 efuse_glb_intr;
+ struct mtk_pcie_lane_efuse *efuse;
+};
+
+static void mtk_pcie_efuse_set_lane(struct mtk_pcie_phy *pcie_phy,
+ unsigned int lane)
+{
+ struct mtk_pcie_lane_efuse *data = &pcie_phy->efuse[lane];
+ void __iomem *addr;
+
+ if (!data->lane_efuse_supported)
+ return;
+
+ addr = pcie_phy->sif_base + PEXTP_ANA_LN0_TRX_REG +
+ lane * PEXTP_ANA_LANE_OFFSET;
+
+ mtk_phy_update_bits(addr + PEXTP_ANA_TX_OFFSET, EFUSE_LN_TX_PMOS_SEL,
+ EFUSE_LN_TX_PMOS_VAL(data->tx_pmos));
+
+ mtk_phy_update_bits(addr + PEXTP_ANA_TX_OFFSET, EFUSE_LN_TX_NMOS_SEL,
+ EFUSE_LN_TX_NMOS_VAL(data->tx_nmos));
+
+ mtk_phy_update_bits(addr + PEXTP_ANA_RX_OFFSET, EFUSE_LN_RX_SEL,
+ EFUSE_LN_RX_VAL(data->rx_data));
+}
+
+/**
+ * mtk_pcie_phy_init() - Initialize the phy
+ * @phy: the phy to be initialized
+ *
+ * Initialize the phy by setting the efuse data.
+ * The hardware settings will be reset during suspend, it should be
+ * reinitialized when the consumer calls phy_init() again on resume.
+ */
+static int mtk_pcie_phy_init(struct phy *phy)
+{
+ struct mtk_pcie_phy *pcie_phy = phy_get_drvdata(phy);
+ int i;
+
+ if (!pcie_phy->sw_efuse_en)
+ return 0;
+
+ /* Set global data */
+ mtk_phy_update_bits(pcie_phy->sif_base + PEXTP_ANA_GLB_00_REG,
+ EFUSE_GLB_INTR_SEL,
+ EFUSE_GLB_INTR_VAL(pcie_phy->efuse_glb_intr));
+
+ for (i = 0; i < pcie_phy->data->num_lanes; i++)
+ mtk_pcie_efuse_set_lane(pcie_phy, i);
+
+ return 0;
+}
+
+static const struct phy_ops mtk_pcie_phy_ops = {
+ .init = mtk_pcie_phy_init,
+ .owner = THIS_MODULE,
+};
+
+static int mtk_pcie_efuse_read_for_lane(struct mtk_pcie_phy *pcie_phy,
+ unsigned int lane)
+{
+ struct mtk_pcie_lane_efuse *efuse = &pcie_phy->efuse[lane];
+ struct device *dev = pcie_phy->dev;
+ char efuse_id[16];
+ int ret;
+
+ snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_pmos", lane);
+ ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse->tx_pmos);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to read %s\n", efuse_id);
+
+ snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_nmos", lane);
+ ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse->tx_nmos);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to read %s\n", efuse_id);
+
+ snprintf(efuse_id, sizeof(efuse_id), "rx_ln%d", lane);
+ ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse->rx_data);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to read %s\n", efuse_id);
+
+ if (!(efuse->tx_pmos || efuse->tx_nmos || efuse->rx_data))
+ return dev_err_probe(dev, -EINVAL,
+ "No eFuse data found for lane%d, but dts enable it\n",
+ lane);
+
+ efuse->lane_efuse_supported = true;
+
+ return 0;
+}
+
+static int mtk_pcie_read_efuse(struct mtk_pcie_phy *pcie_phy)
+{
+ struct device *dev = pcie_phy->dev;
+ bool nvmem_enabled;
+ int ret, i;
+
+ /* nvmem data is optional */
+ nvmem_enabled = device_property_read_bool(dev, "nvmem-cells");
+ if (!nvmem_enabled)
+ return 0;
+
+ ret = nvmem_cell_read_variable_le_u32(dev, "glb_intr",
+ &pcie_phy->efuse_glb_intr);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to read glb_intr\n");
+
+ pcie_phy->sw_efuse_en = true;
+
+ pcie_phy->efuse = devm_kzalloc(dev, pcie_phy->data->num_lanes *
+ sizeof(*pcie_phy->efuse), GFP_KERNEL);
+ if (!pcie_phy->efuse)
+ return -ENOMEM;
+
+ for (i = 0; i < pcie_phy->data->num_lanes; i++) {
+ ret = mtk_pcie_efuse_read_for_lane(pcie_phy, i);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int mtk_pcie_phy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct phy_provider *provider;
+ struct mtk_pcie_phy *pcie_phy;
+ int ret;
+
+ pcie_phy = devm_kzalloc(dev, sizeof(*pcie_phy), GFP_KERNEL);
+ if (!pcie_phy)
+ return -ENOMEM;
+
+ pcie_phy->sif_base = devm_platform_ioremap_resource_byname(pdev, "sif");
+ if (IS_ERR(pcie_phy->sif_base))
+ return dev_err_probe(dev, PTR_ERR(pcie_phy->sif_base),
+ "Failed to map phy-sif base\n");
+
+ pcie_phy->phy = devm_phy_create(dev, dev->of_node, &mtk_pcie_phy_ops);
+ if (IS_ERR(pcie_phy->phy))
+ return dev_err_probe(dev, PTR_ERR(pcie_phy->phy),
+ "Failed to create PCIe phy\n");
+
+ pcie_phy->dev = dev;
+ pcie_phy->data = of_device_get_match_data(dev);
+ if (!pcie_phy->data)
+ return dev_err_probe(dev, -EINVAL, "Failed to get phy data\n");
+
+ if (pcie_phy->data->sw_efuse_supported) {
+ /*
+ * Failed to read the efuse data is not a fatal problem,
+ * ignore the failure and keep going.
+ */
+ ret = mtk_pcie_read_efuse(pcie_phy);
+ if (ret == -EPROBE_DEFER)
+ return ret;
+ }
+
+ phy_set_drvdata(pcie_phy->phy, pcie_phy);
+
+ provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+ if (IS_ERR(provider))
+ return dev_err_probe(dev, PTR_ERR(provider),
+ "PCIe phy probe failed\n");
+
+ return 0;
+}
+
+static const struct mtk_pcie_phy_data mt8195_data = {
+ .num_lanes = 2,
+ .sw_efuse_supported = true,
+};
+
+static const struct of_device_id mtk_pcie_phy_of_match[] = {
+ { .compatible = "mediatek,mt8195-pcie-phy", .data = &mt8195_data },
+ { },
+};
+MODULE_DEVICE_TABLE(of, mtk_pcie_phy_of_match);
+
+static struct platform_driver mtk_pcie_phy_driver = {
+ .probe = mtk_pcie_phy_probe,
+ .driver = {
+ .name = "mtk-pcie-phy",
+ .of_match_table = mtk_pcie_phy_of_match,
+ },
+};
+module_platform_driver(mtk_pcie_phy_driver);
+
+MODULE_DESCRIPTION("MediaTek PCIe PHY driver");
+MODULE_AUTHOR("Jianjun Wang <jianjun.wang@mediatek.com>");
+MODULE_LICENSE("GPL v2");
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [PATCH v5 0/2] phy: mediatek: Add PCIe PHY driver
2022-03-26 2:27 ` Jianjun Wang
(?)
(?)
@ 2022-04-06 5:47 ` Jianjun Wang
-1 siblings, 0 replies; 32+ messages in thread
From: Jianjun Wang @ 2022-04-06 5:47 UTC (permalink / raw)
To: Chunfeng Yun, Kishon Vijay Abraham I, Vinod Koul, Rob Herring,
Matthias Brugger, Chen-Yu Tsai, AngeloGioacchino Del Regno,
Krzysztof Kozlowski
Cc: Wei-Shun Chang, linux-arm-kernel, linux-mediatek, linux-phy,
devicetree, linux-kernel, rex-bc.chen, randy.wu, jieyy.yang,
chuanjia.liu, qizhong.cheng, jian.yang
Hello Maintainers,
Is there anything I can do to get these patches merged?
Thanks.
On Sat, 2022-03-26 at 10:27 +0800, Jianjun Wang wrote:
> These series patches add support for PCIe PHY driver on MediaTek
> chipsets.
>
> Changes in v5:
> 1. Fix typo in kerneldoc: "eFues" => "eFuse".
>
> Changes in v4:
> 1. Fix no return when calling dev_err_probe.
>
> Changes in v3:
> 1. Add introductions for structure members;
> 2. Add SoC dependent data;
> 3. Dynamically allocate efuse data;
> 4. Check return value if it's an -EPROBE_DEFER.
>
> Changes in v2:
> 1. Add specific compatible name;
> 2. Read NVMEM data at probe time;
> 3. Fix typos.
>
> Jianjun Wang (2):
> dt-bindings: phy: mediatek: Add YAML schema for PCIe PHY
> phy: mediatek: Add PCIe PHY driver
>
> .../bindings/phy/mediatek,pcie-phy.yaml | 75 +++++
> drivers/phy/mediatek/Kconfig | 11 +
> drivers/phy/mediatek/Makefile | 1 +
> drivers/phy/mediatek/phy-mtk-pcie.c | 272
> ++++++++++++++++++
> 4 files changed, 359 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml
> create mode 100644 drivers/phy/mediatek/phy-mtk-pcie.c
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v5 0/2] phy: mediatek: Add PCIe PHY driver
@ 2022-04-06 5:47 ` Jianjun Wang
0 siblings, 0 replies; 32+ messages in thread
From: Jianjun Wang @ 2022-04-06 5:47 UTC (permalink / raw)
To: Chunfeng Yun, Kishon Vijay Abraham I, Vinod Koul, Rob Herring,
Matthias Brugger, Chen-Yu Tsai, AngeloGioacchino Del Regno,
Krzysztof Kozlowski
Cc: Wei-Shun Chang, linux-arm-kernel, linux-mediatek, linux-phy,
devicetree, linux-kernel, rex-bc.chen, randy.wu, jieyy.yang,
chuanjia.liu, qizhong.cheng, jian.yang
Hello Maintainers,
Is there anything I can do to get these patches merged?
Thanks.
On Sat, 2022-03-26 at 10:27 +0800, Jianjun Wang wrote:
> These series patches add support for PCIe PHY driver on MediaTek
> chipsets.
>
> Changes in v5:
> 1. Fix typo in kerneldoc: "eFues" => "eFuse".
>
> Changes in v4:
> 1. Fix no return when calling dev_err_probe.
>
> Changes in v3:
> 1. Add introductions for structure members;
> 2. Add SoC dependent data;
> 3. Dynamically allocate efuse data;
> 4. Check return value if it's an -EPROBE_DEFER.
>
> Changes in v2:
> 1. Add specific compatible name;
> 2. Read NVMEM data at probe time;
> 3. Fix typos.
>
> Jianjun Wang (2):
> dt-bindings: phy: mediatek: Add YAML schema for PCIe PHY
> phy: mediatek: Add PCIe PHY driver
>
> .../bindings/phy/mediatek,pcie-phy.yaml | 75 +++++
> drivers/phy/mediatek/Kconfig | 11 +
> drivers/phy/mediatek/Makefile | 1 +
> drivers/phy/mediatek/phy-mtk-pcie.c | 272
> ++++++++++++++++++
> 4 files changed, 359 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml
> create mode 100644 drivers/phy/mediatek/phy-mtk-pcie.c
>
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v5 0/2] phy: mediatek: Add PCIe PHY driver
@ 2022-04-06 5:47 ` Jianjun Wang
0 siblings, 0 replies; 32+ messages in thread
From: Jianjun Wang @ 2022-04-06 5:47 UTC (permalink / raw)
To: Chunfeng Yun, Kishon Vijay Abraham I, Vinod Koul, Rob Herring,
Matthias Brugger, Chen-Yu Tsai, AngeloGioacchino Del Regno,
Krzysztof Kozlowski
Cc: Wei-Shun Chang, linux-arm-kernel, linux-mediatek, linux-phy,
devicetree, linux-kernel, rex-bc.chen, randy.wu, jieyy.yang,
chuanjia.liu, qizhong.cheng, jian.yang
Hello Maintainers,
Is there anything I can do to get these patches merged?
Thanks.
On Sat, 2022-03-26 at 10:27 +0800, Jianjun Wang wrote:
> These series patches add support for PCIe PHY driver on MediaTek
> chipsets.
>
> Changes in v5:
> 1. Fix typo in kerneldoc: "eFues" => "eFuse".
>
> Changes in v4:
> 1. Fix no return when calling dev_err_probe.
>
> Changes in v3:
> 1. Add introductions for structure members;
> 2. Add SoC dependent data;
> 3. Dynamically allocate efuse data;
> 4. Check return value if it's an -EPROBE_DEFER.
>
> Changes in v2:
> 1. Add specific compatible name;
> 2. Read NVMEM data at probe time;
> 3. Fix typos.
>
> Jianjun Wang (2):
> dt-bindings: phy: mediatek: Add YAML schema for PCIe PHY
> phy: mediatek: Add PCIe PHY driver
>
> .../bindings/phy/mediatek,pcie-phy.yaml | 75 +++++
> drivers/phy/mediatek/Kconfig | 11 +
> drivers/phy/mediatek/Makefile | 1 +
> drivers/phy/mediatek/phy-mtk-pcie.c | 272
> ++++++++++++++++++
> 4 files changed, 359 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml
> create mode 100644 drivers/phy/mediatek/phy-mtk-pcie.c
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v5 0/2] phy: mediatek: Add PCIe PHY driver
@ 2022-04-06 5:47 ` Jianjun Wang
0 siblings, 0 replies; 32+ messages in thread
From: Jianjun Wang @ 2022-04-06 5:47 UTC (permalink / raw)
To: Chunfeng Yun, Kishon Vijay Abraham I, Vinod Koul, Rob Herring,
Matthias Brugger, Chen-Yu Tsai, AngeloGioacchino Del Regno,
Krzysztof Kozlowski
Cc: Wei-Shun Chang, linux-arm-kernel, linux-mediatek, linux-phy,
devicetree, linux-kernel, rex-bc.chen, randy.wu, jieyy.yang,
chuanjia.liu, qizhong.cheng, jian.yang
Hello Maintainers,
Is there anything I can do to get these patches merged?
Thanks.
On Sat, 2022-03-26 at 10:27 +0800, Jianjun Wang wrote:
> These series patches add support for PCIe PHY driver on MediaTek
> chipsets.
>
> Changes in v5:
> 1. Fix typo in kerneldoc: "eFues" => "eFuse".
>
> Changes in v4:
> 1. Fix no return when calling dev_err_probe.
>
> Changes in v3:
> 1. Add introductions for structure members;
> 2. Add SoC dependent data;
> 3. Dynamically allocate efuse data;
> 4. Check return value if it's an -EPROBE_DEFER.
>
> Changes in v2:
> 1. Add specific compatible name;
> 2. Read NVMEM data at probe time;
> 3. Fix typos.
>
> Jianjun Wang (2):
> dt-bindings: phy: mediatek: Add YAML schema for PCIe PHY
> phy: mediatek: Add PCIe PHY driver
>
> .../bindings/phy/mediatek,pcie-phy.yaml | 75 +++++
> drivers/phy/mediatek/Kconfig | 11 +
> drivers/phy/mediatek/Makefile | 1 +
> drivers/phy/mediatek/phy-mtk-pcie.c | 272
> ++++++++++++++++++
> 4 files changed, 359 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml
> create mode 100644 drivers/phy/mediatek/phy-mtk-pcie.c
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v5 0/2] phy: mediatek: Add PCIe PHY driver
2022-04-06 5:47 ` Jianjun Wang
(?)
(?)
@ 2022-04-06 15:38 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 32+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-06 15:38 UTC (permalink / raw)
To: Jianjun Wang
Cc: Chunfeng Yun, Kishon Vijay Abraham I, Vinod Koul, Rob Herring,
Matthias Brugger, Chen-Yu Tsai, AngeloGioacchino Del Regno,
Wei-Shun Chang, linux-arm-kernel, linux-mediatek, linux-phy,
devicetree, linux-kernel, rex-bc.chen, randy.wu, jieyy.yang,
chuanjia.liu, qizhong.cheng, jian.yang
On Wed, 6 Apr 2022 at 07:47, Jianjun Wang <jianjun.wang@mediatek.com> wrote:
>
> Hello Maintainers,
>
> Is there anything I can do to get these patches merged?
Patience. :) You posted a patch during the merge window which finished
three days ago, so basically one can assume you ping folks after three
days. Three days is too fast for pinging. :(
Best regards,
Krzysztof
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v5 0/2] phy: mediatek: Add PCIe PHY driver
@ 2022-04-06 15:38 ` Krzysztof Kozlowski
0 siblings, 0 replies; 32+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-06 15:38 UTC (permalink / raw)
To: Jianjun Wang
Cc: Chunfeng Yun, Kishon Vijay Abraham I, Vinod Koul, Rob Herring,
Matthias Brugger, Chen-Yu Tsai, AngeloGioacchino Del Regno,
Wei-Shun Chang, linux-arm-kernel, linux-mediatek, linux-phy,
devicetree, linux-kernel, rex-bc.chen, randy.wu, jieyy.yang,
chuanjia.liu, qizhong.cheng, jian.yang
On Wed, 6 Apr 2022 at 07:47, Jianjun Wang <jianjun.wang@mediatek.com> wrote:
>
> Hello Maintainers,
>
> Is there anything I can do to get these patches merged?
Patience. :) You posted a patch during the merge window which finished
three days ago, so basically one can assume you ping folks after three
days. Three days is too fast for pinging. :(
Best regards,
Krzysztof
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v5 0/2] phy: mediatek: Add PCIe PHY driver
@ 2022-04-06 15:38 ` Krzysztof Kozlowski
0 siblings, 0 replies; 32+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-06 15:38 UTC (permalink / raw)
To: Jianjun Wang
Cc: Chunfeng Yun, Kishon Vijay Abraham I, Vinod Koul, Rob Herring,
Matthias Brugger, Chen-Yu Tsai, AngeloGioacchino Del Regno,
Wei-Shun Chang, linux-arm-kernel, linux-mediatek, linux-phy,
devicetree, linux-kernel, rex-bc.chen, randy.wu, jieyy.yang,
chuanjia.liu, qizhong.cheng, jian.yang
On Wed, 6 Apr 2022 at 07:47, Jianjun Wang <jianjun.wang@mediatek.com> wrote:
>
> Hello Maintainers,
>
> Is there anything I can do to get these patches merged?
Patience. :) You posted a patch during the merge window which finished
three days ago, so basically one can assume you ping folks after three
days. Three days is too fast for pinging. :(
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v5 0/2] phy: mediatek: Add PCIe PHY driver
@ 2022-04-06 15:38 ` Krzysztof Kozlowski
0 siblings, 0 replies; 32+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-06 15:38 UTC (permalink / raw)
To: Jianjun Wang
Cc: Chunfeng Yun, Kishon Vijay Abraham I, Vinod Koul, Rob Herring,
Matthias Brugger, Chen-Yu Tsai, AngeloGioacchino Del Regno,
Wei-Shun Chang, linux-arm-kernel, linux-mediatek, linux-phy,
devicetree, linux-kernel, rex-bc.chen, randy.wu, jieyy.yang,
chuanjia.liu, qizhong.cheng, jian.yang
On Wed, 6 Apr 2022 at 07:47, Jianjun Wang <jianjun.wang@mediatek.com> wrote:
>
> Hello Maintainers,
>
> Is there anything I can do to get these patches merged?
Patience. :) You posted a patch during the merge window which finished
three days ago, so basically one can assume you ping folks after three
days. Three days is too fast for pinging. :(
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v5 0/2] phy: mediatek: Add PCIe PHY driver
2022-04-06 15:38 ` Krzysztof Kozlowski
(?)
(?)
@ 2022-04-07 2:27 ` Jianjun Wang
-1 siblings, 0 replies; 32+ messages in thread
From: Jianjun Wang @ 2022-04-07 2:27 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Chunfeng Yun, Kishon Vijay Abraham I, Vinod Koul, Rob Herring,
Matthias Brugger, Chen-Yu Tsai, AngeloGioacchino Del Regno,
Wei-Shun Chang, linux-arm-kernel, linux-mediatek, linux-phy,
devicetree, linux-kernel, rex-bc.chen, randy.wu, jieyy.yang,
chuanjia.liu, qizhong.cheng, jian.yang
On Wed, 2022-04-06 at 17:38 +0200, Krzysztof Kozlowski wrote:
> On Wed, 6 Apr 2022 at 07:47, Jianjun Wang <jianjun.wang@mediatek.com>
> wrote:
> >
> > Hello Maintainers,
> >
> > Is there anything I can do to get these patches merged?
>
> Patience. :) You posted a patch during the merge window which
> finished
> three days ago, so basically one can assume you ping folks after
> three
> days. Three days is too fast for pinging. :(
Oh, right, thanks for the reminder.
Thanks.
>
> Best regards,
> Krzysztof
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v5 0/2] phy: mediatek: Add PCIe PHY driver
@ 2022-04-07 2:27 ` Jianjun Wang
0 siblings, 0 replies; 32+ messages in thread
From: Jianjun Wang @ 2022-04-07 2:27 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Chunfeng Yun, Kishon Vijay Abraham I, Vinod Koul, Rob Herring,
Matthias Brugger, Chen-Yu Tsai, AngeloGioacchino Del Regno,
Wei-Shun Chang, linux-arm-kernel, linux-mediatek, linux-phy,
devicetree, linux-kernel, rex-bc.chen, randy.wu, jieyy.yang,
chuanjia.liu, qizhong.cheng, jian.yang
On Wed, 2022-04-06 at 17:38 +0200, Krzysztof Kozlowski wrote:
> On Wed, 6 Apr 2022 at 07:47, Jianjun Wang <jianjun.wang@mediatek.com>
> wrote:
> >
> > Hello Maintainers,
> >
> > Is there anything I can do to get these patches merged?
>
> Patience. :) You posted a patch during the merge window which
> finished
> three days ago, so basically one can assume you ping folks after
> three
> days. Three days is too fast for pinging. :(
Oh, right, thanks for the reminder.
Thanks.
>
> Best regards,
> Krzysztof
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v5 0/2] phy: mediatek: Add PCIe PHY driver
@ 2022-04-07 2:27 ` Jianjun Wang
0 siblings, 0 replies; 32+ messages in thread
From: Jianjun Wang @ 2022-04-07 2:27 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Chunfeng Yun, Kishon Vijay Abraham I, Vinod Koul, Rob Herring,
Matthias Brugger, Chen-Yu Tsai, AngeloGioacchino Del Regno,
Wei-Shun Chang, linux-arm-kernel, linux-mediatek, linux-phy,
devicetree, linux-kernel, rex-bc.chen, randy.wu, jieyy.yang,
chuanjia.liu, qizhong.cheng, jian.yang
On Wed, 2022-04-06 at 17:38 +0200, Krzysztof Kozlowski wrote:
> On Wed, 6 Apr 2022 at 07:47, Jianjun Wang <jianjun.wang@mediatek.com>
> wrote:
> >
> > Hello Maintainers,
> >
> > Is there anything I can do to get these patches merged?
>
> Patience. :) You posted a patch during the merge window which
> finished
> three days ago, so basically one can assume you ping folks after
> three
> days. Three days is too fast for pinging. :(
Oh, right, thanks for the reminder.
Thanks.
>
> Best regards,
> Krzysztof
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v5 0/2] phy: mediatek: Add PCIe PHY driver
@ 2022-04-07 2:27 ` Jianjun Wang
0 siblings, 0 replies; 32+ messages in thread
From: Jianjun Wang @ 2022-04-07 2:27 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Chunfeng Yun, Kishon Vijay Abraham I, Vinod Koul, Rob Herring,
Matthias Brugger, Chen-Yu Tsai, AngeloGioacchino Del Regno,
Wei-Shun Chang, linux-arm-kernel, linux-mediatek, linux-phy,
devicetree, linux-kernel, rex-bc.chen, randy.wu, jieyy.yang,
chuanjia.liu, qizhong.cheng, jian.yang
On Wed, 2022-04-06 at 17:38 +0200, Krzysztof Kozlowski wrote:
> On Wed, 6 Apr 2022 at 07:47, Jianjun Wang <jianjun.wang@mediatek.com>
> wrote:
> >
> > Hello Maintainers,
> >
> > Is there anything I can do to get these patches merged?
>
> Patience. :) You posted a patch during the merge window which
> finished
> three days ago, so basically one can assume you ping folks after
> three
> days. Three days is too fast for pinging. :(
Oh, right, thanks for the reminder.
Thanks.
>
> Best regards,
> Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v5 2/2] phy: mediatek: Add PCIe PHY driver
2022-03-26 2:27 ` Jianjun Wang
(?)
(?)
@ 2022-04-11 17:24 ` Vinod Koul
-1 siblings, 0 replies; 32+ messages in thread
From: Vinod Koul @ 2022-04-11 17:24 UTC (permalink / raw)
To: Jianjun Wang
Cc: Chunfeng Yun, Kishon Vijay Abraham I, Rob Herring,
Matthias Brugger, Chen-Yu Tsai, AngeloGioacchino Del Regno,
Krzysztof Kozlowski, Wei-Shun Chang, linux-arm-kernel,
linux-mediatek, linux-phy, devicetree, linux-kernel, rex-bc.chen,
randy.wu, jieyy.yang, chuanjia.liu, qizhong.cheng, jian.yang
On 26-03-22, 10:27, Jianjun Wang wrote:
> Add PCIe GEN3 PHY driver support on MediaTek chipsets.
>
> Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> drivers/phy/mediatek/Kconfig | 11 ++
> drivers/phy/mediatek/Makefile | 1 +
> drivers/phy/mediatek/phy-mtk-pcie.c | 272 ++++++++++++++++++++++++++++
> 3 files changed, 284 insertions(+)
> create mode 100644 drivers/phy/mediatek/phy-mtk-pcie.c
>
> diff --git a/drivers/phy/mediatek/Kconfig b/drivers/phy/mediatek/Kconfig
> index 55f8e6c048ab..387ed1b3f2cc 100644
> --- a/drivers/phy/mediatek/Kconfig
> +++ b/drivers/phy/mediatek/Kconfig
> @@ -55,3 +55,14 @@ config PHY_MTK_MIPI_DSI
> select GENERIC_PHY
> help
> Support MIPI DSI for Mediatek SoCs.
> +
> +config PHY_MTK_PCIE
> + tristate "MediaTek PCIe-PHY Driver"
> + depends on ARCH_MEDIATEK || COMPILE_TEST
> + depends on OF
> + select GENERIC_PHY
> + help
> + Say 'Y' here to add support for MediaTek PCIe PHY driver.
> + This driver create the basic PHY instance and provides initialize
> + callback for PCIe GEN3 port, it supports software efuse
> + initialization.
> diff --git a/drivers/phy/mediatek/Makefile b/drivers/phy/mediatek/Makefile
> index ace660fbed3a..788c13147f63 100644
> --- a/drivers/phy/mediatek/Makefile
> +++ b/drivers/phy/mediatek/Makefile
> @@ -6,6 +6,7 @@
> obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
> obj-$(CONFIG_PHY_MTK_UFS) += phy-mtk-ufs.o
> obj-$(CONFIG_PHY_MTK_XSPHY) += phy-mtk-xsphy.o
> +obj-$(CONFIG_PHY_MTK_PCIE) += phy-mtk-pcie.o
>
> phy-mtk-hdmi-drv-y := phy-mtk-hdmi.o
> phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt2701.o
> diff --git a/drivers/phy/mediatek/phy-mtk-pcie.c b/drivers/phy/mediatek/phy-mtk-pcie.c
> new file mode 100644
> index 000000000000..d288655b6cff
> --- /dev/null
> +++ b/drivers/phy/mediatek/phy-mtk-pcie.c
> @@ -0,0 +1,272 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2022 MediaTek Inc.
> + * Author: Jianjun Wang <jianjun.wang@mediatek.com>
> + */
> +
> +#include <linux/bits.h>
> +#include <linux/compiler_types.h>
Why do you need this header
> +#include <linux/module.h>
> +#include <linux/nvmem-consumer.h>
> +#include <linux/of_device.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +
> +#include "phy-mtk-io.h"
> +
> +#define PEXTP_ANA_GLB_00_REG 0x9000
> +#define PEXTP_ANA_LN0_TRX_REG 0xa000
> +#define PEXTP_ANA_TX_OFFSET 0x04
> +#define PEXTP_ANA_RX_OFFSET 0x3c
> +#define PEXTP_ANA_LANE_OFFSET 0x100
> +
> +/* PEXTP_GLB_00_REG[28:24] Internal Resistor Selection of TX Bias Current */
> +#define EFUSE_GLB_INTR_SEL GENMASK(28, 24)
> +#define EFUSE_GLB_INTR_VAL(x) ((0x1f & (x)) << 24)
There are nice macros in bitfield.h which you can use to set/get value
> +
> +/* PEXTP_ANA_LN_RX_REG[3:0] RX impedance selection */
> +#define EFUSE_LN_RX_SEL GENMASK(3, 0)
> +#define EFUSE_LN_RX_VAL(x) (0xf & (x))
> +
> +/* PEXTP_ANA_LN_TX_REG[5:2] TX PMOS impedance selection */
> +#define EFUSE_LN_TX_PMOS_SEL GENMASK(5, 2)
> +#define EFUSE_LN_TX_PMOS_VAL(x) ((0xf & (x)) << 2)
> +
> +/* PEXTP_ANA_LN_TX_REG[11:8] TX NMOS impedance selection */
> +#define EFUSE_LN_TX_NMOS_SEL GENMASK(11, 8)
> +#define EFUSE_LN_TX_NMOS_VAL(x) ((0xf & (x)) << 8)
> +
> +/**
> + * struct mtk_pcie_lane_efuse - eFuse data for each lane
> + * @tx_pmos: TX PMOS impedance selection data
> + * @tx_nmos: TX NMOS impedance selection data
> + * @rx_data: RX impedance selection data
> + * @lane_efuse_supported: software eFuse data is supported for this lane
> + */
> +struct mtk_pcie_lane_efuse {
> + u32 tx_pmos;
> + u32 tx_nmos;
> + u32 rx_data;
> + bool lane_efuse_supported;
> +};
> +
> +/**
> + * struct mtk_pcie_phy_data - phy data for each SoC
> + * @num_lanes: supported lane numbers
> + * @sw_efuse_supported: support software to load eFuse data
> + */
> +struct mtk_pcie_phy_data {
> + int num_lanes;
> + bool sw_efuse_supported;
> +};
> +
> +/**
> + * struct mtk_pcie_phy - PCIe phy driver main structure
> + * @dev: pointer to device
> + * @phy: pointer to generic phy
> + * @sif_base: IO mapped register base address of system interface
> + * @data: pointer to SoC dependent data
> + * @sw_efuse_en: software eFuse enable status
> + * @efuse_glb_intr: internal resistor selection of TX bias current data
> + * @efuse: pointer to eFuse data for each lane
> + */
> +struct mtk_pcie_phy {
> + struct device *dev;
> + struct phy *phy;
> + void __iomem *sif_base;
> + const struct mtk_pcie_phy_data *data;
> +
> + bool sw_efuse_en;
> + u32 efuse_glb_intr;
> + struct mtk_pcie_lane_efuse *efuse;
> +};
> +
> +static void mtk_pcie_efuse_set_lane(struct mtk_pcie_phy *pcie_phy,
> + unsigned int lane)
> +{
> + struct mtk_pcie_lane_efuse *data = &pcie_phy->efuse[lane];
> + void __iomem *addr;
> +
> + if (!data->lane_efuse_supported)
> + return;
> +
> + addr = pcie_phy->sif_base + PEXTP_ANA_LN0_TRX_REG +
> + lane * PEXTP_ANA_LANE_OFFSET;
> +
> + mtk_phy_update_bits(addr + PEXTP_ANA_TX_OFFSET, EFUSE_LN_TX_PMOS_SEL,
> + EFUSE_LN_TX_PMOS_VAL(data->tx_pmos));
> +
> + mtk_phy_update_bits(addr + PEXTP_ANA_TX_OFFSET, EFUSE_LN_TX_NMOS_SEL,
> + EFUSE_LN_TX_NMOS_VAL(data->tx_nmos));
> +
> + mtk_phy_update_bits(addr + PEXTP_ANA_RX_OFFSET, EFUSE_LN_RX_SEL,
> + EFUSE_LN_RX_VAL(data->rx_data));
> +}
> +
> +/**
> + * mtk_pcie_phy_init() - Initialize the phy
> + * @phy: the phy to be initialized
> + *
> + * Initialize the phy by setting the efuse data.
> + * The hardware settings will be reset during suspend, it should be
> + * reinitialized when the consumer calls phy_init() again on resume.
> + */
> +static int mtk_pcie_phy_init(struct phy *phy)
> +{
> + struct mtk_pcie_phy *pcie_phy = phy_get_drvdata(phy);
> + int i;
> +
> + if (!pcie_phy->sw_efuse_en)
> + return 0;
> +
> + /* Set global data */
> + mtk_phy_update_bits(pcie_phy->sif_base + PEXTP_ANA_GLB_00_REG,
> + EFUSE_GLB_INTR_SEL,
> + EFUSE_GLB_INTR_VAL(pcie_phy->efuse_glb_intr));
> +
> + for (i = 0; i < pcie_phy->data->num_lanes; i++)
> + mtk_pcie_efuse_set_lane(pcie_phy, i);
> +
> + return 0;
> +}
> +
> +static const struct phy_ops mtk_pcie_phy_ops = {
> + .init = mtk_pcie_phy_init,
Only init for this phy? no power up/down either??
> + .owner = THIS_MODULE,
> +};
> +
> +static int mtk_pcie_efuse_read_for_lane(struct mtk_pcie_phy *pcie_phy,
> + unsigned int lane)
> +{
> + struct mtk_pcie_lane_efuse *efuse = &pcie_phy->efuse[lane];
> + struct device *dev = pcie_phy->dev;
> + char efuse_id[16];
> + int ret;
> +
> + snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_pmos", lane);
> + ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse->tx_pmos);
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to read %s\n", efuse_id);
> +
> + snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_nmos", lane);
> + ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse->tx_nmos);
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to read %s\n", efuse_id);
> +
> + snprintf(efuse_id, sizeof(efuse_id), "rx_ln%d", lane);
> + ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse->rx_data);
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to read %s\n", efuse_id);
> +
> + if (!(efuse->tx_pmos || efuse->tx_nmos || efuse->rx_data))
> + return dev_err_probe(dev, -EINVAL,
> + "No eFuse data found for lane%d, but dts enable it\n",
> + lane);
> +
> + efuse->lane_efuse_supported = true;
> +
> + return 0;
> +}
> +
> +static int mtk_pcie_read_efuse(struct mtk_pcie_phy *pcie_phy)
> +{
> + struct device *dev = pcie_phy->dev;
> + bool nvmem_enabled;
> + int ret, i;
> +
> + /* nvmem data is optional */
> + nvmem_enabled = device_property_read_bool(dev, "nvmem-cells");
> + if (!nvmem_enabled)
> + return 0;
> +
> + ret = nvmem_cell_read_variable_le_u32(dev, "glb_intr",
> + &pcie_phy->efuse_glb_intr);
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to read glb_intr\n");
> +
> + pcie_phy->sw_efuse_en = true;
> +
> + pcie_phy->efuse = devm_kzalloc(dev, pcie_phy->data->num_lanes *
> + sizeof(*pcie_phy->efuse), GFP_KERNEL);
> + if (!pcie_phy->efuse)
> + return -ENOMEM;
> +
> + for (i = 0; i < pcie_phy->data->num_lanes; i++) {
> + ret = mtk_pcie_efuse_read_for_lane(pcie_phy, i);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int mtk_pcie_phy_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct phy_provider *provider;
> + struct mtk_pcie_phy *pcie_phy;
> + int ret;
> +
> + pcie_phy = devm_kzalloc(dev, sizeof(*pcie_phy), GFP_KERNEL);
> + if (!pcie_phy)
> + return -ENOMEM;
> +
> + pcie_phy->sif_base = devm_platform_ioremap_resource_byname(pdev, "sif");
> + if (IS_ERR(pcie_phy->sif_base))
> + return dev_err_probe(dev, PTR_ERR(pcie_phy->sif_base),
> + "Failed to map phy-sif base\n");
> +
> + pcie_phy->phy = devm_phy_create(dev, dev->of_node, &mtk_pcie_phy_ops);
> + if (IS_ERR(pcie_phy->phy))
> + return dev_err_probe(dev, PTR_ERR(pcie_phy->phy),
> + "Failed to create PCIe phy\n");
> +
> + pcie_phy->dev = dev;
> + pcie_phy->data = of_device_get_match_data(dev);
> + if (!pcie_phy->data)
> + return dev_err_probe(dev, -EINVAL, "Failed to get phy data\n");
> +
> + if (pcie_phy->data->sw_efuse_supported) {
> + /*
> + * Failed to read the efuse data is not a fatal problem,
> + * ignore the failure and keep going.
> + */
> + ret = mtk_pcie_read_efuse(pcie_phy);
> + if (ret == -EPROBE_DEFER)
> + return ret;
> + }
> +
> + phy_set_drvdata(pcie_phy->phy, pcie_phy);
> +
> + provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> + if (IS_ERR(provider))
> + return dev_err_probe(dev, PTR_ERR(provider),
> + "PCIe phy probe failed\n");
> +
> + return 0;
> +}
> +
> +static const struct mtk_pcie_phy_data mt8195_data = {
> + .num_lanes = 2,
> + .sw_efuse_supported = true,
> +};
> +
> +static const struct of_device_id mtk_pcie_phy_of_match[] = {
> + { .compatible = "mediatek,mt8195-pcie-phy", .data = &mt8195_data },
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, mtk_pcie_phy_of_match);
> +
> +static struct platform_driver mtk_pcie_phy_driver = {
> + .probe = mtk_pcie_phy_probe,
> + .driver = {
> + .name = "mtk-pcie-phy",
> + .of_match_table = mtk_pcie_phy_of_match,
> + },
> +};
> +module_platform_driver(mtk_pcie_phy_driver);
> +
> +MODULE_DESCRIPTION("MediaTek PCIe PHY driver");
> +MODULE_AUTHOR("Jianjun Wang <jianjun.wang@mediatek.com>");
> +MODULE_LICENSE("GPL v2");
> --
> 2.18.0
--
~Vinod
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v5 2/2] phy: mediatek: Add PCIe PHY driver
@ 2022-04-11 17:24 ` Vinod Koul
0 siblings, 0 replies; 32+ messages in thread
From: Vinod Koul @ 2022-04-11 17:24 UTC (permalink / raw)
To: Jianjun Wang
Cc: Chunfeng Yun, Kishon Vijay Abraham I, Rob Herring,
Matthias Brugger, Chen-Yu Tsai, AngeloGioacchino Del Regno,
Krzysztof Kozlowski, Wei-Shun Chang, linux-arm-kernel,
linux-mediatek, linux-phy, devicetree, linux-kernel, rex-bc.chen,
randy.wu, jieyy.yang, chuanjia.liu, qizhong.cheng, jian.yang
On 26-03-22, 10:27, Jianjun Wang wrote:
> Add PCIe GEN3 PHY driver support on MediaTek chipsets.
>
> Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> drivers/phy/mediatek/Kconfig | 11 ++
> drivers/phy/mediatek/Makefile | 1 +
> drivers/phy/mediatek/phy-mtk-pcie.c | 272 ++++++++++++++++++++++++++++
> 3 files changed, 284 insertions(+)
> create mode 100644 drivers/phy/mediatek/phy-mtk-pcie.c
>
> diff --git a/drivers/phy/mediatek/Kconfig b/drivers/phy/mediatek/Kconfig
> index 55f8e6c048ab..387ed1b3f2cc 100644
> --- a/drivers/phy/mediatek/Kconfig
> +++ b/drivers/phy/mediatek/Kconfig
> @@ -55,3 +55,14 @@ config PHY_MTK_MIPI_DSI
> select GENERIC_PHY
> help
> Support MIPI DSI for Mediatek SoCs.
> +
> +config PHY_MTK_PCIE
> + tristate "MediaTek PCIe-PHY Driver"
> + depends on ARCH_MEDIATEK || COMPILE_TEST
> + depends on OF
> + select GENERIC_PHY
> + help
> + Say 'Y' here to add support for MediaTek PCIe PHY driver.
> + This driver create the basic PHY instance and provides initialize
> + callback for PCIe GEN3 port, it supports software efuse
> + initialization.
> diff --git a/drivers/phy/mediatek/Makefile b/drivers/phy/mediatek/Makefile
> index ace660fbed3a..788c13147f63 100644
> --- a/drivers/phy/mediatek/Makefile
> +++ b/drivers/phy/mediatek/Makefile
> @@ -6,6 +6,7 @@
> obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
> obj-$(CONFIG_PHY_MTK_UFS) += phy-mtk-ufs.o
> obj-$(CONFIG_PHY_MTK_XSPHY) += phy-mtk-xsphy.o
> +obj-$(CONFIG_PHY_MTK_PCIE) += phy-mtk-pcie.o
>
> phy-mtk-hdmi-drv-y := phy-mtk-hdmi.o
> phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt2701.o
> diff --git a/drivers/phy/mediatek/phy-mtk-pcie.c b/drivers/phy/mediatek/phy-mtk-pcie.c
> new file mode 100644
> index 000000000000..d288655b6cff
> --- /dev/null
> +++ b/drivers/phy/mediatek/phy-mtk-pcie.c
> @@ -0,0 +1,272 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2022 MediaTek Inc.
> + * Author: Jianjun Wang <jianjun.wang@mediatek.com>
> + */
> +
> +#include <linux/bits.h>
> +#include <linux/compiler_types.h>
Why do you need this header
> +#include <linux/module.h>
> +#include <linux/nvmem-consumer.h>
> +#include <linux/of_device.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +
> +#include "phy-mtk-io.h"
> +
> +#define PEXTP_ANA_GLB_00_REG 0x9000
> +#define PEXTP_ANA_LN0_TRX_REG 0xa000
> +#define PEXTP_ANA_TX_OFFSET 0x04
> +#define PEXTP_ANA_RX_OFFSET 0x3c
> +#define PEXTP_ANA_LANE_OFFSET 0x100
> +
> +/* PEXTP_GLB_00_REG[28:24] Internal Resistor Selection of TX Bias Current */
> +#define EFUSE_GLB_INTR_SEL GENMASK(28, 24)
> +#define EFUSE_GLB_INTR_VAL(x) ((0x1f & (x)) << 24)
There are nice macros in bitfield.h which you can use to set/get value
> +
> +/* PEXTP_ANA_LN_RX_REG[3:0] RX impedance selection */
> +#define EFUSE_LN_RX_SEL GENMASK(3, 0)
> +#define EFUSE_LN_RX_VAL(x) (0xf & (x))
> +
> +/* PEXTP_ANA_LN_TX_REG[5:2] TX PMOS impedance selection */
> +#define EFUSE_LN_TX_PMOS_SEL GENMASK(5, 2)
> +#define EFUSE_LN_TX_PMOS_VAL(x) ((0xf & (x)) << 2)
> +
> +/* PEXTP_ANA_LN_TX_REG[11:8] TX NMOS impedance selection */
> +#define EFUSE_LN_TX_NMOS_SEL GENMASK(11, 8)
> +#define EFUSE_LN_TX_NMOS_VAL(x) ((0xf & (x)) << 8)
> +
> +/**
> + * struct mtk_pcie_lane_efuse - eFuse data for each lane
> + * @tx_pmos: TX PMOS impedance selection data
> + * @tx_nmos: TX NMOS impedance selection data
> + * @rx_data: RX impedance selection data
> + * @lane_efuse_supported: software eFuse data is supported for this lane
> + */
> +struct mtk_pcie_lane_efuse {
> + u32 tx_pmos;
> + u32 tx_nmos;
> + u32 rx_data;
> + bool lane_efuse_supported;
> +};
> +
> +/**
> + * struct mtk_pcie_phy_data - phy data for each SoC
> + * @num_lanes: supported lane numbers
> + * @sw_efuse_supported: support software to load eFuse data
> + */
> +struct mtk_pcie_phy_data {
> + int num_lanes;
> + bool sw_efuse_supported;
> +};
> +
> +/**
> + * struct mtk_pcie_phy - PCIe phy driver main structure
> + * @dev: pointer to device
> + * @phy: pointer to generic phy
> + * @sif_base: IO mapped register base address of system interface
> + * @data: pointer to SoC dependent data
> + * @sw_efuse_en: software eFuse enable status
> + * @efuse_glb_intr: internal resistor selection of TX bias current data
> + * @efuse: pointer to eFuse data for each lane
> + */
> +struct mtk_pcie_phy {
> + struct device *dev;
> + struct phy *phy;
> + void __iomem *sif_base;
> + const struct mtk_pcie_phy_data *data;
> +
> + bool sw_efuse_en;
> + u32 efuse_glb_intr;
> + struct mtk_pcie_lane_efuse *efuse;
> +};
> +
> +static void mtk_pcie_efuse_set_lane(struct mtk_pcie_phy *pcie_phy,
> + unsigned int lane)
> +{
> + struct mtk_pcie_lane_efuse *data = &pcie_phy->efuse[lane];
> + void __iomem *addr;
> +
> + if (!data->lane_efuse_supported)
> + return;
> +
> + addr = pcie_phy->sif_base + PEXTP_ANA_LN0_TRX_REG +
> + lane * PEXTP_ANA_LANE_OFFSET;
> +
> + mtk_phy_update_bits(addr + PEXTP_ANA_TX_OFFSET, EFUSE_LN_TX_PMOS_SEL,
> + EFUSE_LN_TX_PMOS_VAL(data->tx_pmos));
> +
> + mtk_phy_update_bits(addr + PEXTP_ANA_TX_OFFSET, EFUSE_LN_TX_NMOS_SEL,
> + EFUSE_LN_TX_NMOS_VAL(data->tx_nmos));
> +
> + mtk_phy_update_bits(addr + PEXTP_ANA_RX_OFFSET, EFUSE_LN_RX_SEL,
> + EFUSE_LN_RX_VAL(data->rx_data));
> +}
> +
> +/**
> + * mtk_pcie_phy_init() - Initialize the phy
> + * @phy: the phy to be initialized
> + *
> + * Initialize the phy by setting the efuse data.
> + * The hardware settings will be reset during suspend, it should be
> + * reinitialized when the consumer calls phy_init() again on resume.
> + */
> +static int mtk_pcie_phy_init(struct phy *phy)
> +{
> + struct mtk_pcie_phy *pcie_phy = phy_get_drvdata(phy);
> + int i;
> +
> + if (!pcie_phy->sw_efuse_en)
> + return 0;
> +
> + /* Set global data */
> + mtk_phy_update_bits(pcie_phy->sif_base + PEXTP_ANA_GLB_00_REG,
> + EFUSE_GLB_INTR_SEL,
> + EFUSE_GLB_INTR_VAL(pcie_phy->efuse_glb_intr));
> +
> + for (i = 0; i < pcie_phy->data->num_lanes; i++)
> + mtk_pcie_efuse_set_lane(pcie_phy, i);
> +
> + return 0;
> +}
> +
> +static const struct phy_ops mtk_pcie_phy_ops = {
> + .init = mtk_pcie_phy_init,
Only init for this phy? no power up/down either??
> + .owner = THIS_MODULE,
> +};
> +
> +static int mtk_pcie_efuse_read_for_lane(struct mtk_pcie_phy *pcie_phy,
> + unsigned int lane)
> +{
> + struct mtk_pcie_lane_efuse *efuse = &pcie_phy->efuse[lane];
> + struct device *dev = pcie_phy->dev;
> + char efuse_id[16];
> + int ret;
> +
> + snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_pmos", lane);
> + ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse->tx_pmos);
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to read %s\n", efuse_id);
> +
> + snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_nmos", lane);
> + ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse->tx_nmos);
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to read %s\n", efuse_id);
> +
> + snprintf(efuse_id, sizeof(efuse_id), "rx_ln%d", lane);
> + ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse->rx_data);
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to read %s\n", efuse_id);
> +
> + if (!(efuse->tx_pmos || efuse->tx_nmos || efuse->rx_data))
> + return dev_err_probe(dev, -EINVAL,
> + "No eFuse data found for lane%d, but dts enable it\n",
> + lane);
> +
> + efuse->lane_efuse_supported = true;
> +
> + return 0;
> +}
> +
> +static int mtk_pcie_read_efuse(struct mtk_pcie_phy *pcie_phy)
> +{
> + struct device *dev = pcie_phy->dev;
> + bool nvmem_enabled;
> + int ret, i;
> +
> + /* nvmem data is optional */
> + nvmem_enabled = device_property_read_bool(dev, "nvmem-cells");
> + if (!nvmem_enabled)
> + return 0;
> +
> + ret = nvmem_cell_read_variable_le_u32(dev, "glb_intr",
> + &pcie_phy->efuse_glb_intr);
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to read glb_intr\n");
> +
> + pcie_phy->sw_efuse_en = true;
> +
> + pcie_phy->efuse = devm_kzalloc(dev, pcie_phy->data->num_lanes *
> + sizeof(*pcie_phy->efuse), GFP_KERNEL);
> + if (!pcie_phy->efuse)
> + return -ENOMEM;
> +
> + for (i = 0; i < pcie_phy->data->num_lanes; i++) {
> + ret = mtk_pcie_efuse_read_for_lane(pcie_phy, i);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int mtk_pcie_phy_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct phy_provider *provider;
> + struct mtk_pcie_phy *pcie_phy;
> + int ret;
> +
> + pcie_phy = devm_kzalloc(dev, sizeof(*pcie_phy), GFP_KERNEL);
> + if (!pcie_phy)
> + return -ENOMEM;
> +
> + pcie_phy->sif_base = devm_platform_ioremap_resource_byname(pdev, "sif");
> + if (IS_ERR(pcie_phy->sif_base))
> + return dev_err_probe(dev, PTR_ERR(pcie_phy->sif_base),
> + "Failed to map phy-sif base\n");
> +
> + pcie_phy->phy = devm_phy_create(dev, dev->of_node, &mtk_pcie_phy_ops);
> + if (IS_ERR(pcie_phy->phy))
> + return dev_err_probe(dev, PTR_ERR(pcie_phy->phy),
> + "Failed to create PCIe phy\n");
> +
> + pcie_phy->dev = dev;
> + pcie_phy->data = of_device_get_match_data(dev);
> + if (!pcie_phy->data)
> + return dev_err_probe(dev, -EINVAL, "Failed to get phy data\n");
> +
> + if (pcie_phy->data->sw_efuse_supported) {
> + /*
> + * Failed to read the efuse data is not a fatal problem,
> + * ignore the failure and keep going.
> + */
> + ret = mtk_pcie_read_efuse(pcie_phy);
> + if (ret == -EPROBE_DEFER)
> + return ret;
> + }
> +
> + phy_set_drvdata(pcie_phy->phy, pcie_phy);
> +
> + provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> + if (IS_ERR(provider))
> + return dev_err_probe(dev, PTR_ERR(provider),
> + "PCIe phy probe failed\n");
> +
> + return 0;
> +}
> +
> +static const struct mtk_pcie_phy_data mt8195_data = {
> + .num_lanes = 2,
> + .sw_efuse_supported = true,
> +};
> +
> +static const struct of_device_id mtk_pcie_phy_of_match[] = {
> + { .compatible = "mediatek,mt8195-pcie-phy", .data = &mt8195_data },
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, mtk_pcie_phy_of_match);
> +
> +static struct platform_driver mtk_pcie_phy_driver = {
> + .probe = mtk_pcie_phy_probe,
> + .driver = {
> + .name = "mtk-pcie-phy",
> + .of_match_table = mtk_pcie_phy_of_match,
> + },
> +};
> +module_platform_driver(mtk_pcie_phy_driver);
> +
> +MODULE_DESCRIPTION("MediaTek PCIe PHY driver");
> +MODULE_AUTHOR("Jianjun Wang <jianjun.wang@mediatek.com>");
> +MODULE_LICENSE("GPL v2");
> --
> 2.18.0
--
~Vinod
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v5 2/2] phy: mediatek: Add PCIe PHY driver
@ 2022-04-11 17:24 ` Vinod Koul
0 siblings, 0 replies; 32+ messages in thread
From: Vinod Koul @ 2022-04-11 17:24 UTC (permalink / raw)
To: Jianjun Wang
Cc: Chunfeng Yun, Kishon Vijay Abraham I, Rob Herring,
Matthias Brugger, Chen-Yu Tsai, AngeloGioacchino Del Regno,
Krzysztof Kozlowski, Wei-Shun Chang, linux-arm-kernel,
linux-mediatek, linux-phy, devicetree, linux-kernel, rex-bc.chen,
randy.wu, jieyy.yang, chuanjia.liu, qizhong.cheng, jian.yang
On 26-03-22, 10:27, Jianjun Wang wrote:
> Add PCIe GEN3 PHY driver support on MediaTek chipsets.
>
> Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> drivers/phy/mediatek/Kconfig | 11 ++
> drivers/phy/mediatek/Makefile | 1 +
> drivers/phy/mediatek/phy-mtk-pcie.c | 272 ++++++++++++++++++++++++++++
> 3 files changed, 284 insertions(+)
> create mode 100644 drivers/phy/mediatek/phy-mtk-pcie.c
>
> diff --git a/drivers/phy/mediatek/Kconfig b/drivers/phy/mediatek/Kconfig
> index 55f8e6c048ab..387ed1b3f2cc 100644
> --- a/drivers/phy/mediatek/Kconfig
> +++ b/drivers/phy/mediatek/Kconfig
> @@ -55,3 +55,14 @@ config PHY_MTK_MIPI_DSI
> select GENERIC_PHY
> help
> Support MIPI DSI for Mediatek SoCs.
> +
> +config PHY_MTK_PCIE
> + tristate "MediaTek PCIe-PHY Driver"
> + depends on ARCH_MEDIATEK || COMPILE_TEST
> + depends on OF
> + select GENERIC_PHY
> + help
> + Say 'Y' here to add support for MediaTek PCIe PHY driver.
> + This driver create the basic PHY instance and provides initialize
> + callback for PCIe GEN3 port, it supports software efuse
> + initialization.
> diff --git a/drivers/phy/mediatek/Makefile b/drivers/phy/mediatek/Makefile
> index ace660fbed3a..788c13147f63 100644
> --- a/drivers/phy/mediatek/Makefile
> +++ b/drivers/phy/mediatek/Makefile
> @@ -6,6 +6,7 @@
> obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
> obj-$(CONFIG_PHY_MTK_UFS) += phy-mtk-ufs.o
> obj-$(CONFIG_PHY_MTK_XSPHY) += phy-mtk-xsphy.o
> +obj-$(CONFIG_PHY_MTK_PCIE) += phy-mtk-pcie.o
>
> phy-mtk-hdmi-drv-y := phy-mtk-hdmi.o
> phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt2701.o
> diff --git a/drivers/phy/mediatek/phy-mtk-pcie.c b/drivers/phy/mediatek/phy-mtk-pcie.c
> new file mode 100644
> index 000000000000..d288655b6cff
> --- /dev/null
> +++ b/drivers/phy/mediatek/phy-mtk-pcie.c
> @@ -0,0 +1,272 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2022 MediaTek Inc.
> + * Author: Jianjun Wang <jianjun.wang@mediatek.com>
> + */
> +
> +#include <linux/bits.h>
> +#include <linux/compiler_types.h>
Why do you need this header
> +#include <linux/module.h>
> +#include <linux/nvmem-consumer.h>
> +#include <linux/of_device.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +
> +#include "phy-mtk-io.h"
> +
> +#define PEXTP_ANA_GLB_00_REG 0x9000
> +#define PEXTP_ANA_LN0_TRX_REG 0xa000
> +#define PEXTP_ANA_TX_OFFSET 0x04
> +#define PEXTP_ANA_RX_OFFSET 0x3c
> +#define PEXTP_ANA_LANE_OFFSET 0x100
> +
> +/* PEXTP_GLB_00_REG[28:24] Internal Resistor Selection of TX Bias Current */
> +#define EFUSE_GLB_INTR_SEL GENMASK(28, 24)
> +#define EFUSE_GLB_INTR_VAL(x) ((0x1f & (x)) << 24)
There are nice macros in bitfield.h which you can use to set/get value
> +
> +/* PEXTP_ANA_LN_RX_REG[3:0] RX impedance selection */
> +#define EFUSE_LN_RX_SEL GENMASK(3, 0)
> +#define EFUSE_LN_RX_VAL(x) (0xf & (x))
> +
> +/* PEXTP_ANA_LN_TX_REG[5:2] TX PMOS impedance selection */
> +#define EFUSE_LN_TX_PMOS_SEL GENMASK(5, 2)
> +#define EFUSE_LN_TX_PMOS_VAL(x) ((0xf & (x)) << 2)
> +
> +/* PEXTP_ANA_LN_TX_REG[11:8] TX NMOS impedance selection */
> +#define EFUSE_LN_TX_NMOS_SEL GENMASK(11, 8)
> +#define EFUSE_LN_TX_NMOS_VAL(x) ((0xf & (x)) << 8)
> +
> +/**
> + * struct mtk_pcie_lane_efuse - eFuse data for each lane
> + * @tx_pmos: TX PMOS impedance selection data
> + * @tx_nmos: TX NMOS impedance selection data
> + * @rx_data: RX impedance selection data
> + * @lane_efuse_supported: software eFuse data is supported for this lane
> + */
> +struct mtk_pcie_lane_efuse {
> + u32 tx_pmos;
> + u32 tx_nmos;
> + u32 rx_data;
> + bool lane_efuse_supported;
> +};
> +
> +/**
> + * struct mtk_pcie_phy_data - phy data for each SoC
> + * @num_lanes: supported lane numbers
> + * @sw_efuse_supported: support software to load eFuse data
> + */
> +struct mtk_pcie_phy_data {
> + int num_lanes;
> + bool sw_efuse_supported;
> +};
> +
> +/**
> + * struct mtk_pcie_phy - PCIe phy driver main structure
> + * @dev: pointer to device
> + * @phy: pointer to generic phy
> + * @sif_base: IO mapped register base address of system interface
> + * @data: pointer to SoC dependent data
> + * @sw_efuse_en: software eFuse enable status
> + * @efuse_glb_intr: internal resistor selection of TX bias current data
> + * @efuse: pointer to eFuse data for each lane
> + */
> +struct mtk_pcie_phy {
> + struct device *dev;
> + struct phy *phy;
> + void __iomem *sif_base;
> + const struct mtk_pcie_phy_data *data;
> +
> + bool sw_efuse_en;
> + u32 efuse_glb_intr;
> + struct mtk_pcie_lane_efuse *efuse;
> +};
> +
> +static void mtk_pcie_efuse_set_lane(struct mtk_pcie_phy *pcie_phy,
> + unsigned int lane)
> +{
> + struct mtk_pcie_lane_efuse *data = &pcie_phy->efuse[lane];
> + void __iomem *addr;
> +
> + if (!data->lane_efuse_supported)
> + return;
> +
> + addr = pcie_phy->sif_base + PEXTP_ANA_LN0_TRX_REG +
> + lane * PEXTP_ANA_LANE_OFFSET;
> +
> + mtk_phy_update_bits(addr + PEXTP_ANA_TX_OFFSET, EFUSE_LN_TX_PMOS_SEL,
> + EFUSE_LN_TX_PMOS_VAL(data->tx_pmos));
> +
> + mtk_phy_update_bits(addr + PEXTP_ANA_TX_OFFSET, EFUSE_LN_TX_NMOS_SEL,
> + EFUSE_LN_TX_NMOS_VAL(data->tx_nmos));
> +
> + mtk_phy_update_bits(addr + PEXTP_ANA_RX_OFFSET, EFUSE_LN_RX_SEL,
> + EFUSE_LN_RX_VAL(data->rx_data));
> +}
> +
> +/**
> + * mtk_pcie_phy_init() - Initialize the phy
> + * @phy: the phy to be initialized
> + *
> + * Initialize the phy by setting the efuse data.
> + * The hardware settings will be reset during suspend, it should be
> + * reinitialized when the consumer calls phy_init() again on resume.
> + */
> +static int mtk_pcie_phy_init(struct phy *phy)
> +{
> + struct mtk_pcie_phy *pcie_phy = phy_get_drvdata(phy);
> + int i;
> +
> + if (!pcie_phy->sw_efuse_en)
> + return 0;
> +
> + /* Set global data */
> + mtk_phy_update_bits(pcie_phy->sif_base + PEXTP_ANA_GLB_00_REG,
> + EFUSE_GLB_INTR_SEL,
> + EFUSE_GLB_INTR_VAL(pcie_phy->efuse_glb_intr));
> +
> + for (i = 0; i < pcie_phy->data->num_lanes; i++)
> + mtk_pcie_efuse_set_lane(pcie_phy, i);
> +
> + return 0;
> +}
> +
> +static const struct phy_ops mtk_pcie_phy_ops = {
> + .init = mtk_pcie_phy_init,
Only init for this phy? no power up/down either??
> + .owner = THIS_MODULE,
> +};
> +
> +static int mtk_pcie_efuse_read_for_lane(struct mtk_pcie_phy *pcie_phy,
> + unsigned int lane)
> +{
> + struct mtk_pcie_lane_efuse *efuse = &pcie_phy->efuse[lane];
> + struct device *dev = pcie_phy->dev;
> + char efuse_id[16];
> + int ret;
> +
> + snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_pmos", lane);
> + ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse->tx_pmos);
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to read %s\n", efuse_id);
> +
> + snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_nmos", lane);
> + ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse->tx_nmos);
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to read %s\n", efuse_id);
> +
> + snprintf(efuse_id, sizeof(efuse_id), "rx_ln%d", lane);
> + ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse->rx_data);
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to read %s\n", efuse_id);
> +
> + if (!(efuse->tx_pmos || efuse->tx_nmos || efuse->rx_data))
> + return dev_err_probe(dev, -EINVAL,
> + "No eFuse data found for lane%d, but dts enable it\n",
> + lane);
> +
> + efuse->lane_efuse_supported = true;
> +
> + return 0;
> +}
> +
> +static int mtk_pcie_read_efuse(struct mtk_pcie_phy *pcie_phy)
> +{
> + struct device *dev = pcie_phy->dev;
> + bool nvmem_enabled;
> + int ret, i;
> +
> + /* nvmem data is optional */
> + nvmem_enabled = device_property_read_bool(dev, "nvmem-cells");
> + if (!nvmem_enabled)
> + return 0;
> +
> + ret = nvmem_cell_read_variable_le_u32(dev, "glb_intr",
> + &pcie_phy->efuse_glb_intr);
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to read glb_intr\n");
> +
> + pcie_phy->sw_efuse_en = true;
> +
> + pcie_phy->efuse = devm_kzalloc(dev, pcie_phy->data->num_lanes *
> + sizeof(*pcie_phy->efuse), GFP_KERNEL);
> + if (!pcie_phy->efuse)
> + return -ENOMEM;
> +
> + for (i = 0; i < pcie_phy->data->num_lanes; i++) {
> + ret = mtk_pcie_efuse_read_for_lane(pcie_phy, i);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int mtk_pcie_phy_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct phy_provider *provider;
> + struct mtk_pcie_phy *pcie_phy;
> + int ret;
> +
> + pcie_phy = devm_kzalloc(dev, sizeof(*pcie_phy), GFP_KERNEL);
> + if (!pcie_phy)
> + return -ENOMEM;
> +
> + pcie_phy->sif_base = devm_platform_ioremap_resource_byname(pdev, "sif");
> + if (IS_ERR(pcie_phy->sif_base))
> + return dev_err_probe(dev, PTR_ERR(pcie_phy->sif_base),
> + "Failed to map phy-sif base\n");
> +
> + pcie_phy->phy = devm_phy_create(dev, dev->of_node, &mtk_pcie_phy_ops);
> + if (IS_ERR(pcie_phy->phy))
> + return dev_err_probe(dev, PTR_ERR(pcie_phy->phy),
> + "Failed to create PCIe phy\n");
> +
> + pcie_phy->dev = dev;
> + pcie_phy->data = of_device_get_match_data(dev);
> + if (!pcie_phy->data)
> + return dev_err_probe(dev, -EINVAL, "Failed to get phy data\n");
> +
> + if (pcie_phy->data->sw_efuse_supported) {
> + /*
> + * Failed to read the efuse data is not a fatal problem,
> + * ignore the failure and keep going.
> + */
> + ret = mtk_pcie_read_efuse(pcie_phy);
> + if (ret == -EPROBE_DEFER)
> + return ret;
> + }
> +
> + phy_set_drvdata(pcie_phy->phy, pcie_phy);
> +
> + provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> + if (IS_ERR(provider))
> + return dev_err_probe(dev, PTR_ERR(provider),
> + "PCIe phy probe failed\n");
> +
> + return 0;
> +}
> +
> +static const struct mtk_pcie_phy_data mt8195_data = {
> + .num_lanes = 2,
> + .sw_efuse_supported = true,
> +};
> +
> +static const struct of_device_id mtk_pcie_phy_of_match[] = {
> + { .compatible = "mediatek,mt8195-pcie-phy", .data = &mt8195_data },
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, mtk_pcie_phy_of_match);
> +
> +static struct platform_driver mtk_pcie_phy_driver = {
> + .probe = mtk_pcie_phy_probe,
> + .driver = {
> + .name = "mtk-pcie-phy",
> + .of_match_table = mtk_pcie_phy_of_match,
> + },
> +};
> +module_platform_driver(mtk_pcie_phy_driver);
> +
> +MODULE_DESCRIPTION("MediaTek PCIe PHY driver");
> +MODULE_AUTHOR("Jianjun Wang <jianjun.wang@mediatek.com>");
> +MODULE_LICENSE("GPL v2");
> --
> 2.18.0
--
~Vinod
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v5 2/2] phy: mediatek: Add PCIe PHY driver
@ 2022-04-11 17:24 ` Vinod Koul
0 siblings, 0 replies; 32+ messages in thread
From: Vinod Koul @ 2022-04-11 17:24 UTC (permalink / raw)
To: Jianjun Wang
Cc: Chunfeng Yun, Kishon Vijay Abraham I, Rob Herring,
Matthias Brugger, Chen-Yu Tsai, AngeloGioacchino Del Regno,
Krzysztof Kozlowski, Wei-Shun Chang, linux-arm-kernel,
linux-mediatek, linux-phy, devicetree, linux-kernel, rex-bc.chen,
randy.wu, jieyy.yang, chuanjia.liu, qizhong.cheng, jian.yang
On 26-03-22, 10:27, Jianjun Wang wrote:
> Add PCIe GEN3 PHY driver support on MediaTek chipsets.
>
> Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> drivers/phy/mediatek/Kconfig | 11 ++
> drivers/phy/mediatek/Makefile | 1 +
> drivers/phy/mediatek/phy-mtk-pcie.c | 272 ++++++++++++++++++++++++++++
> 3 files changed, 284 insertions(+)
> create mode 100644 drivers/phy/mediatek/phy-mtk-pcie.c
>
> diff --git a/drivers/phy/mediatek/Kconfig b/drivers/phy/mediatek/Kconfig
> index 55f8e6c048ab..387ed1b3f2cc 100644
> --- a/drivers/phy/mediatek/Kconfig
> +++ b/drivers/phy/mediatek/Kconfig
> @@ -55,3 +55,14 @@ config PHY_MTK_MIPI_DSI
> select GENERIC_PHY
> help
> Support MIPI DSI for Mediatek SoCs.
> +
> +config PHY_MTK_PCIE
> + tristate "MediaTek PCIe-PHY Driver"
> + depends on ARCH_MEDIATEK || COMPILE_TEST
> + depends on OF
> + select GENERIC_PHY
> + help
> + Say 'Y' here to add support for MediaTek PCIe PHY driver.
> + This driver create the basic PHY instance and provides initialize
> + callback for PCIe GEN3 port, it supports software efuse
> + initialization.
> diff --git a/drivers/phy/mediatek/Makefile b/drivers/phy/mediatek/Makefile
> index ace660fbed3a..788c13147f63 100644
> --- a/drivers/phy/mediatek/Makefile
> +++ b/drivers/phy/mediatek/Makefile
> @@ -6,6 +6,7 @@
> obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
> obj-$(CONFIG_PHY_MTK_UFS) += phy-mtk-ufs.o
> obj-$(CONFIG_PHY_MTK_XSPHY) += phy-mtk-xsphy.o
> +obj-$(CONFIG_PHY_MTK_PCIE) += phy-mtk-pcie.o
>
> phy-mtk-hdmi-drv-y := phy-mtk-hdmi.o
> phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt2701.o
> diff --git a/drivers/phy/mediatek/phy-mtk-pcie.c b/drivers/phy/mediatek/phy-mtk-pcie.c
> new file mode 100644
> index 000000000000..d288655b6cff
> --- /dev/null
> +++ b/drivers/phy/mediatek/phy-mtk-pcie.c
> @@ -0,0 +1,272 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2022 MediaTek Inc.
> + * Author: Jianjun Wang <jianjun.wang@mediatek.com>
> + */
> +
> +#include <linux/bits.h>
> +#include <linux/compiler_types.h>
Why do you need this header
> +#include <linux/module.h>
> +#include <linux/nvmem-consumer.h>
> +#include <linux/of_device.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +
> +#include "phy-mtk-io.h"
> +
> +#define PEXTP_ANA_GLB_00_REG 0x9000
> +#define PEXTP_ANA_LN0_TRX_REG 0xa000
> +#define PEXTP_ANA_TX_OFFSET 0x04
> +#define PEXTP_ANA_RX_OFFSET 0x3c
> +#define PEXTP_ANA_LANE_OFFSET 0x100
> +
> +/* PEXTP_GLB_00_REG[28:24] Internal Resistor Selection of TX Bias Current */
> +#define EFUSE_GLB_INTR_SEL GENMASK(28, 24)
> +#define EFUSE_GLB_INTR_VAL(x) ((0x1f & (x)) << 24)
There are nice macros in bitfield.h which you can use to set/get value
> +
> +/* PEXTP_ANA_LN_RX_REG[3:0] RX impedance selection */
> +#define EFUSE_LN_RX_SEL GENMASK(3, 0)
> +#define EFUSE_LN_RX_VAL(x) (0xf & (x))
> +
> +/* PEXTP_ANA_LN_TX_REG[5:2] TX PMOS impedance selection */
> +#define EFUSE_LN_TX_PMOS_SEL GENMASK(5, 2)
> +#define EFUSE_LN_TX_PMOS_VAL(x) ((0xf & (x)) << 2)
> +
> +/* PEXTP_ANA_LN_TX_REG[11:8] TX NMOS impedance selection */
> +#define EFUSE_LN_TX_NMOS_SEL GENMASK(11, 8)
> +#define EFUSE_LN_TX_NMOS_VAL(x) ((0xf & (x)) << 8)
> +
> +/**
> + * struct mtk_pcie_lane_efuse - eFuse data for each lane
> + * @tx_pmos: TX PMOS impedance selection data
> + * @tx_nmos: TX NMOS impedance selection data
> + * @rx_data: RX impedance selection data
> + * @lane_efuse_supported: software eFuse data is supported for this lane
> + */
> +struct mtk_pcie_lane_efuse {
> + u32 tx_pmos;
> + u32 tx_nmos;
> + u32 rx_data;
> + bool lane_efuse_supported;
> +};
> +
> +/**
> + * struct mtk_pcie_phy_data - phy data for each SoC
> + * @num_lanes: supported lane numbers
> + * @sw_efuse_supported: support software to load eFuse data
> + */
> +struct mtk_pcie_phy_data {
> + int num_lanes;
> + bool sw_efuse_supported;
> +};
> +
> +/**
> + * struct mtk_pcie_phy - PCIe phy driver main structure
> + * @dev: pointer to device
> + * @phy: pointer to generic phy
> + * @sif_base: IO mapped register base address of system interface
> + * @data: pointer to SoC dependent data
> + * @sw_efuse_en: software eFuse enable status
> + * @efuse_glb_intr: internal resistor selection of TX bias current data
> + * @efuse: pointer to eFuse data for each lane
> + */
> +struct mtk_pcie_phy {
> + struct device *dev;
> + struct phy *phy;
> + void __iomem *sif_base;
> + const struct mtk_pcie_phy_data *data;
> +
> + bool sw_efuse_en;
> + u32 efuse_glb_intr;
> + struct mtk_pcie_lane_efuse *efuse;
> +};
> +
> +static void mtk_pcie_efuse_set_lane(struct mtk_pcie_phy *pcie_phy,
> + unsigned int lane)
> +{
> + struct mtk_pcie_lane_efuse *data = &pcie_phy->efuse[lane];
> + void __iomem *addr;
> +
> + if (!data->lane_efuse_supported)
> + return;
> +
> + addr = pcie_phy->sif_base + PEXTP_ANA_LN0_TRX_REG +
> + lane * PEXTP_ANA_LANE_OFFSET;
> +
> + mtk_phy_update_bits(addr + PEXTP_ANA_TX_OFFSET, EFUSE_LN_TX_PMOS_SEL,
> + EFUSE_LN_TX_PMOS_VAL(data->tx_pmos));
> +
> + mtk_phy_update_bits(addr + PEXTP_ANA_TX_OFFSET, EFUSE_LN_TX_NMOS_SEL,
> + EFUSE_LN_TX_NMOS_VAL(data->tx_nmos));
> +
> + mtk_phy_update_bits(addr + PEXTP_ANA_RX_OFFSET, EFUSE_LN_RX_SEL,
> + EFUSE_LN_RX_VAL(data->rx_data));
> +}
> +
> +/**
> + * mtk_pcie_phy_init() - Initialize the phy
> + * @phy: the phy to be initialized
> + *
> + * Initialize the phy by setting the efuse data.
> + * The hardware settings will be reset during suspend, it should be
> + * reinitialized when the consumer calls phy_init() again on resume.
> + */
> +static int mtk_pcie_phy_init(struct phy *phy)
> +{
> + struct mtk_pcie_phy *pcie_phy = phy_get_drvdata(phy);
> + int i;
> +
> + if (!pcie_phy->sw_efuse_en)
> + return 0;
> +
> + /* Set global data */
> + mtk_phy_update_bits(pcie_phy->sif_base + PEXTP_ANA_GLB_00_REG,
> + EFUSE_GLB_INTR_SEL,
> + EFUSE_GLB_INTR_VAL(pcie_phy->efuse_glb_intr));
> +
> + for (i = 0; i < pcie_phy->data->num_lanes; i++)
> + mtk_pcie_efuse_set_lane(pcie_phy, i);
> +
> + return 0;
> +}
> +
> +static const struct phy_ops mtk_pcie_phy_ops = {
> + .init = mtk_pcie_phy_init,
Only init for this phy? no power up/down either??
> + .owner = THIS_MODULE,
> +};
> +
> +static int mtk_pcie_efuse_read_for_lane(struct mtk_pcie_phy *pcie_phy,
> + unsigned int lane)
> +{
> + struct mtk_pcie_lane_efuse *efuse = &pcie_phy->efuse[lane];
> + struct device *dev = pcie_phy->dev;
> + char efuse_id[16];
> + int ret;
> +
> + snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_pmos", lane);
> + ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse->tx_pmos);
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to read %s\n", efuse_id);
> +
> + snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_nmos", lane);
> + ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse->tx_nmos);
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to read %s\n", efuse_id);
> +
> + snprintf(efuse_id, sizeof(efuse_id), "rx_ln%d", lane);
> + ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse->rx_data);
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to read %s\n", efuse_id);
> +
> + if (!(efuse->tx_pmos || efuse->tx_nmos || efuse->rx_data))
> + return dev_err_probe(dev, -EINVAL,
> + "No eFuse data found for lane%d, but dts enable it\n",
> + lane);
> +
> + efuse->lane_efuse_supported = true;
> +
> + return 0;
> +}
> +
> +static int mtk_pcie_read_efuse(struct mtk_pcie_phy *pcie_phy)
> +{
> + struct device *dev = pcie_phy->dev;
> + bool nvmem_enabled;
> + int ret, i;
> +
> + /* nvmem data is optional */
> + nvmem_enabled = device_property_read_bool(dev, "nvmem-cells");
> + if (!nvmem_enabled)
> + return 0;
> +
> + ret = nvmem_cell_read_variable_le_u32(dev, "glb_intr",
> + &pcie_phy->efuse_glb_intr);
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to read glb_intr\n");
> +
> + pcie_phy->sw_efuse_en = true;
> +
> + pcie_phy->efuse = devm_kzalloc(dev, pcie_phy->data->num_lanes *
> + sizeof(*pcie_phy->efuse), GFP_KERNEL);
> + if (!pcie_phy->efuse)
> + return -ENOMEM;
> +
> + for (i = 0; i < pcie_phy->data->num_lanes; i++) {
> + ret = mtk_pcie_efuse_read_for_lane(pcie_phy, i);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int mtk_pcie_phy_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct phy_provider *provider;
> + struct mtk_pcie_phy *pcie_phy;
> + int ret;
> +
> + pcie_phy = devm_kzalloc(dev, sizeof(*pcie_phy), GFP_KERNEL);
> + if (!pcie_phy)
> + return -ENOMEM;
> +
> + pcie_phy->sif_base = devm_platform_ioremap_resource_byname(pdev, "sif");
> + if (IS_ERR(pcie_phy->sif_base))
> + return dev_err_probe(dev, PTR_ERR(pcie_phy->sif_base),
> + "Failed to map phy-sif base\n");
> +
> + pcie_phy->phy = devm_phy_create(dev, dev->of_node, &mtk_pcie_phy_ops);
> + if (IS_ERR(pcie_phy->phy))
> + return dev_err_probe(dev, PTR_ERR(pcie_phy->phy),
> + "Failed to create PCIe phy\n");
> +
> + pcie_phy->dev = dev;
> + pcie_phy->data = of_device_get_match_data(dev);
> + if (!pcie_phy->data)
> + return dev_err_probe(dev, -EINVAL, "Failed to get phy data\n");
> +
> + if (pcie_phy->data->sw_efuse_supported) {
> + /*
> + * Failed to read the efuse data is not a fatal problem,
> + * ignore the failure and keep going.
> + */
> + ret = mtk_pcie_read_efuse(pcie_phy);
> + if (ret == -EPROBE_DEFER)
> + return ret;
> + }
> +
> + phy_set_drvdata(pcie_phy->phy, pcie_phy);
> +
> + provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> + if (IS_ERR(provider))
> + return dev_err_probe(dev, PTR_ERR(provider),
> + "PCIe phy probe failed\n");
> +
> + return 0;
> +}
> +
> +static const struct mtk_pcie_phy_data mt8195_data = {
> + .num_lanes = 2,
> + .sw_efuse_supported = true,
> +};
> +
> +static const struct of_device_id mtk_pcie_phy_of_match[] = {
> + { .compatible = "mediatek,mt8195-pcie-phy", .data = &mt8195_data },
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, mtk_pcie_phy_of_match);
> +
> +static struct platform_driver mtk_pcie_phy_driver = {
> + .probe = mtk_pcie_phy_probe,
> + .driver = {
> + .name = "mtk-pcie-phy",
> + .of_match_table = mtk_pcie_phy_of_match,
> + },
> +};
> +module_platform_driver(mtk_pcie_phy_driver);
> +
> +MODULE_DESCRIPTION("MediaTek PCIe PHY driver");
> +MODULE_AUTHOR("Jianjun Wang <jianjun.wang@mediatek.com>");
> +MODULE_LICENSE("GPL v2");
> --
> 2.18.0
--
~Vinod
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v5 2/2] phy: mediatek: Add PCIe PHY driver
2022-04-11 17:24 ` Vinod Koul
(?)
(?)
@ 2022-04-14 8:50 ` Jianjun Wang
-1 siblings, 0 replies; 32+ messages in thread
From: Jianjun Wang @ 2022-04-14 8:50 UTC (permalink / raw)
To: Vinod Koul
Cc: Chunfeng Yun, Kishon Vijay Abraham I, Rob Herring,
Matthias Brugger, Chen-Yu Tsai, AngeloGioacchino Del Regno,
Krzysztof Kozlowski, Wei-Shun Chang, linux-arm-kernel,
linux-mediatek, linux-phy, devicetree, linux-kernel, rex-bc.chen,
randy.wu, jieyy.yang, chuanjia.liu, qizhong.cheng, jian.yang
On Mon, 2022-04-11 at 22:54 +0530, Vinod Koul wrote:
> On 26-03-22, 10:27, Jianjun Wang wrote:
> > Add PCIe GEN3 PHY driver support on MediaTek chipsets.
> >
> > Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> > drivers/phy/mediatek/Kconfig | 11 ++
> > drivers/phy/mediatek/Makefile | 1 +
> > drivers/phy/mediatek/phy-mtk-pcie.c | 272
> > ++++++++++++++++++++++++++++
> > 3 files changed, 284 insertions(+)
> > create mode 100644 drivers/phy/mediatek/phy-mtk-pcie.c
> >
> > diff --git a/drivers/phy/mediatek/Kconfig
> > b/drivers/phy/mediatek/Kconfig
> > index 55f8e6c048ab..387ed1b3f2cc 100644
> > --- a/drivers/phy/mediatek/Kconfig
> > +++ b/drivers/phy/mediatek/Kconfig
> > @@ -55,3 +55,14 @@ config PHY_MTK_MIPI_DSI
> > select GENERIC_PHY
> > help
> > Support MIPI DSI for Mediatek SoCs.
> > +
> > +config PHY_MTK_PCIE
> > + tristate "MediaTek PCIe-PHY Driver"
> > + depends on ARCH_MEDIATEK || COMPILE_TEST
> > + depends on OF
> > + select GENERIC_PHY
> > + help
> > + Say 'Y' here to add support for MediaTek PCIe PHY driver.
> > + This driver create the basic PHY instance and provides
> > initialize
> > + callback for PCIe GEN3 port, it supports software efuse
> > + initialization.
> > diff --git a/drivers/phy/mediatek/Makefile
> > b/drivers/phy/mediatek/Makefile
> > index ace660fbed3a..788c13147f63 100644
> > --- a/drivers/phy/mediatek/Makefile
> > +++ b/drivers/phy/mediatek/Makefile
> > @@ -6,6 +6,7 @@
> > obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
> > obj-$(CONFIG_PHY_MTK_UFS) += phy-mtk-ufs.o
> > obj-$(CONFIG_PHY_MTK_XSPHY) += phy-mtk-xsphy.o
> > +obj-$(CONFIG_PHY_MTK_PCIE) += phy-mtk-pcie.o
> >
> > phy-mtk-hdmi-drv-y := phy-mtk-hdmi.o
> > phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt2701.o
> > diff --git a/drivers/phy/mediatek/phy-mtk-pcie.c
> > b/drivers/phy/mediatek/phy-mtk-pcie.c
> > new file mode 100644
> > index 000000000000..d288655b6cff
> > --- /dev/null
> > +++ b/drivers/phy/mediatek/phy-mtk-pcie.c
> > @@ -0,0 +1,272 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (c) 2022 MediaTek Inc.
> > + * Author: Jianjun Wang <jianjun.wang@mediatek.com>
> > + */
> > +
> > +#include <linux/bits.h>
> > +#include <linux/compiler_types.h>
>
> Why do you need this header
I'll remove them in the next version, thanks.
>
> > +#include <linux/module.h>
> > +#include <linux/nvmem-consumer.h>
> > +#include <linux/of_device.h>
> > +#include <linux/phy/phy.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/slab.h>
> > +
> > +#include "phy-mtk-io.h"
> > +
> > +#define PEXTP_ANA_GLB_00_REG 0x9000
> > +#define PEXTP_ANA_LN0_TRX_REG 0xa000
> > +#define PEXTP_ANA_TX_OFFSET 0x04
> > +#define PEXTP_ANA_RX_OFFSET 0x3c
> > +#define PEXTP_ANA_LANE_OFFSET 0x100
> > +
> > +/* PEXTP_GLB_00_REG[28:24] Internal Resistor Selection of TX Bias
> > Current */
> > +#define EFUSE_GLB_INTR_SEL GENMASK(28, 24)
> > +#define EFUSE_GLB_INTR_VAL(x) ((0x1f & (x)) << 24)
>
> There are nice macros in bitfield.h which you can use to set/get
> value
Thanks for the suggestion, that's really helpful, I'll replace them
with the macros in bitfield.h.
>
> > +
> > +/* PEXTP_ANA_LN_RX_REG[3:0] RX impedance selection */
> > +#define EFUSE_LN_RX_SEL GENMASK(3, 0)
> > +#define EFUSE_LN_RX_VAL(x) (0xf & (x))
> > +
> > +/* PEXTP_ANA_LN_TX_REG[5:2] TX PMOS impedance selection */
> > +#define EFUSE_LN_TX_PMOS_SEL GENMASK(5, 2)
> > +#define EFUSE_LN_TX_PMOS_VAL(x) ((0xf & (x)) << 2)
> > +
> > +/* PEXTP_ANA_LN_TX_REG[11:8] TX NMOS impedance selection */
> > +#define EFUSE_LN_TX_NMOS_SEL GENMASK(11, 8)
> > +#define EFUSE_LN_TX_NMOS_VAL(x) ((0xf & (x)) << 8)
> > +
> > +/**
> > + * struct mtk_pcie_lane_efuse - eFuse data for each lane
> > + * @tx_pmos: TX PMOS impedance selection data
> > + * @tx_nmos: TX NMOS impedance selection data
> > + * @rx_data: RX impedance selection data
> > + * @lane_efuse_supported: software eFuse data is supported for
> > this lane
> > + */
> > +struct mtk_pcie_lane_efuse {
> > + u32 tx_pmos;
> > + u32 tx_nmos;
> > + u32 rx_data;
> > + bool lane_efuse_supported;
> > +};
> > +
> > +/**
> > + * struct mtk_pcie_phy_data - phy data for each SoC
> > + * @num_lanes: supported lane numbers
> > + * @sw_efuse_supported: support software to load eFuse data
> > + */
> > +struct mtk_pcie_phy_data {
> > + int num_lanes;
> > + bool sw_efuse_supported;
> > +};
> > +
> > +/**
> > + * struct mtk_pcie_phy - PCIe phy driver main structure
> > + * @dev: pointer to device
> > + * @phy: pointer to generic phy
> > + * @sif_base: IO mapped register base address of system interface
> > + * @data: pointer to SoC dependent data
> > + * @sw_efuse_en: software eFuse enable status
> > + * @efuse_glb_intr: internal resistor selection of TX bias current
> > data
> > + * @efuse: pointer to eFuse data for each lane
> > + */
> > +struct mtk_pcie_phy {
> > + struct device *dev;
> > + struct phy *phy;
> > + void __iomem *sif_base;
> > + const struct mtk_pcie_phy_data *data;
> > +
> > + bool sw_efuse_en;
> > + u32 efuse_glb_intr;
> > + struct mtk_pcie_lane_efuse *efuse;
> > +};
> > +
> > +static void mtk_pcie_efuse_set_lane(struct mtk_pcie_phy *pcie_phy,
> > + unsigned int lane)
> > +{
> > + struct mtk_pcie_lane_efuse *data = &pcie_phy->efuse[lane];
> > + void __iomem *addr;
> > +
> > + if (!data->lane_efuse_supported)
> > + return;
> > +
> > + addr = pcie_phy->sif_base + PEXTP_ANA_LN0_TRX_REG +
> > + lane * PEXTP_ANA_LANE_OFFSET;
> > +
> > + mtk_phy_update_bits(addr + PEXTP_ANA_TX_OFFSET,
> > EFUSE_LN_TX_PMOS_SEL,
> > + EFUSE_LN_TX_PMOS_VAL(data->tx_pmos));
> > +
> > + mtk_phy_update_bits(addr + PEXTP_ANA_TX_OFFSET,
> > EFUSE_LN_TX_NMOS_SEL,
> > + EFUSE_LN_TX_NMOS_VAL(data->tx_nmos));
> > +
> > + mtk_phy_update_bits(addr + PEXTP_ANA_RX_OFFSET,
> > EFUSE_LN_RX_SEL,
> > + EFUSE_LN_RX_VAL(data->rx_data));
> > +}
> > +
> > +/**
> > + * mtk_pcie_phy_init() - Initialize the phy
> > + * @phy: the phy to be initialized
> > + *
> > + * Initialize the phy by setting the efuse data.
> > + * The hardware settings will be reset during suspend, it should
> > be
> > + * reinitialized when the consumer calls phy_init() again on
> > resume.
> > + */
> > +static int mtk_pcie_phy_init(struct phy *phy)
> > +{
> > + struct mtk_pcie_phy *pcie_phy = phy_get_drvdata(phy);
> > + int i;
> > +
> > + if (!pcie_phy->sw_efuse_en)
> > + return 0;
> > +
> > + /* Set global data */
> > + mtk_phy_update_bits(pcie_phy->sif_base + PEXTP_ANA_GLB_00_REG,
> > + EFUSE_GLB_INTR_SEL,
> > + EFUSE_GLB_INTR_VAL(pcie_phy-
> > >efuse_glb_intr));
> > +
> > + for (i = 0; i < pcie_phy->data->num_lanes; i++)
> > + mtk_pcie_efuse_set_lane(pcie_phy, i);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct phy_ops mtk_pcie_phy_ops = {
> > + .init = mtk_pcie_phy_init,
>
> Only init for this phy? no power up/down either??
Yes, we only need this init to setting its efuse data.
>
>
> > + .owner = THIS_MODULE,
> > +};
> > +
> > +static int mtk_pcie_efuse_read_for_lane(struct mtk_pcie_phy
> > *pcie_phy,
> > + unsigned int lane)
> > +{
> > + struct mtk_pcie_lane_efuse *efuse = &pcie_phy->efuse[lane];
> > + struct device *dev = pcie_phy->dev;
> > + char efuse_id[16];
> > + int ret;
> > +
> > + snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_pmos", lane);
> > + ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse-
> > >tx_pmos);
> > + if (ret)
> > + return dev_err_probe(dev, ret, "Failed to read %s\n",
> > efuse_id);
> > +
> > + snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_nmos", lane);
> > + ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse-
> > >tx_nmos);
> > + if (ret)
> > + return dev_err_probe(dev, ret, "Failed to read %s\n",
> > efuse_id);
> > +
> > + snprintf(efuse_id, sizeof(efuse_id), "rx_ln%d", lane);
> > + ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse-
> > >rx_data);
> > + if (ret)
> > + return dev_err_probe(dev, ret, "Failed to read %s\n",
> > efuse_id);
> > +
> > + if (!(efuse->tx_pmos || efuse->tx_nmos || efuse->rx_data))
> > + return dev_err_probe(dev, -EINVAL,
> > + "No eFuse data found for lane%d,
> > but dts enable it\n",
> > + lane);
> > +
> > + efuse->lane_efuse_supported = true;
> > +
> > + return 0;
> > +}
> > +
> > +static int mtk_pcie_read_efuse(struct mtk_pcie_phy *pcie_phy)
> > +{
> > + struct device *dev = pcie_phy->dev;
> > + bool nvmem_enabled;
> > + int ret, i;
> > +
> > + /* nvmem data is optional */
> > + nvmem_enabled = device_property_read_bool(dev, "nvmem-cells");
> > + if (!nvmem_enabled)
> > + return 0;
> > +
> > + ret = nvmem_cell_read_variable_le_u32(dev, "glb_intr",
> > + &pcie_phy-
> > >efuse_glb_intr);
> > + if (ret)
> > + return dev_err_probe(dev, ret, "Failed to read
> > glb_intr\n");
> > +
> > + pcie_phy->sw_efuse_en = true;
> > +
> > + pcie_phy->efuse = devm_kzalloc(dev, pcie_phy->data->num_lanes *
> > + sizeof(*pcie_phy->efuse),
> > GFP_KERNEL);
> > + if (!pcie_phy->efuse)
> > + return -ENOMEM;
> > +
> > + for (i = 0; i < pcie_phy->data->num_lanes; i++) {
> > + ret = mtk_pcie_efuse_read_for_lane(pcie_phy, i);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int mtk_pcie_phy_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct phy_provider *provider;
> > + struct mtk_pcie_phy *pcie_phy;
> > + int ret;
> > +
> > + pcie_phy = devm_kzalloc(dev, sizeof(*pcie_phy), GFP_KERNEL);
> > + if (!pcie_phy)
> > + return -ENOMEM;
> > +
> > + pcie_phy->sif_base =
> > devm_platform_ioremap_resource_byname(pdev, "sif");
> > + if (IS_ERR(pcie_phy->sif_base))
> > + return dev_err_probe(dev, PTR_ERR(pcie_phy->sif_base),
> > + "Failed to map phy-sif base\n");
> > +
> > + pcie_phy->phy = devm_phy_create(dev, dev->of_node,
> > &mtk_pcie_phy_ops);
> > + if (IS_ERR(pcie_phy->phy))
> > + return dev_err_probe(dev, PTR_ERR(pcie_phy->phy),
> > + "Failed to create PCIe phy\n");
> > +
> > + pcie_phy->dev = dev;
> > + pcie_phy->data = of_device_get_match_data(dev);
> > + if (!pcie_phy->data)
> > + return dev_err_probe(dev, -EINVAL, "Failed to get phy
> > data\n");
> > +
> > + if (pcie_phy->data->sw_efuse_supported) {
> > + /*
> > + * Failed to read the efuse data is not a fatal
> > problem,
> > + * ignore the failure and keep going.
> > + */
> > + ret = mtk_pcie_read_efuse(pcie_phy);
> > + if (ret == -EPROBE_DEFER)
> > + return ret;
> > + }
> > +
> > + phy_set_drvdata(pcie_phy->phy, pcie_phy);
> > +
> > + provider = devm_of_phy_provider_register(dev,
> > of_phy_simple_xlate);
> > + if (IS_ERR(provider))
> > + return dev_err_probe(dev, PTR_ERR(provider),
> > + "PCIe phy probe failed\n");
> > +
> > + return 0;
> > +}
> > +
> > +static const struct mtk_pcie_phy_data mt8195_data = {
> > + .num_lanes = 2,
> > + .sw_efuse_supported = true,
> > +};
> > +
> > +static const struct of_device_id mtk_pcie_phy_of_match[] = {
> > + { .compatible = "mediatek,mt8195-pcie-phy", .data =
> > &mt8195_data },
> > + { },
> > +};
> > +MODULE_DEVICE_TABLE(of, mtk_pcie_phy_of_match);
> > +
> > +static struct platform_driver mtk_pcie_phy_driver = {
> > + .probe = mtk_pcie_phy_probe,
> > + .driver = {
> > + .name = "mtk-pcie-phy",
> > + .of_match_table = mtk_pcie_phy_of_match,
> > + },
> > +};
> > +module_platform_driver(mtk_pcie_phy_driver);
> > +
> > +MODULE_DESCRIPTION("MediaTek PCIe PHY driver");
> > +MODULE_AUTHOR("Jianjun Wang <jianjun.wang@mediatek.com>");
> > +MODULE_LICENSE("GPL v2");
> > --
> > 2.18.0
>
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v5 2/2] phy: mediatek: Add PCIe PHY driver
@ 2022-04-14 8:50 ` Jianjun Wang
0 siblings, 0 replies; 32+ messages in thread
From: Jianjun Wang @ 2022-04-14 8:50 UTC (permalink / raw)
To: Vinod Koul
Cc: Chunfeng Yun, Kishon Vijay Abraham I, Rob Herring,
Matthias Brugger, Chen-Yu Tsai, AngeloGioacchino Del Regno,
Krzysztof Kozlowski, Wei-Shun Chang, linux-arm-kernel,
linux-mediatek, linux-phy, devicetree, linux-kernel, rex-bc.chen,
randy.wu, jieyy.yang, chuanjia.liu, qizhong.cheng, jian.yang
On Mon, 2022-04-11 at 22:54 +0530, Vinod Koul wrote:
> On 26-03-22, 10:27, Jianjun Wang wrote:
> > Add PCIe GEN3 PHY driver support on MediaTek chipsets.
> >
> > Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> > drivers/phy/mediatek/Kconfig | 11 ++
> > drivers/phy/mediatek/Makefile | 1 +
> > drivers/phy/mediatek/phy-mtk-pcie.c | 272
> > ++++++++++++++++++++++++++++
> > 3 files changed, 284 insertions(+)
> > create mode 100644 drivers/phy/mediatek/phy-mtk-pcie.c
> >
> > diff --git a/drivers/phy/mediatek/Kconfig
> > b/drivers/phy/mediatek/Kconfig
> > index 55f8e6c048ab..387ed1b3f2cc 100644
> > --- a/drivers/phy/mediatek/Kconfig
> > +++ b/drivers/phy/mediatek/Kconfig
> > @@ -55,3 +55,14 @@ config PHY_MTK_MIPI_DSI
> > select GENERIC_PHY
> > help
> > Support MIPI DSI for Mediatek SoCs.
> > +
> > +config PHY_MTK_PCIE
> > + tristate "MediaTek PCIe-PHY Driver"
> > + depends on ARCH_MEDIATEK || COMPILE_TEST
> > + depends on OF
> > + select GENERIC_PHY
> > + help
> > + Say 'Y' here to add support for MediaTek PCIe PHY driver.
> > + This driver create the basic PHY instance and provides
> > initialize
> > + callback for PCIe GEN3 port, it supports software efuse
> > + initialization.
> > diff --git a/drivers/phy/mediatek/Makefile
> > b/drivers/phy/mediatek/Makefile
> > index ace660fbed3a..788c13147f63 100644
> > --- a/drivers/phy/mediatek/Makefile
> > +++ b/drivers/phy/mediatek/Makefile
> > @@ -6,6 +6,7 @@
> > obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
> > obj-$(CONFIG_PHY_MTK_UFS) += phy-mtk-ufs.o
> > obj-$(CONFIG_PHY_MTK_XSPHY) += phy-mtk-xsphy.o
> > +obj-$(CONFIG_PHY_MTK_PCIE) += phy-mtk-pcie.o
> >
> > phy-mtk-hdmi-drv-y := phy-mtk-hdmi.o
> > phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt2701.o
> > diff --git a/drivers/phy/mediatek/phy-mtk-pcie.c
> > b/drivers/phy/mediatek/phy-mtk-pcie.c
> > new file mode 100644
> > index 000000000000..d288655b6cff
> > --- /dev/null
> > +++ b/drivers/phy/mediatek/phy-mtk-pcie.c
> > @@ -0,0 +1,272 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (c) 2022 MediaTek Inc.
> > + * Author: Jianjun Wang <jianjun.wang@mediatek.com>
> > + */
> > +
> > +#include <linux/bits.h>
> > +#include <linux/compiler_types.h>
>
> Why do you need this header
I'll remove them in the next version, thanks.
>
> > +#include <linux/module.h>
> > +#include <linux/nvmem-consumer.h>
> > +#include <linux/of_device.h>
> > +#include <linux/phy/phy.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/slab.h>
> > +
> > +#include "phy-mtk-io.h"
> > +
> > +#define PEXTP_ANA_GLB_00_REG 0x9000
> > +#define PEXTP_ANA_LN0_TRX_REG 0xa000
> > +#define PEXTP_ANA_TX_OFFSET 0x04
> > +#define PEXTP_ANA_RX_OFFSET 0x3c
> > +#define PEXTP_ANA_LANE_OFFSET 0x100
> > +
> > +/* PEXTP_GLB_00_REG[28:24] Internal Resistor Selection of TX Bias
> > Current */
> > +#define EFUSE_GLB_INTR_SEL GENMASK(28, 24)
> > +#define EFUSE_GLB_INTR_VAL(x) ((0x1f & (x)) << 24)
>
> There are nice macros in bitfield.h which you can use to set/get
> value
Thanks for the suggestion, that's really helpful, I'll replace them
with the macros in bitfield.h.
>
> > +
> > +/* PEXTP_ANA_LN_RX_REG[3:0] RX impedance selection */
> > +#define EFUSE_LN_RX_SEL GENMASK(3, 0)
> > +#define EFUSE_LN_RX_VAL(x) (0xf & (x))
> > +
> > +/* PEXTP_ANA_LN_TX_REG[5:2] TX PMOS impedance selection */
> > +#define EFUSE_LN_TX_PMOS_SEL GENMASK(5, 2)
> > +#define EFUSE_LN_TX_PMOS_VAL(x) ((0xf & (x)) << 2)
> > +
> > +/* PEXTP_ANA_LN_TX_REG[11:8] TX NMOS impedance selection */
> > +#define EFUSE_LN_TX_NMOS_SEL GENMASK(11, 8)
> > +#define EFUSE_LN_TX_NMOS_VAL(x) ((0xf & (x)) << 8)
> > +
> > +/**
> > + * struct mtk_pcie_lane_efuse - eFuse data for each lane
> > + * @tx_pmos: TX PMOS impedance selection data
> > + * @tx_nmos: TX NMOS impedance selection data
> > + * @rx_data: RX impedance selection data
> > + * @lane_efuse_supported: software eFuse data is supported for
> > this lane
> > + */
> > +struct mtk_pcie_lane_efuse {
> > + u32 tx_pmos;
> > + u32 tx_nmos;
> > + u32 rx_data;
> > + bool lane_efuse_supported;
> > +};
> > +
> > +/**
> > + * struct mtk_pcie_phy_data - phy data for each SoC
> > + * @num_lanes: supported lane numbers
> > + * @sw_efuse_supported: support software to load eFuse data
> > + */
> > +struct mtk_pcie_phy_data {
> > + int num_lanes;
> > + bool sw_efuse_supported;
> > +};
> > +
> > +/**
> > + * struct mtk_pcie_phy - PCIe phy driver main structure
> > + * @dev: pointer to device
> > + * @phy: pointer to generic phy
> > + * @sif_base: IO mapped register base address of system interface
> > + * @data: pointer to SoC dependent data
> > + * @sw_efuse_en: software eFuse enable status
> > + * @efuse_glb_intr: internal resistor selection of TX bias current
> > data
> > + * @efuse: pointer to eFuse data for each lane
> > + */
> > +struct mtk_pcie_phy {
> > + struct device *dev;
> > + struct phy *phy;
> > + void __iomem *sif_base;
> > + const struct mtk_pcie_phy_data *data;
> > +
> > + bool sw_efuse_en;
> > + u32 efuse_glb_intr;
> > + struct mtk_pcie_lane_efuse *efuse;
> > +};
> > +
> > +static void mtk_pcie_efuse_set_lane(struct mtk_pcie_phy *pcie_phy,
> > + unsigned int lane)
> > +{
> > + struct mtk_pcie_lane_efuse *data = &pcie_phy->efuse[lane];
> > + void __iomem *addr;
> > +
> > + if (!data->lane_efuse_supported)
> > + return;
> > +
> > + addr = pcie_phy->sif_base + PEXTP_ANA_LN0_TRX_REG +
> > + lane * PEXTP_ANA_LANE_OFFSET;
> > +
> > + mtk_phy_update_bits(addr + PEXTP_ANA_TX_OFFSET,
> > EFUSE_LN_TX_PMOS_SEL,
> > + EFUSE_LN_TX_PMOS_VAL(data->tx_pmos));
> > +
> > + mtk_phy_update_bits(addr + PEXTP_ANA_TX_OFFSET,
> > EFUSE_LN_TX_NMOS_SEL,
> > + EFUSE_LN_TX_NMOS_VAL(data->tx_nmos));
> > +
> > + mtk_phy_update_bits(addr + PEXTP_ANA_RX_OFFSET,
> > EFUSE_LN_RX_SEL,
> > + EFUSE_LN_RX_VAL(data->rx_data));
> > +}
> > +
> > +/**
> > + * mtk_pcie_phy_init() - Initialize the phy
> > + * @phy: the phy to be initialized
> > + *
> > + * Initialize the phy by setting the efuse data.
> > + * The hardware settings will be reset during suspend, it should
> > be
> > + * reinitialized when the consumer calls phy_init() again on
> > resume.
> > + */
> > +static int mtk_pcie_phy_init(struct phy *phy)
> > +{
> > + struct mtk_pcie_phy *pcie_phy = phy_get_drvdata(phy);
> > + int i;
> > +
> > + if (!pcie_phy->sw_efuse_en)
> > + return 0;
> > +
> > + /* Set global data */
> > + mtk_phy_update_bits(pcie_phy->sif_base + PEXTP_ANA_GLB_00_REG,
> > + EFUSE_GLB_INTR_SEL,
> > + EFUSE_GLB_INTR_VAL(pcie_phy-
> > >efuse_glb_intr));
> > +
> > + for (i = 0; i < pcie_phy->data->num_lanes; i++)
> > + mtk_pcie_efuse_set_lane(pcie_phy, i);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct phy_ops mtk_pcie_phy_ops = {
> > + .init = mtk_pcie_phy_init,
>
> Only init for this phy? no power up/down either??
Yes, we only need this init to setting its efuse data.
>
>
> > + .owner = THIS_MODULE,
> > +};
> > +
> > +static int mtk_pcie_efuse_read_for_lane(struct mtk_pcie_phy
> > *pcie_phy,
> > + unsigned int lane)
> > +{
> > + struct mtk_pcie_lane_efuse *efuse = &pcie_phy->efuse[lane];
> > + struct device *dev = pcie_phy->dev;
> > + char efuse_id[16];
> > + int ret;
> > +
> > + snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_pmos", lane);
> > + ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse-
> > >tx_pmos);
> > + if (ret)
> > + return dev_err_probe(dev, ret, "Failed to read %s\n",
> > efuse_id);
> > +
> > + snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_nmos", lane);
> > + ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse-
> > >tx_nmos);
> > + if (ret)
> > + return dev_err_probe(dev, ret, "Failed to read %s\n",
> > efuse_id);
> > +
> > + snprintf(efuse_id, sizeof(efuse_id), "rx_ln%d", lane);
> > + ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse-
> > >rx_data);
> > + if (ret)
> > + return dev_err_probe(dev, ret, "Failed to read %s\n",
> > efuse_id);
> > +
> > + if (!(efuse->tx_pmos || efuse->tx_nmos || efuse->rx_data))
> > + return dev_err_probe(dev, -EINVAL,
> > + "No eFuse data found for lane%d,
> > but dts enable it\n",
> > + lane);
> > +
> > + efuse->lane_efuse_supported = true;
> > +
> > + return 0;
> > +}
> > +
> > +static int mtk_pcie_read_efuse(struct mtk_pcie_phy *pcie_phy)
> > +{
> > + struct device *dev = pcie_phy->dev;
> > + bool nvmem_enabled;
> > + int ret, i;
> > +
> > + /* nvmem data is optional */
> > + nvmem_enabled = device_property_read_bool(dev, "nvmem-cells");
> > + if (!nvmem_enabled)
> > + return 0;
> > +
> > + ret = nvmem_cell_read_variable_le_u32(dev, "glb_intr",
> > + &pcie_phy-
> > >efuse_glb_intr);
> > + if (ret)
> > + return dev_err_probe(dev, ret, "Failed to read
> > glb_intr\n");
> > +
> > + pcie_phy->sw_efuse_en = true;
> > +
> > + pcie_phy->efuse = devm_kzalloc(dev, pcie_phy->data->num_lanes *
> > + sizeof(*pcie_phy->efuse),
> > GFP_KERNEL);
> > + if (!pcie_phy->efuse)
> > + return -ENOMEM;
> > +
> > + for (i = 0; i < pcie_phy->data->num_lanes; i++) {
> > + ret = mtk_pcie_efuse_read_for_lane(pcie_phy, i);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int mtk_pcie_phy_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct phy_provider *provider;
> > + struct mtk_pcie_phy *pcie_phy;
> > + int ret;
> > +
> > + pcie_phy = devm_kzalloc(dev, sizeof(*pcie_phy), GFP_KERNEL);
> > + if (!pcie_phy)
> > + return -ENOMEM;
> > +
> > + pcie_phy->sif_base =
> > devm_platform_ioremap_resource_byname(pdev, "sif");
> > + if (IS_ERR(pcie_phy->sif_base))
> > + return dev_err_probe(dev, PTR_ERR(pcie_phy->sif_base),
> > + "Failed to map phy-sif base\n");
> > +
> > + pcie_phy->phy = devm_phy_create(dev, dev->of_node,
> > &mtk_pcie_phy_ops);
> > + if (IS_ERR(pcie_phy->phy))
> > + return dev_err_probe(dev, PTR_ERR(pcie_phy->phy),
> > + "Failed to create PCIe phy\n");
> > +
> > + pcie_phy->dev = dev;
> > + pcie_phy->data = of_device_get_match_data(dev);
> > + if (!pcie_phy->data)
> > + return dev_err_probe(dev, -EINVAL, "Failed to get phy
> > data\n");
> > +
> > + if (pcie_phy->data->sw_efuse_supported) {
> > + /*
> > + * Failed to read the efuse data is not a fatal
> > problem,
> > + * ignore the failure and keep going.
> > + */
> > + ret = mtk_pcie_read_efuse(pcie_phy);
> > + if (ret == -EPROBE_DEFER)
> > + return ret;
> > + }
> > +
> > + phy_set_drvdata(pcie_phy->phy, pcie_phy);
> > +
> > + provider = devm_of_phy_provider_register(dev,
> > of_phy_simple_xlate);
> > + if (IS_ERR(provider))
> > + return dev_err_probe(dev, PTR_ERR(provider),
> > + "PCIe phy probe failed\n");
> > +
> > + return 0;
> > +}
> > +
> > +static const struct mtk_pcie_phy_data mt8195_data = {
> > + .num_lanes = 2,
> > + .sw_efuse_supported = true,
> > +};
> > +
> > +static const struct of_device_id mtk_pcie_phy_of_match[] = {
> > + { .compatible = "mediatek,mt8195-pcie-phy", .data =
> > &mt8195_data },
> > + { },
> > +};
> > +MODULE_DEVICE_TABLE(of, mtk_pcie_phy_of_match);
> > +
> > +static struct platform_driver mtk_pcie_phy_driver = {
> > + .probe = mtk_pcie_phy_probe,
> > + .driver = {
> > + .name = "mtk-pcie-phy",
> > + .of_match_table = mtk_pcie_phy_of_match,
> > + },
> > +};
> > +module_platform_driver(mtk_pcie_phy_driver);
> > +
> > +MODULE_DESCRIPTION("MediaTek PCIe PHY driver");
> > +MODULE_AUTHOR("Jianjun Wang <jianjun.wang@mediatek.com>");
> > +MODULE_LICENSE("GPL v2");
> > --
> > 2.18.0
>
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v5 2/2] phy: mediatek: Add PCIe PHY driver
@ 2022-04-14 8:50 ` Jianjun Wang
0 siblings, 0 replies; 32+ messages in thread
From: Jianjun Wang @ 2022-04-14 8:50 UTC (permalink / raw)
To: Vinod Koul
Cc: Chunfeng Yun, Kishon Vijay Abraham I, Rob Herring,
Matthias Brugger, Chen-Yu Tsai, AngeloGioacchino Del Regno,
Krzysztof Kozlowski, Wei-Shun Chang, linux-arm-kernel,
linux-mediatek, linux-phy, devicetree, linux-kernel, rex-bc.chen,
randy.wu, jieyy.yang, chuanjia.liu, qizhong.cheng, jian.yang
On Mon, 2022-04-11 at 22:54 +0530, Vinod Koul wrote:
> On 26-03-22, 10:27, Jianjun Wang wrote:
> > Add PCIe GEN3 PHY driver support on MediaTek chipsets.
> >
> > Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> > drivers/phy/mediatek/Kconfig | 11 ++
> > drivers/phy/mediatek/Makefile | 1 +
> > drivers/phy/mediatek/phy-mtk-pcie.c | 272
> > ++++++++++++++++++++++++++++
> > 3 files changed, 284 insertions(+)
> > create mode 100644 drivers/phy/mediatek/phy-mtk-pcie.c
> >
> > diff --git a/drivers/phy/mediatek/Kconfig
> > b/drivers/phy/mediatek/Kconfig
> > index 55f8e6c048ab..387ed1b3f2cc 100644
> > --- a/drivers/phy/mediatek/Kconfig
> > +++ b/drivers/phy/mediatek/Kconfig
> > @@ -55,3 +55,14 @@ config PHY_MTK_MIPI_DSI
> > select GENERIC_PHY
> > help
> > Support MIPI DSI for Mediatek SoCs.
> > +
> > +config PHY_MTK_PCIE
> > + tristate "MediaTek PCIe-PHY Driver"
> > + depends on ARCH_MEDIATEK || COMPILE_TEST
> > + depends on OF
> > + select GENERIC_PHY
> > + help
> > + Say 'Y' here to add support for MediaTek PCIe PHY driver.
> > + This driver create the basic PHY instance and provides
> > initialize
> > + callback for PCIe GEN3 port, it supports software efuse
> > + initialization.
> > diff --git a/drivers/phy/mediatek/Makefile
> > b/drivers/phy/mediatek/Makefile
> > index ace660fbed3a..788c13147f63 100644
> > --- a/drivers/phy/mediatek/Makefile
> > +++ b/drivers/phy/mediatek/Makefile
> > @@ -6,6 +6,7 @@
> > obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
> > obj-$(CONFIG_PHY_MTK_UFS) += phy-mtk-ufs.o
> > obj-$(CONFIG_PHY_MTK_XSPHY) += phy-mtk-xsphy.o
> > +obj-$(CONFIG_PHY_MTK_PCIE) += phy-mtk-pcie.o
> >
> > phy-mtk-hdmi-drv-y := phy-mtk-hdmi.o
> > phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt2701.o
> > diff --git a/drivers/phy/mediatek/phy-mtk-pcie.c
> > b/drivers/phy/mediatek/phy-mtk-pcie.c
> > new file mode 100644
> > index 000000000000..d288655b6cff
> > --- /dev/null
> > +++ b/drivers/phy/mediatek/phy-mtk-pcie.c
> > @@ -0,0 +1,272 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (c) 2022 MediaTek Inc.
> > + * Author: Jianjun Wang <jianjun.wang@mediatek.com>
> > + */
> > +
> > +#include <linux/bits.h>
> > +#include <linux/compiler_types.h>
>
> Why do you need this header
I'll remove them in the next version, thanks.
>
> > +#include <linux/module.h>
> > +#include <linux/nvmem-consumer.h>
> > +#include <linux/of_device.h>
> > +#include <linux/phy/phy.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/slab.h>
> > +
> > +#include "phy-mtk-io.h"
> > +
> > +#define PEXTP_ANA_GLB_00_REG 0x9000
> > +#define PEXTP_ANA_LN0_TRX_REG 0xa000
> > +#define PEXTP_ANA_TX_OFFSET 0x04
> > +#define PEXTP_ANA_RX_OFFSET 0x3c
> > +#define PEXTP_ANA_LANE_OFFSET 0x100
> > +
> > +/* PEXTP_GLB_00_REG[28:24] Internal Resistor Selection of TX Bias
> > Current */
> > +#define EFUSE_GLB_INTR_SEL GENMASK(28, 24)
> > +#define EFUSE_GLB_INTR_VAL(x) ((0x1f & (x)) << 24)
>
> There are nice macros in bitfield.h which you can use to set/get
> value
Thanks for the suggestion, that's really helpful, I'll replace them
with the macros in bitfield.h.
>
> > +
> > +/* PEXTP_ANA_LN_RX_REG[3:0] RX impedance selection */
> > +#define EFUSE_LN_RX_SEL GENMASK(3, 0)
> > +#define EFUSE_LN_RX_VAL(x) (0xf & (x))
> > +
> > +/* PEXTP_ANA_LN_TX_REG[5:2] TX PMOS impedance selection */
> > +#define EFUSE_LN_TX_PMOS_SEL GENMASK(5, 2)
> > +#define EFUSE_LN_TX_PMOS_VAL(x) ((0xf & (x)) << 2)
> > +
> > +/* PEXTP_ANA_LN_TX_REG[11:8] TX NMOS impedance selection */
> > +#define EFUSE_LN_TX_NMOS_SEL GENMASK(11, 8)
> > +#define EFUSE_LN_TX_NMOS_VAL(x) ((0xf & (x)) << 8)
> > +
> > +/**
> > + * struct mtk_pcie_lane_efuse - eFuse data for each lane
> > + * @tx_pmos: TX PMOS impedance selection data
> > + * @tx_nmos: TX NMOS impedance selection data
> > + * @rx_data: RX impedance selection data
> > + * @lane_efuse_supported: software eFuse data is supported for
> > this lane
> > + */
> > +struct mtk_pcie_lane_efuse {
> > + u32 tx_pmos;
> > + u32 tx_nmos;
> > + u32 rx_data;
> > + bool lane_efuse_supported;
> > +};
> > +
> > +/**
> > + * struct mtk_pcie_phy_data - phy data for each SoC
> > + * @num_lanes: supported lane numbers
> > + * @sw_efuse_supported: support software to load eFuse data
> > + */
> > +struct mtk_pcie_phy_data {
> > + int num_lanes;
> > + bool sw_efuse_supported;
> > +};
> > +
> > +/**
> > + * struct mtk_pcie_phy - PCIe phy driver main structure
> > + * @dev: pointer to device
> > + * @phy: pointer to generic phy
> > + * @sif_base: IO mapped register base address of system interface
> > + * @data: pointer to SoC dependent data
> > + * @sw_efuse_en: software eFuse enable status
> > + * @efuse_glb_intr: internal resistor selection of TX bias current
> > data
> > + * @efuse: pointer to eFuse data for each lane
> > + */
> > +struct mtk_pcie_phy {
> > + struct device *dev;
> > + struct phy *phy;
> > + void __iomem *sif_base;
> > + const struct mtk_pcie_phy_data *data;
> > +
> > + bool sw_efuse_en;
> > + u32 efuse_glb_intr;
> > + struct mtk_pcie_lane_efuse *efuse;
> > +};
> > +
> > +static void mtk_pcie_efuse_set_lane(struct mtk_pcie_phy *pcie_phy,
> > + unsigned int lane)
> > +{
> > + struct mtk_pcie_lane_efuse *data = &pcie_phy->efuse[lane];
> > + void __iomem *addr;
> > +
> > + if (!data->lane_efuse_supported)
> > + return;
> > +
> > + addr = pcie_phy->sif_base + PEXTP_ANA_LN0_TRX_REG +
> > + lane * PEXTP_ANA_LANE_OFFSET;
> > +
> > + mtk_phy_update_bits(addr + PEXTP_ANA_TX_OFFSET,
> > EFUSE_LN_TX_PMOS_SEL,
> > + EFUSE_LN_TX_PMOS_VAL(data->tx_pmos));
> > +
> > + mtk_phy_update_bits(addr + PEXTP_ANA_TX_OFFSET,
> > EFUSE_LN_TX_NMOS_SEL,
> > + EFUSE_LN_TX_NMOS_VAL(data->tx_nmos));
> > +
> > + mtk_phy_update_bits(addr + PEXTP_ANA_RX_OFFSET,
> > EFUSE_LN_RX_SEL,
> > + EFUSE_LN_RX_VAL(data->rx_data));
> > +}
> > +
> > +/**
> > + * mtk_pcie_phy_init() - Initialize the phy
> > + * @phy: the phy to be initialized
> > + *
> > + * Initialize the phy by setting the efuse data.
> > + * The hardware settings will be reset during suspend, it should
> > be
> > + * reinitialized when the consumer calls phy_init() again on
> > resume.
> > + */
> > +static int mtk_pcie_phy_init(struct phy *phy)
> > +{
> > + struct mtk_pcie_phy *pcie_phy = phy_get_drvdata(phy);
> > + int i;
> > +
> > + if (!pcie_phy->sw_efuse_en)
> > + return 0;
> > +
> > + /* Set global data */
> > + mtk_phy_update_bits(pcie_phy->sif_base + PEXTP_ANA_GLB_00_REG,
> > + EFUSE_GLB_INTR_SEL,
> > + EFUSE_GLB_INTR_VAL(pcie_phy-
> > >efuse_glb_intr));
> > +
> > + for (i = 0; i < pcie_phy->data->num_lanes; i++)
> > + mtk_pcie_efuse_set_lane(pcie_phy, i);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct phy_ops mtk_pcie_phy_ops = {
> > + .init = mtk_pcie_phy_init,
>
> Only init for this phy? no power up/down either??
Yes, we only need this init to setting its efuse data.
>
>
> > + .owner = THIS_MODULE,
> > +};
> > +
> > +static int mtk_pcie_efuse_read_for_lane(struct mtk_pcie_phy
> > *pcie_phy,
> > + unsigned int lane)
> > +{
> > + struct mtk_pcie_lane_efuse *efuse = &pcie_phy->efuse[lane];
> > + struct device *dev = pcie_phy->dev;
> > + char efuse_id[16];
> > + int ret;
> > +
> > + snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_pmos", lane);
> > + ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse-
> > >tx_pmos);
> > + if (ret)
> > + return dev_err_probe(dev, ret, "Failed to read %s\n",
> > efuse_id);
> > +
> > + snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_nmos", lane);
> > + ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse-
> > >tx_nmos);
> > + if (ret)
> > + return dev_err_probe(dev, ret, "Failed to read %s\n",
> > efuse_id);
> > +
> > + snprintf(efuse_id, sizeof(efuse_id), "rx_ln%d", lane);
> > + ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse-
> > >rx_data);
> > + if (ret)
> > + return dev_err_probe(dev, ret, "Failed to read %s\n",
> > efuse_id);
> > +
> > + if (!(efuse->tx_pmos || efuse->tx_nmos || efuse->rx_data))
> > + return dev_err_probe(dev, -EINVAL,
> > + "No eFuse data found for lane%d,
> > but dts enable it\n",
> > + lane);
> > +
> > + efuse->lane_efuse_supported = true;
> > +
> > + return 0;
> > +}
> > +
> > +static int mtk_pcie_read_efuse(struct mtk_pcie_phy *pcie_phy)
> > +{
> > + struct device *dev = pcie_phy->dev;
> > + bool nvmem_enabled;
> > + int ret, i;
> > +
> > + /* nvmem data is optional */
> > + nvmem_enabled = device_property_read_bool(dev, "nvmem-cells");
> > + if (!nvmem_enabled)
> > + return 0;
> > +
> > + ret = nvmem_cell_read_variable_le_u32(dev, "glb_intr",
> > + &pcie_phy-
> > >efuse_glb_intr);
> > + if (ret)
> > + return dev_err_probe(dev, ret, "Failed to read
> > glb_intr\n");
> > +
> > + pcie_phy->sw_efuse_en = true;
> > +
> > + pcie_phy->efuse = devm_kzalloc(dev, pcie_phy->data->num_lanes *
> > + sizeof(*pcie_phy->efuse),
> > GFP_KERNEL);
> > + if (!pcie_phy->efuse)
> > + return -ENOMEM;
> > +
> > + for (i = 0; i < pcie_phy->data->num_lanes; i++) {
> > + ret = mtk_pcie_efuse_read_for_lane(pcie_phy, i);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int mtk_pcie_phy_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct phy_provider *provider;
> > + struct mtk_pcie_phy *pcie_phy;
> > + int ret;
> > +
> > + pcie_phy = devm_kzalloc(dev, sizeof(*pcie_phy), GFP_KERNEL);
> > + if (!pcie_phy)
> > + return -ENOMEM;
> > +
> > + pcie_phy->sif_base =
> > devm_platform_ioremap_resource_byname(pdev, "sif");
> > + if (IS_ERR(pcie_phy->sif_base))
> > + return dev_err_probe(dev, PTR_ERR(pcie_phy->sif_base),
> > + "Failed to map phy-sif base\n");
> > +
> > + pcie_phy->phy = devm_phy_create(dev, dev->of_node,
> > &mtk_pcie_phy_ops);
> > + if (IS_ERR(pcie_phy->phy))
> > + return dev_err_probe(dev, PTR_ERR(pcie_phy->phy),
> > + "Failed to create PCIe phy\n");
> > +
> > + pcie_phy->dev = dev;
> > + pcie_phy->data = of_device_get_match_data(dev);
> > + if (!pcie_phy->data)
> > + return dev_err_probe(dev, -EINVAL, "Failed to get phy
> > data\n");
> > +
> > + if (pcie_phy->data->sw_efuse_supported) {
> > + /*
> > + * Failed to read the efuse data is not a fatal
> > problem,
> > + * ignore the failure and keep going.
> > + */
> > + ret = mtk_pcie_read_efuse(pcie_phy);
> > + if (ret == -EPROBE_DEFER)
> > + return ret;
> > + }
> > +
> > + phy_set_drvdata(pcie_phy->phy, pcie_phy);
> > +
> > + provider = devm_of_phy_provider_register(dev,
> > of_phy_simple_xlate);
> > + if (IS_ERR(provider))
> > + return dev_err_probe(dev, PTR_ERR(provider),
> > + "PCIe phy probe failed\n");
> > +
> > + return 0;
> > +}
> > +
> > +static const struct mtk_pcie_phy_data mt8195_data = {
> > + .num_lanes = 2,
> > + .sw_efuse_supported = true,
> > +};
> > +
> > +static const struct of_device_id mtk_pcie_phy_of_match[] = {
> > + { .compatible = "mediatek,mt8195-pcie-phy", .data =
> > &mt8195_data },
> > + { },
> > +};
> > +MODULE_DEVICE_TABLE(of, mtk_pcie_phy_of_match);
> > +
> > +static struct platform_driver mtk_pcie_phy_driver = {
> > + .probe = mtk_pcie_phy_probe,
> > + .driver = {
> > + .name = "mtk-pcie-phy",
> > + .of_match_table = mtk_pcie_phy_of_match,
> > + },
> > +};
> > +module_platform_driver(mtk_pcie_phy_driver);
> > +
> > +MODULE_DESCRIPTION("MediaTek PCIe PHY driver");
> > +MODULE_AUTHOR("Jianjun Wang <jianjun.wang@mediatek.com>");
> > +MODULE_LICENSE("GPL v2");
> > --
> > 2.18.0
>
>
--
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linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v5 2/2] phy: mediatek: Add PCIe PHY driver
@ 2022-04-14 8:50 ` Jianjun Wang
0 siblings, 0 replies; 32+ messages in thread
From: Jianjun Wang @ 2022-04-14 8:50 UTC (permalink / raw)
To: Vinod Koul
Cc: Chunfeng Yun, Kishon Vijay Abraham I, Rob Herring,
Matthias Brugger, Chen-Yu Tsai, AngeloGioacchino Del Regno,
Krzysztof Kozlowski, Wei-Shun Chang, linux-arm-kernel,
linux-mediatek, linux-phy, devicetree, linux-kernel, rex-bc.chen,
randy.wu, jieyy.yang, chuanjia.liu, qizhong.cheng, jian.yang
On Mon, 2022-04-11 at 22:54 +0530, Vinod Koul wrote:
> On 26-03-22, 10:27, Jianjun Wang wrote:
> > Add PCIe GEN3 PHY driver support on MediaTek chipsets.
> >
> > Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> > drivers/phy/mediatek/Kconfig | 11 ++
> > drivers/phy/mediatek/Makefile | 1 +
> > drivers/phy/mediatek/phy-mtk-pcie.c | 272
> > ++++++++++++++++++++++++++++
> > 3 files changed, 284 insertions(+)
> > create mode 100644 drivers/phy/mediatek/phy-mtk-pcie.c
> >
> > diff --git a/drivers/phy/mediatek/Kconfig
> > b/drivers/phy/mediatek/Kconfig
> > index 55f8e6c048ab..387ed1b3f2cc 100644
> > --- a/drivers/phy/mediatek/Kconfig
> > +++ b/drivers/phy/mediatek/Kconfig
> > @@ -55,3 +55,14 @@ config PHY_MTK_MIPI_DSI
> > select GENERIC_PHY
> > help
> > Support MIPI DSI for Mediatek SoCs.
> > +
> > +config PHY_MTK_PCIE
> > + tristate "MediaTek PCIe-PHY Driver"
> > + depends on ARCH_MEDIATEK || COMPILE_TEST
> > + depends on OF
> > + select GENERIC_PHY
> > + help
> > + Say 'Y' here to add support for MediaTek PCIe PHY driver.
> > + This driver create the basic PHY instance and provides
> > initialize
> > + callback for PCIe GEN3 port, it supports software efuse
> > + initialization.
> > diff --git a/drivers/phy/mediatek/Makefile
> > b/drivers/phy/mediatek/Makefile
> > index ace660fbed3a..788c13147f63 100644
> > --- a/drivers/phy/mediatek/Makefile
> > +++ b/drivers/phy/mediatek/Makefile
> > @@ -6,6 +6,7 @@
> > obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
> > obj-$(CONFIG_PHY_MTK_UFS) += phy-mtk-ufs.o
> > obj-$(CONFIG_PHY_MTK_XSPHY) += phy-mtk-xsphy.o
> > +obj-$(CONFIG_PHY_MTK_PCIE) += phy-mtk-pcie.o
> >
> > phy-mtk-hdmi-drv-y := phy-mtk-hdmi.o
> > phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt2701.o
> > diff --git a/drivers/phy/mediatek/phy-mtk-pcie.c
> > b/drivers/phy/mediatek/phy-mtk-pcie.c
> > new file mode 100644
> > index 000000000000..d288655b6cff
> > --- /dev/null
> > +++ b/drivers/phy/mediatek/phy-mtk-pcie.c
> > @@ -0,0 +1,272 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (c) 2022 MediaTek Inc.
> > + * Author: Jianjun Wang <jianjun.wang@mediatek.com>
> > + */
> > +
> > +#include <linux/bits.h>
> > +#include <linux/compiler_types.h>
>
> Why do you need this header
I'll remove them in the next version, thanks.
>
> > +#include <linux/module.h>
> > +#include <linux/nvmem-consumer.h>
> > +#include <linux/of_device.h>
> > +#include <linux/phy/phy.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/slab.h>
> > +
> > +#include "phy-mtk-io.h"
> > +
> > +#define PEXTP_ANA_GLB_00_REG 0x9000
> > +#define PEXTP_ANA_LN0_TRX_REG 0xa000
> > +#define PEXTP_ANA_TX_OFFSET 0x04
> > +#define PEXTP_ANA_RX_OFFSET 0x3c
> > +#define PEXTP_ANA_LANE_OFFSET 0x100
> > +
> > +/* PEXTP_GLB_00_REG[28:24] Internal Resistor Selection of TX Bias
> > Current */
> > +#define EFUSE_GLB_INTR_SEL GENMASK(28, 24)
> > +#define EFUSE_GLB_INTR_VAL(x) ((0x1f & (x)) << 24)
>
> There are nice macros in bitfield.h which you can use to set/get
> value
Thanks for the suggestion, that's really helpful, I'll replace them
with the macros in bitfield.h.
>
> > +
> > +/* PEXTP_ANA_LN_RX_REG[3:0] RX impedance selection */
> > +#define EFUSE_LN_RX_SEL GENMASK(3, 0)
> > +#define EFUSE_LN_RX_VAL(x) (0xf & (x))
> > +
> > +/* PEXTP_ANA_LN_TX_REG[5:2] TX PMOS impedance selection */
> > +#define EFUSE_LN_TX_PMOS_SEL GENMASK(5, 2)
> > +#define EFUSE_LN_TX_PMOS_VAL(x) ((0xf & (x)) << 2)
> > +
> > +/* PEXTP_ANA_LN_TX_REG[11:8] TX NMOS impedance selection */
> > +#define EFUSE_LN_TX_NMOS_SEL GENMASK(11, 8)
> > +#define EFUSE_LN_TX_NMOS_VAL(x) ((0xf & (x)) << 8)
> > +
> > +/**
> > + * struct mtk_pcie_lane_efuse - eFuse data for each lane
> > + * @tx_pmos: TX PMOS impedance selection data
> > + * @tx_nmos: TX NMOS impedance selection data
> > + * @rx_data: RX impedance selection data
> > + * @lane_efuse_supported: software eFuse data is supported for
> > this lane
> > + */
> > +struct mtk_pcie_lane_efuse {
> > + u32 tx_pmos;
> > + u32 tx_nmos;
> > + u32 rx_data;
> > + bool lane_efuse_supported;
> > +};
> > +
> > +/**
> > + * struct mtk_pcie_phy_data - phy data for each SoC
> > + * @num_lanes: supported lane numbers
> > + * @sw_efuse_supported: support software to load eFuse data
> > + */
> > +struct mtk_pcie_phy_data {
> > + int num_lanes;
> > + bool sw_efuse_supported;
> > +};
> > +
> > +/**
> > + * struct mtk_pcie_phy - PCIe phy driver main structure
> > + * @dev: pointer to device
> > + * @phy: pointer to generic phy
> > + * @sif_base: IO mapped register base address of system interface
> > + * @data: pointer to SoC dependent data
> > + * @sw_efuse_en: software eFuse enable status
> > + * @efuse_glb_intr: internal resistor selection of TX bias current
> > data
> > + * @efuse: pointer to eFuse data for each lane
> > + */
> > +struct mtk_pcie_phy {
> > + struct device *dev;
> > + struct phy *phy;
> > + void __iomem *sif_base;
> > + const struct mtk_pcie_phy_data *data;
> > +
> > + bool sw_efuse_en;
> > + u32 efuse_glb_intr;
> > + struct mtk_pcie_lane_efuse *efuse;
> > +};
> > +
> > +static void mtk_pcie_efuse_set_lane(struct mtk_pcie_phy *pcie_phy,
> > + unsigned int lane)
> > +{
> > + struct mtk_pcie_lane_efuse *data = &pcie_phy->efuse[lane];
> > + void __iomem *addr;
> > +
> > + if (!data->lane_efuse_supported)
> > + return;
> > +
> > + addr = pcie_phy->sif_base + PEXTP_ANA_LN0_TRX_REG +
> > + lane * PEXTP_ANA_LANE_OFFSET;
> > +
> > + mtk_phy_update_bits(addr + PEXTP_ANA_TX_OFFSET,
> > EFUSE_LN_TX_PMOS_SEL,
> > + EFUSE_LN_TX_PMOS_VAL(data->tx_pmos));
> > +
> > + mtk_phy_update_bits(addr + PEXTP_ANA_TX_OFFSET,
> > EFUSE_LN_TX_NMOS_SEL,
> > + EFUSE_LN_TX_NMOS_VAL(data->tx_nmos));
> > +
> > + mtk_phy_update_bits(addr + PEXTP_ANA_RX_OFFSET,
> > EFUSE_LN_RX_SEL,
> > + EFUSE_LN_RX_VAL(data->rx_data));
> > +}
> > +
> > +/**
> > + * mtk_pcie_phy_init() - Initialize the phy
> > + * @phy: the phy to be initialized
> > + *
> > + * Initialize the phy by setting the efuse data.
> > + * The hardware settings will be reset during suspend, it should
> > be
> > + * reinitialized when the consumer calls phy_init() again on
> > resume.
> > + */
> > +static int mtk_pcie_phy_init(struct phy *phy)
> > +{
> > + struct mtk_pcie_phy *pcie_phy = phy_get_drvdata(phy);
> > + int i;
> > +
> > + if (!pcie_phy->sw_efuse_en)
> > + return 0;
> > +
> > + /* Set global data */
> > + mtk_phy_update_bits(pcie_phy->sif_base + PEXTP_ANA_GLB_00_REG,
> > + EFUSE_GLB_INTR_SEL,
> > + EFUSE_GLB_INTR_VAL(pcie_phy-
> > >efuse_glb_intr));
> > +
> > + for (i = 0; i < pcie_phy->data->num_lanes; i++)
> > + mtk_pcie_efuse_set_lane(pcie_phy, i);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct phy_ops mtk_pcie_phy_ops = {
> > + .init = mtk_pcie_phy_init,
>
> Only init for this phy? no power up/down either??
Yes, we only need this init to setting its efuse data.
>
>
> > + .owner = THIS_MODULE,
> > +};
> > +
> > +static int mtk_pcie_efuse_read_for_lane(struct mtk_pcie_phy
> > *pcie_phy,
> > + unsigned int lane)
> > +{
> > + struct mtk_pcie_lane_efuse *efuse = &pcie_phy->efuse[lane];
> > + struct device *dev = pcie_phy->dev;
> > + char efuse_id[16];
> > + int ret;
> > +
> > + snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_pmos", lane);
> > + ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse-
> > >tx_pmos);
> > + if (ret)
> > + return dev_err_probe(dev, ret, "Failed to read %s\n",
> > efuse_id);
> > +
> > + snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_nmos", lane);
> > + ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse-
> > >tx_nmos);
> > + if (ret)
> > + return dev_err_probe(dev, ret, "Failed to read %s\n",
> > efuse_id);
> > +
> > + snprintf(efuse_id, sizeof(efuse_id), "rx_ln%d", lane);
> > + ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse-
> > >rx_data);
> > + if (ret)
> > + return dev_err_probe(dev, ret, "Failed to read %s\n",
> > efuse_id);
> > +
> > + if (!(efuse->tx_pmos || efuse->tx_nmos || efuse->rx_data))
> > + return dev_err_probe(dev, -EINVAL,
> > + "No eFuse data found for lane%d,
> > but dts enable it\n",
> > + lane);
> > +
> > + efuse->lane_efuse_supported = true;
> > +
> > + return 0;
> > +}
> > +
> > +static int mtk_pcie_read_efuse(struct mtk_pcie_phy *pcie_phy)
> > +{
> > + struct device *dev = pcie_phy->dev;
> > + bool nvmem_enabled;
> > + int ret, i;
> > +
> > + /* nvmem data is optional */
> > + nvmem_enabled = device_property_read_bool(dev, "nvmem-cells");
> > + if (!nvmem_enabled)
> > + return 0;
> > +
> > + ret = nvmem_cell_read_variable_le_u32(dev, "glb_intr",
> > + &pcie_phy-
> > >efuse_glb_intr);
> > + if (ret)
> > + return dev_err_probe(dev, ret, "Failed to read
> > glb_intr\n");
> > +
> > + pcie_phy->sw_efuse_en = true;
> > +
> > + pcie_phy->efuse = devm_kzalloc(dev, pcie_phy->data->num_lanes *
> > + sizeof(*pcie_phy->efuse),
> > GFP_KERNEL);
> > + if (!pcie_phy->efuse)
> > + return -ENOMEM;
> > +
> > + for (i = 0; i < pcie_phy->data->num_lanes; i++) {
> > + ret = mtk_pcie_efuse_read_for_lane(pcie_phy, i);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int mtk_pcie_phy_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct phy_provider *provider;
> > + struct mtk_pcie_phy *pcie_phy;
> > + int ret;
> > +
> > + pcie_phy = devm_kzalloc(dev, sizeof(*pcie_phy), GFP_KERNEL);
> > + if (!pcie_phy)
> > + return -ENOMEM;
> > +
> > + pcie_phy->sif_base =
> > devm_platform_ioremap_resource_byname(pdev, "sif");
> > + if (IS_ERR(pcie_phy->sif_base))
> > + return dev_err_probe(dev, PTR_ERR(pcie_phy->sif_base),
> > + "Failed to map phy-sif base\n");
> > +
> > + pcie_phy->phy = devm_phy_create(dev, dev->of_node,
> > &mtk_pcie_phy_ops);
> > + if (IS_ERR(pcie_phy->phy))
> > + return dev_err_probe(dev, PTR_ERR(pcie_phy->phy),
> > + "Failed to create PCIe phy\n");
> > +
> > + pcie_phy->dev = dev;
> > + pcie_phy->data = of_device_get_match_data(dev);
> > + if (!pcie_phy->data)
> > + return dev_err_probe(dev, -EINVAL, "Failed to get phy
> > data\n");
> > +
> > + if (pcie_phy->data->sw_efuse_supported) {
> > + /*
> > + * Failed to read the efuse data is not a fatal
> > problem,
> > + * ignore the failure and keep going.
> > + */
> > + ret = mtk_pcie_read_efuse(pcie_phy);
> > + if (ret == -EPROBE_DEFER)
> > + return ret;
> > + }
> > +
> > + phy_set_drvdata(pcie_phy->phy, pcie_phy);
> > +
> > + provider = devm_of_phy_provider_register(dev,
> > of_phy_simple_xlate);
> > + if (IS_ERR(provider))
> > + return dev_err_probe(dev, PTR_ERR(provider),
> > + "PCIe phy probe failed\n");
> > +
> > + return 0;
> > +}
> > +
> > +static const struct mtk_pcie_phy_data mt8195_data = {
> > + .num_lanes = 2,
> > + .sw_efuse_supported = true,
> > +};
> > +
> > +static const struct of_device_id mtk_pcie_phy_of_match[] = {
> > + { .compatible = "mediatek,mt8195-pcie-phy", .data =
> > &mt8195_data },
> > + { },
> > +};
> > +MODULE_DEVICE_TABLE(of, mtk_pcie_phy_of_match);
> > +
> > +static struct platform_driver mtk_pcie_phy_driver = {
> > + .probe = mtk_pcie_phy_probe,
> > + .driver = {
> > + .name = "mtk-pcie-phy",
> > + .of_match_table = mtk_pcie_phy_of_match,
> > + },
> > +};
> > +module_platform_driver(mtk_pcie_phy_driver);
> > +
> > +MODULE_DESCRIPTION("MediaTek PCIe PHY driver");
> > +MODULE_AUTHOR("Jianjun Wang <jianjun.wang@mediatek.com>");
> > +MODULE_LICENSE("GPL v2");
> > --
> > 2.18.0
>
>
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^ permalink raw reply [flat|nested] 32+ messages in thread
end of thread, other threads:[~2022-04-14 8:56 UTC | newest]
Thread overview: 32+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-03-26 2:27 [PATCH v5 0/2] phy: mediatek: Add PCIe PHY driver Jianjun Wang
2022-03-26 2:27 ` Jianjun Wang
2022-03-26 2:27 ` Jianjun Wang
2022-03-26 2:27 ` Jianjun Wang
2022-03-26 2:27 ` [PATCH v5 1/2] dt-bindings: phy: mediatek: Add YAML schema for PCIe PHY Jianjun Wang
2022-03-26 2:27 ` Jianjun Wang
2022-03-26 2:27 ` Jianjun Wang
2022-03-26 2:27 ` Jianjun Wang
2022-03-26 2:27 ` [PATCH v5 2/2] phy: mediatek: Add PCIe PHY driver Jianjun Wang
2022-03-26 2:27 ` Jianjun Wang
2022-03-26 2:27 ` Jianjun Wang
2022-03-26 2:27 ` Jianjun Wang
2022-04-11 17:24 ` Vinod Koul
2022-04-11 17:24 ` Vinod Koul
2022-04-11 17:24 ` Vinod Koul
2022-04-11 17:24 ` Vinod Koul
2022-04-14 8:50 ` Jianjun Wang
2022-04-14 8:50 ` Jianjun Wang
2022-04-14 8:50 ` Jianjun Wang
2022-04-14 8:50 ` Jianjun Wang
2022-04-06 5:47 ` [PATCH v5 0/2] " Jianjun Wang
2022-04-06 5:47 ` Jianjun Wang
2022-04-06 5:47 ` Jianjun Wang
2022-04-06 5:47 ` Jianjun Wang
2022-04-06 15:38 ` Krzysztof Kozlowski
2022-04-06 15:38 ` Krzysztof Kozlowski
2022-04-06 15:38 ` Krzysztof Kozlowski
2022-04-06 15:38 ` Krzysztof Kozlowski
2022-04-07 2:27 ` Jianjun Wang
2022-04-07 2:27 ` Jianjun Wang
2022-04-07 2:27 ` Jianjun Wang
2022-04-07 2:27 ` Jianjun Wang
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