From: Michael Walle <michael@walle.cc> To: Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Nicolas Ferre <nicolas.ferre@microchip.com>, Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Walle <michael@walle.cc> Subject: [PATCH] ARM: dts: lan966x: fix sys_clk frequency Date: Sat, 26 Mar 2022 20:40:28 +0100 [thread overview] Message-ID: <20220326194028.2945985-1-michael@walle.cc> (raw) The sys_clk frequency is 165.625MHz. The register reference of the Generic Clock controller lists the CPU clock as 600MHz, the DDR clock as 300MHz and the SYS clock as 162.5MHz. This is wrong. It was first noticed during the fan driver development and it was measured and verified via the CLK_MON output of the SoC which can be configured to output sys_clk/64. The core PLL settings (which drives the SYS clock) seems to be as follows: DIVF = 52 DIVQ = 3 DIVR = 1 With a refernce clock of 25MHz, this means we have a post divider clock Fpfd = Fref / (DIVR + 1) = 25MHz / (1 + 1) = 12.5MHz The resulting VCO frequency is then Fvco = Fpfd * (DIVF + 1) * 2 = 12.5MHz * (52 + 1) * 2 = 1325MHz And the output frequency is Fout = Fvco / 2^DIVQ = 1325MHz / 2^3 = 165.625Mhz This all adds up to the constrains of the PLL: 10MHz <= Fpfd <= 200MHz 20MHz <= Fout <= 1000MHz 1000MHz <= Fvco <= 2000MHz Fixes: 290deaa10c50 ("ARM: dts: add DT for lan966 SoC and 2-port board pcb8291") Signed-off-by: Michael Walle <michael@walle.cc> --- arch/arm/boot/dts/lan966x.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi index 14c9cb3c0f3b..03045ec4aca4 100644 --- a/arch/arm/boot/dts/lan966x.dtsi +++ b/arch/arm/boot/dts/lan966x.dtsi @@ -38,7 +38,7 @@ clocks { sys_clk: sys_clk { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <162500000>; + clock-frequency = <165625000>; }; cpu_clk: cpu_clk { -- 2.30.2
next reply other threads:[~2022-03-26 19:41 UTC|newest] Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-03-26 19:40 Michael Walle [this message] 2022-04-28 8:49 ` Michael Walle 2022-06-22 11:51 ` Michael Walle 2022-07-15 18:41 ` Michael Walle 2022-07-18 6:36 ` Claudiu.Beznea 2022-06-29 11:40 ` Kavyasree.Kotagiri
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20220326194028.2945985-1-michael@walle.cc \ --to=michael@walle.cc \ --cc=devicetree@vger.kernel.org \ --cc=kavyasree.kotagiri@microchip.com \ --cc=krzk+dt@kernel.org \ --cc=linux-kernel@vger.kernel.org \ --cc=nicolas.ferre@microchip.com \ --cc=robh+dt@kernel.org \ --subject='Re: [PATCH] ARM: dts: lan966x: fix sys_clk frequency' \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: link
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.