* [PATCH v2 0/3] arm64: dts: add corstone1000 device tree
@ 2022-03-29 21:35 ` Rui Miguel Silva
0 siblings, 0 replies; 16+ messages in thread
From: Rui Miguel Silva @ 2022-03-29 21:35 UTC (permalink / raw)
To: Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-kernel, devicetree, Rui Miguel Silva
Add device tree and correspondent binding for ARM corstone1000
[0] platform for FVP (Fixed Virtual Platform) and FPGA MPS3
prototyping board implementation of this system.
Cheers,
Rui
v1 [1] ->v2:
Rob Herring:
- change license to dual
- distinguish cpu entry for fvp and mps3
- mmio nodes in simple-bus
- refactor mhu entries
- add secure-status to secure world only accessible mhu
- add smsc,lan91c111 binding patch to avoid dtbs_check
warnings
Marc Zyngier:
- fixed SPI cpu mask invalid entries
- reduce the mask to the existing cpu count (4->1)
- change one interrupt to symbolic enconding
0: https://documentation-service.arm.com/static/619e02b1f45f0b1fbf3a8f16
1: https://lore.kernel.org/linux-devicetree/20220325133655.4177977-1-rui.silva@linaro.org/
Rui Miguel Silva (3):
dt-bindings: net: smsc,lan91c111 convert to schema
dt-bindings: arm: add corstone1000 platform
arm64: dts: arm: add corstone1000 device tree
.../bindings/arm/arm,corstone1000.yaml | 45 +++++
.../bindings/net/smsc,lan91c111.yaml | 59 +++++++
arch/arm64/boot/dts/arm/Makefile | 1 +
arch/arm64/boot/dts/arm/corstone1000-fvp.dts | 27 +++
arch/arm64/boot/dts/arm/corstone1000-mps3.dts | 36 ++++
arch/arm64/boot/dts/arm/corstone1000.dtsi | 161 ++++++++++++++++++
6 files changed, 329 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/arm,corstone1000.yaml
create mode 100644 Documentation/devicetree/bindings/net/smsc,lan91c111.yaml
create mode 100644 arch/arm64/boot/dts/arm/corstone1000-fvp.dts
create mode 100644 arch/arm64/boot/dts/arm/corstone1000-mps3.dts
create mode 100644 arch/arm64/boot/dts/arm/corstone1000.dtsi
--
2.35.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 0/3] arm64: dts: add corstone1000 device tree
@ 2022-03-29 21:35 ` Rui Miguel Silva
0 siblings, 0 replies; 16+ messages in thread
From: Rui Miguel Silva @ 2022-03-29 21:35 UTC (permalink / raw)
To: Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-kernel, devicetree, Rui Miguel Silva
Add device tree and correspondent binding for ARM corstone1000
[0] platform for FVP (Fixed Virtual Platform) and FPGA MPS3
prototyping board implementation of this system.
Cheers,
Rui
v1 [1] ->v2:
Rob Herring:
- change license to dual
- distinguish cpu entry for fvp and mps3
- mmio nodes in simple-bus
- refactor mhu entries
- add secure-status to secure world only accessible mhu
- add smsc,lan91c111 binding patch to avoid dtbs_check
warnings
Marc Zyngier:
- fixed SPI cpu mask invalid entries
- reduce the mask to the existing cpu count (4->1)
- change one interrupt to symbolic enconding
0: https://documentation-service.arm.com/static/619e02b1f45f0b1fbf3a8f16
1: https://lore.kernel.org/linux-devicetree/20220325133655.4177977-1-rui.silva@linaro.org/
Rui Miguel Silva (3):
dt-bindings: net: smsc,lan91c111 convert to schema
dt-bindings: arm: add corstone1000 platform
arm64: dts: arm: add corstone1000 device tree
.../bindings/arm/arm,corstone1000.yaml | 45 +++++
.../bindings/net/smsc,lan91c111.yaml | 59 +++++++
arch/arm64/boot/dts/arm/Makefile | 1 +
arch/arm64/boot/dts/arm/corstone1000-fvp.dts | 27 +++
arch/arm64/boot/dts/arm/corstone1000-mps3.dts | 36 ++++
arch/arm64/boot/dts/arm/corstone1000.dtsi | 161 ++++++++++++++++++
6 files changed, 329 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/arm,corstone1000.yaml
create mode 100644 Documentation/devicetree/bindings/net/smsc,lan91c111.yaml
create mode 100644 arch/arm64/boot/dts/arm/corstone1000-fvp.dts
create mode 100644 arch/arm64/boot/dts/arm/corstone1000-mps3.dts
create mode 100644 arch/arm64/boot/dts/arm/corstone1000.dtsi
--
2.35.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 1/3] dt-bindings: net: smsc,lan91c111 convert to schema
2022-03-29 21:35 ` Rui Miguel Silva
@ 2022-03-29 21:35 ` Rui Miguel Silva
-1 siblings, 0 replies; 16+ messages in thread
From: Rui Miguel Silva @ 2022-03-29 21:35 UTC (permalink / raw)
To: Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-kernel, devicetree, Rui Miguel Silva
Convert the smsc lan91c9x and lan91c1xx controller device tree
bindings documentation to json-schema.
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
---
.../bindings/net/smsc,lan91c111.yaml | 59 +++++++++++++++++++
1 file changed, 59 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/smsc,lan91c111.yaml
diff --git a/Documentation/devicetree/bindings/net/smsc,lan91c111.yaml b/Documentation/devicetree/bindings/net/smsc,lan91c111.yaml
new file mode 100644
index 000000000000..5976f4fa4a80
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/smsc,lan91c111.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/smsc,lan91c111.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Smart Mixed-Signal Connectivity (SMSC) LAN91C9x/91C1xx Controller
+
+maintainers:
+ - Nicolas Pitre <nico@fluxnic.net>
+
+allOf:
+ - $ref: ethernet-controller.yaml#
+
+properties:
+ compatible:
+ const: smsc,lan91c111
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ reg-shift: true
+
+ reg-io-width:
+ enum: [ 1, 2, 4 ]
+ default: 2
+
+ reset-gpios:
+ description: GPIO connected to control RESET pin
+ maxItems: 1
+
+ power-gpios:
+ description: GPIO connect to control PWRDEWN pin
+ maxItems: 1
+
+ pxa-u16-align4:
+ description: put in place the workaround the force all u16 writes to be
+ 32 bits aligned
+ type: boolean
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: true
+
+examples:
+ - |
+ ethernet@4010000 {
+ compatible = "smsc,lan91c111";
+ reg = <0x40100000 0x10000>;
+ phy-mode = "mii";
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <2>;
+ };
--
2.35.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2 1/3] dt-bindings: net: smsc,lan91c111 convert to schema
@ 2022-03-29 21:35 ` Rui Miguel Silva
0 siblings, 0 replies; 16+ messages in thread
From: Rui Miguel Silva @ 2022-03-29 21:35 UTC (permalink / raw)
To: Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-kernel, devicetree, Rui Miguel Silva
Convert the smsc lan91c9x and lan91c1xx controller device tree
bindings documentation to json-schema.
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
---
.../bindings/net/smsc,lan91c111.yaml | 59 +++++++++++++++++++
1 file changed, 59 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/smsc,lan91c111.yaml
diff --git a/Documentation/devicetree/bindings/net/smsc,lan91c111.yaml b/Documentation/devicetree/bindings/net/smsc,lan91c111.yaml
new file mode 100644
index 000000000000..5976f4fa4a80
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/smsc,lan91c111.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/smsc,lan91c111.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Smart Mixed-Signal Connectivity (SMSC) LAN91C9x/91C1xx Controller
+
+maintainers:
+ - Nicolas Pitre <nico@fluxnic.net>
+
+allOf:
+ - $ref: ethernet-controller.yaml#
+
+properties:
+ compatible:
+ const: smsc,lan91c111
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ reg-shift: true
+
+ reg-io-width:
+ enum: [ 1, 2, 4 ]
+ default: 2
+
+ reset-gpios:
+ description: GPIO connected to control RESET pin
+ maxItems: 1
+
+ power-gpios:
+ description: GPIO connect to control PWRDEWN pin
+ maxItems: 1
+
+ pxa-u16-align4:
+ description: put in place the workaround the force all u16 writes to be
+ 32 bits aligned
+ type: boolean
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: true
+
+examples:
+ - |
+ ethernet@4010000 {
+ compatible = "smsc,lan91c111";
+ reg = <0x40100000 0x10000>;
+ phy-mode = "mii";
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <2>;
+ };
--
2.35.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2 2/3] dt-bindings: arm: add corstone1000 platform
2022-03-29 21:35 ` Rui Miguel Silva
@ 2022-03-29 21:35 ` Rui Miguel Silva
-1 siblings, 0 replies; 16+ messages in thread
From: Rui Miguel Silva @ 2022-03-29 21:35 UTC (permalink / raw)
To: Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-kernel, devicetree, Rui Miguel Silva
Add bindings to describe the FPGA in a prototyping board
(MPS3) implementation and the Fixed Virtual Platform
implementation of the ARM Corstone1000 platform.
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
---
.../bindings/arm/arm,corstone1000.yaml | 45 +++++++++++++++++++
1 file changed, 45 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/arm,corstone1000.yaml
diff --git a/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml b/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml
new file mode 100644
index 000000000000..a77f88223801
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/arm,corstone1000.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Corstone1000 Device Tree Bindings
+
+maintainers:
+ - Vishnu Banavath <vishnu.banavath@arm.com>
+ - Rui Miguel Silva <rui.silva@linaro.org>
+
+description: |+
+ ARM's Corstone1000 includes pre-verified Corstone SSE-710 subsystem that
+ provides a flexible compute architecture that combines Cortex‑A and Cortex‑M
+ processors.
+
+ Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion
+ systems for M-Class (or other) processors for adding sensors, connectivity,
+ video, audio and machine learning at the edge System and security IPs to build
+ a secure SoC for a range of rich IoT applications, for example gateways, smart
+ cameras and embedded systems.
+
+ Integrated Secure Enclave providing hardware Root of Trust and supporting
+ seamless integration of the optional CryptoCell™-312 cryptographic
+ accelerator.
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - description: Corstone1000 MPS3 it has 1 Cortex-A35 CPU core in a FPGA
+ implementation of the Corstone1000 in the MPS3 prototyping board. See
+ ARM document DAI0550.
+ items:
+ - const: arm,corstone1000-mps3
+ - description: Corstone1000 FVP is the Fixed Virtual Platform
+ implementation of this system. See ARM ecosystems FVP's.
+ items:
+ - const: arm,corstone1000-fvp
+
+additionalProperties: true
+
+...
--
2.35.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2 2/3] dt-bindings: arm: add corstone1000 platform
@ 2022-03-29 21:35 ` Rui Miguel Silva
0 siblings, 0 replies; 16+ messages in thread
From: Rui Miguel Silva @ 2022-03-29 21:35 UTC (permalink / raw)
To: Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-kernel, devicetree, Rui Miguel Silva
Add bindings to describe the FPGA in a prototyping board
(MPS3) implementation and the Fixed Virtual Platform
implementation of the ARM Corstone1000 platform.
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
---
.../bindings/arm/arm,corstone1000.yaml | 45 +++++++++++++++++++
1 file changed, 45 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/arm,corstone1000.yaml
diff --git a/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml b/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml
new file mode 100644
index 000000000000..a77f88223801
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/arm,corstone1000.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Corstone1000 Device Tree Bindings
+
+maintainers:
+ - Vishnu Banavath <vishnu.banavath@arm.com>
+ - Rui Miguel Silva <rui.silva@linaro.org>
+
+description: |+
+ ARM's Corstone1000 includes pre-verified Corstone SSE-710 subsystem that
+ provides a flexible compute architecture that combines Cortex‑A and Cortex‑M
+ processors.
+
+ Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion
+ systems for M-Class (or other) processors for adding sensors, connectivity,
+ video, audio and machine learning at the edge System and security IPs to build
+ a secure SoC for a range of rich IoT applications, for example gateways, smart
+ cameras and embedded systems.
+
+ Integrated Secure Enclave providing hardware Root of Trust and supporting
+ seamless integration of the optional CryptoCell™-312 cryptographic
+ accelerator.
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - description: Corstone1000 MPS3 it has 1 Cortex-A35 CPU core in a FPGA
+ implementation of the Corstone1000 in the MPS3 prototyping board. See
+ ARM document DAI0550.
+ items:
+ - const: arm,corstone1000-mps3
+ - description: Corstone1000 FVP is the Fixed Virtual Platform
+ implementation of this system. See ARM ecosystems FVP's.
+ items:
+ - const: arm,corstone1000-fvp
+
+additionalProperties: true
+
+...
--
2.35.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2 3/3] arm64: dts: arm: add corstone1000 device tree
2022-03-29 21:35 ` Rui Miguel Silva
@ 2022-03-29 21:35 ` Rui Miguel Silva
-1 siblings, 0 replies; 16+ messages in thread
From: Rui Miguel Silva @ 2022-03-29 21:35 UTC (permalink / raw)
To: Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-kernel, devicetree, Rui Miguel Silva
Corstone1000 is a platform from arm, which includes pre
verified Corstone SSE710 sub-system that combines Cortex-A and
Cortex-M processors [0].
These device trees contains the necessary bits to support the
Corstone 1000 FVP (Fixed Virtual Platform) [1] and the
FPGA MPS3 board Cortex-A35 implementation at Cortex-A35 host
side of this platform. [2]
0: https://documentation-service.arm.com/static/619e02b1f45f0b1fbf3a8f16
1: https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps
2: https://documentation-service.arm.com/static/61f3f4d7fa8173727a1b71bf
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
---
arch/arm64/boot/dts/arm/Makefile | 1 +
arch/arm64/boot/dts/arm/corstone1000-fvp.dts | 27 +++
arch/arm64/boot/dts/arm/corstone1000-mps3.dts | 36 ++++
arch/arm64/boot/dts/arm/corstone1000.dtsi | 161 ++++++++++++++++++
4 files changed, 225 insertions(+)
create mode 100644 arch/arm64/boot/dts/arm/corstone1000-fvp.dts
create mode 100644 arch/arm64/boot/dts/arm/corstone1000-mps3.dts
create mode 100644 arch/arm64/boot/dts/arm/corstone1000.dtsi
diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile
index 4382b73baef5..d908e96d7ddc 100644
--- a/arch/arm64/boot/dts/arm/Makefile
+++ b/arch/arm64/boot/dts/arm/Makefile
@@ -6,3 +6,4 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb juno-r2.dtb juno-scmi.dtb ju
dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb
+dtb-$(CONFIG_ARCH_VEXPRESS) += corstone1000-fvp.dtb corstone1000-mps3.dtb
diff --git a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts
new file mode 100644
index 000000000000..dea8b5f4d68a
--- /dev/null
+++ b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2022, Linaro Limited. All rights reserved.
+ *
+ */
+
+/dts-v1/;
+
+#include "corstone1000.dtsi"
+
+/ {
+ model = "ARM Corstone1000 FVP (Fixed Virtual Platform)";
+ compatible = "arm,corstone1000-fvp";
+
+ smsc: ethernet@4010000 {
+ compatible = "smsc,lan91c111";
+ reg = <0x40100000 0x10000>;
+ phy-mode = "mii";
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <2>;
+ };
+};
+
+&cpu {
+ compatible = "arm,armv8";
+};
diff --git a/arch/arm64/boot/dts/arm/corstone1000-mps3.dts b/arch/arm64/boot/dts/arm/corstone1000-mps3.dts
new file mode 100644
index 000000000000..9989586db70e
--- /dev/null
+++ b/arch/arm64/boot/dts/arm/corstone1000-mps3.dts
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2022, Linaro Limited. All rights reserved.
+ *
+ */
+
+/dts-v1/;
+
+#include "corstone1000.dtsi"
+
+/ {
+ model = "ARM Corstone1000 FPGA MPS3 board";
+ compatible = "arm,corstone1000-mps3";
+
+ smsc: ethernet@4010000 {
+ compatible = "smsc,lan9220", "smsc,lan9115";
+ reg = <0x40100000 0x10000>;
+ phy-mode = "mii";
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <2>;
+ smsc,irq-push-pull;
+ };
+
+ usb_host: usb@40200000 {
+ compatible = "nxp,usb-isp1763";
+ reg = <0x40200000 0x100000>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ bus-width = <16>;
+ dr_mode = "host";
+ };
+};
+
+&cpu {
+ compatible = "arm,cortex-a35";
+};
diff --git a/arch/arm64/boot/dts/arm/corstone1000.dtsi b/arch/arm64/boot/dts/arm/corstone1000.dtsi
new file mode 100644
index 000000000000..194d959de828
--- /dev/null
+++ b/arch/arm64/boot/dts/arm/corstone1000.dtsi
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2022, Linaro Limited. All rights reserved.
+ *
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu: cpu@0 {
+ device_type = "cpu";
+ reg = <0>;
+ next-level-cache = <&L2_0>;
+ };
+ };
+
+ memory@88200000 {
+ device_type = "memory";
+ reg = <0x88200000 0x77e00000>;
+ };
+
+ gic: interrupt-controller@1c000000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x1c010000 0x1000>,
+ <0x1c02f000 0x2000>,
+ <0x1c04f000 0x1000>,
+ <0x1c06f000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ };
+
+ refclk100mhz: refclk100mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "apb_pclk";
+ };
+
+ smbclk: refclk24mhzx2 {
+ /* Reference 24MHz clock x 2 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ clock-output-names = "smclk";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ uartclk: uartclk {
+ /* UART clock - 50MHz */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ clock-output-names = "uartclk";
+ };
+
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&gic>;
+ ranges;
+
+ timer@1a220000 {
+ compatible = "arm,armv7-timer-mem";
+ reg = <0x1a220000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clock-frequency = <50000000>;
+ ranges;
+
+ frame@1a230000 {
+ frame-number = <0>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x1a230000 0x1000>;
+ };
+ };
+
+ uart0: serial@1a510000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x1a510000 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&uartclk>, <&refclk100mhz>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+
+ uart1: serial@1a520000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x1a520000 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&uartclk>, <&refclk100mhz>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+
+ mhu_hse1: mailbox@1b820000 {
+ compatible = "arm,mhuv2-tx", "arm,primecell";
+ reg = <0x1b820000 0x1000>;
+ clocks = <&refclk100mhz>;
+ clock-names = "apb_pclk";
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ arm,mhuv2-protocols = <0 0>;
+ secure-status = "okay"; /* secure-world-only */
+ status = "disabled";
+ };
+
+ mhu_seh1: mailbox@1b830000 {
+ compatible = "arm,mhuv2-rx", "arm,primecell";
+ reg = <0x1b830000 0x1000>;
+ clocks = <&refclk100mhz>;
+ clock-names = "apb_pclk";
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ arm,mhuv2-protocols = <0 0>;
+ secure-status = "okay"; /* secure-world-only */
+ status = "disabled";
+ };
+ };
+};
--
2.35.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2 3/3] arm64: dts: arm: add corstone1000 device tree
@ 2022-03-29 21:35 ` Rui Miguel Silva
0 siblings, 0 replies; 16+ messages in thread
From: Rui Miguel Silva @ 2022-03-29 21:35 UTC (permalink / raw)
To: Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-kernel, devicetree, Rui Miguel Silva
Corstone1000 is a platform from arm, which includes pre
verified Corstone SSE710 sub-system that combines Cortex-A and
Cortex-M processors [0].
These device trees contains the necessary bits to support the
Corstone 1000 FVP (Fixed Virtual Platform) [1] and the
FPGA MPS3 board Cortex-A35 implementation at Cortex-A35 host
side of this platform. [2]
0: https://documentation-service.arm.com/static/619e02b1f45f0b1fbf3a8f16
1: https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps
2: https://documentation-service.arm.com/static/61f3f4d7fa8173727a1b71bf
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
---
arch/arm64/boot/dts/arm/Makefile | 1 +
arch/arm64/boot/dts/arm/corstone1000-fvp.dts | 27 +++
arch/arm64/boot/dts/arm/corstone1000-mps3.dts | 36 ++++
arch/arm64/boot/dts/arm/corstone1000.dtsi | 161 ++++++++++++++++++
4 files changed, 225 insertions(+)
create mode 100644 arch/arm64/boot/dts/arm/corstone1000-fvp.dts
create mode 100644 arch/arm64/boot/dts/arm/corstone1000-mps3.dts
create mode 100644 arch/arm64/boot/dts/arm/corstone1000.dtsi
diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile
index 4382b73baef5..d908e96d7ddc 100644
--- a/arch/arm64/boot/dts/arm/Makefile
+++ b/arch/arm64/boot/dts/arm/Makefile
@@ -6,3 +6,4 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb juno-r2.dtb juno-scmi.dtb ju
dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb
+dtb-$(CONFIG_ARCH_VEXPRESS) += corstone1000-fvp.dtb corstone1000-mps3.dtb
diff --git a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts
new file mode 100644
index 000000000000..dea8b5f4d68a
--- /dev/null
+++ b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2022, Linaro Limited. All rights reserved.
+ *
+ */
+
+/dts-v1/;
+
+#include "corstone1000.dtsi"
+
+/ {
+ model = "ARM Corstone1000 FVP (Fixed Virtual Platform)";
+ compatible = "arm,corstone1000-fvp";
+
+ smsc: ethernet@4010000 {
+ compatible = "smsc,lan91c111";
+ reg = <0x40100000 0x10000>;
+ phy-mode = "mii";
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <2>;
+ };
+};
+
+&cpu {
+ compatible = "arm,armv8";
+};
diff --git a/arch/arm64/boot/dts/arm/corstone1000-mps3.dts b/arch/arm64/boot/dts/arm/corstone1000-mps3.dts
new file mode 100644
index 000000000000..9989586db70e
--- /dev/null
+++ b/arch/arm64/boot/dts/arm/corstone1000-mps3.dts
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2022, Linaro Limited. All rights reserved.
+ *
+ */
+
+/dts-v1/;
+
+#include "corstone1000.dtsi"
+
+/ {
+ model = "ARM Corstone1000 FPGA MPS3 board";
+ compatible = "arm,corstone1000-mps3";
+
+ smsc: ethernet@4010000 {
+ compatible = "smsc,lan9220", "smsc,lan9115";
+ reg = <0x40100000 0x10000>;
+ phy-mode = "mii";
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <2>;
+ smsc,irq-push-pull;
+ };
+
+ usb_host: usb@40200000 {
+ compatible = "nxp,usb-isp1763";
+ reg = <0x40200000 0x100000>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ bus-width = <16>;
+ dr_mode = "host";
+ };
+};
+
+&cpu {
+ compatible = "arm,cortex-a35";
+};
diff --git a/arch/arm64/boot/dts/arm/corstone1000.dtsi b/arch/arm64/boot/dts/arm/corstone1000.dtsi
new file mode 100644
index 000000000000..194d959de828
--- /dev/null
+++ b/arch/arm64/boot/dts/arm/corstone1000.dtsi
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2022, Linaro Limited. All rights reserved.
+ *
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu: cpu@0 {
+ device_type = "cpu";
+ reg = <0>;
+ next-level-cache = <&L2_0>;
+ };
+ };
+
+ memory@88200000 {
+ device_type = "memory";
+ reg = <0x88200000 0x77e00000>;
+ };
+
+ gic: interrupt-controller@1c000000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x1c010000 0x1000>,
+ <0x1c02f000 0x2000>,
+ <0x1c04f000 0x1000>,
+ <0x1c06f000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ };
+
+ refclk100mhz: refclk100mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "apb_pclk";
+ };
+
+ smbclk: refclk24mhzx2 {
+ /* Reference 24MHz clock x 2 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ clock-output-names = "smclk";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ uartclk: uartclk {
+ /* UART clock - 50MHz */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ clock-output-names = "uartclk";
+ };
+
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&gic>;
+ ranges;
+
+ timer@1a220000 {
+ compatible = "arm,armv7-timer-mem";
+ reg = <0x1a220000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clock-frequency = <50000000>;
+ ranges;
+
+ frame@1a230000 {
+ frame-number = <0>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x1a230000 0x1000>;
+ };
+ };
+
+ uart0: serial@1a510000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x1a510000 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&uartclk>, <&refclk100mhz>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+
+ uart1: serial@1a520000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x1a520000 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&uartclk>, <&refclk100mhz>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+
+ mhu_hse1: mailbox@1b820000 {
+ compatible = "arm,mhuv2-tx", "arm,primecell";
+ reg = <0x1b820000 0x1000>;
+ clocks = <&refclk100mhz>;
+ clock-names = "apb_pclk";
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ arm,mhuv2-protocols = <0 0>;
+ secure-status = "okay"; /* secure-world-only */
+ status = "disabled";
+ };
+
+ mhu_seh1: mailbox@1b830000 {
+ compatible = "arm,mhuv2-rx", "arm,primecell";
+ reg = <0x1b830000 0x1000>;
+ clocks = <&refclk100mhz>;
+ clock-names = "apb_pclk";
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ arm,mhuv2-protocols = <0 0>;
+ secure-status = "okay"; /* secure-world-only */
+ status = "disabled";
+ };
+ };
+};
--
2.35.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: net: smsc,lan91c111 convert to schema
2022-03-29 21:35 ` Rui Miguel Silva
@ 2022-03-29 22:40 ` Andrew Lunn
-1 siblings, 0 replies; 16+ messages in thread
From: Andrew Lunn @ 2022-03-29 22:40 UTC (permalink / raw)
To: Rui Miguel Silva
Cc: Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Rob Herring,
Krzysztof Kozlowski, linux-arm-kernel, devicetree
On Tue, Mar 29, 2022 at 10:35:17PM +0100, Rui Miguel Silva wrote:
> Convert the smsc lan91c9x and lan91c1xx controller device tree
> bindings documentation to json-schema.
>
> Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
> ---
> .../bindings/net/smsc,lan91c111.yaml | 59 +++++++++++++++++++
> 1 file changed, 59 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/net/smsc,lan91c111.yaml
Hi Rui
It is normal to also remove the contents of the .txt file and add a
single line that points to the .yaml file.
Andrew
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: net: smsc, lan91c111 convert to schema
@ 2022-03-29 22:40 ` Andrew Lunn
0 siblings, 0 replies; 16+ messages in thread
From: Andrew Lunn @ 2022-03-29 22:40 UTC (permalink / raw)
To: Rui Miguel Silva
Cc: Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Rob Herring,
Krzysztof Kozlowski, linux-arm-kernel, devicetree
On Tue, Mar 29, 2022 at 10:35:17PM +0100, Rui Miguel Silva wrote:
> Convert the smsc lan91c9x and lan91c1xx controller device tree
> bindings documentation to json-schema.
>
> Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
> ---
> .../bindings/net/smsc,lan91c111.yaml | 59 +++++++++++++++++++
> 1 file changed, 59 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/net/smsc,lan91c111.yaml
Hi Rui
It is normal to also remove the contents of the .txt file and add a
single line that points to the .yaml file.
Andrew
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: net: smsc,lan91c111 convert to schema
2022-03-29 21:35 ` Rui Miguel Silva
@ 2022-03-29 23:39 ` Rob Herring
-1 siblings, 0 replies; 16+ messages in thread
From: Rob Herring @ 2022-03-29 23:39 UTC (permalink / raw)
To: Rui Miguel Silva
Cc: Liviu Dudau, devicetree, linux-arm-kernel, Sudeep Holla,
Lorenzo Pieralisi, Rob Herring, Krzysztof Kozlowski
On Tue, 29 Mar 2022 22:35:17 +0100, Rui Miguel Silva wrote:
> Convert the smsc lan91c9x and lan91c1xx controller device tree
> bindings documentation to json-schema.
>
> Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
> ---
> .../bindings/net/smsc,lan91c111.yaml | 59 +++++++++++++++++++
> 1 file changed, 59 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/net/smsc,lan91c111.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Error: Documentation/devicetree/bindings/net/smsc,lan91c111.example.dts:27.29-30 syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:378: Documentation/devicetree/bindings/net/smsc,lan91c111.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1398: dt_binding_check] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1610868
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: net: smsc, lan91c111 convert to schema
@ 2022-03-29 23:39 ` Rob Herring
0 siblings, 0 replies; 16+ messages in thread
From: Rob Herring @ 2022-03-29 23:39 UTC (permalink / raw)
To: Rui Miguel Silva
Cc: Liviu Dudau, devicetree, linux-arm-kernel, Sudeep Holla,
Lorenzo Pieralisi, Rob Herring, Krzysztof Kozlowski
On Tue, 29 Mar 2022 22:35:17 +0100, Rui Miguel Silva wrote:
> Convert the smsc lan91c9x and lan91c1xx controller device tree
> bindings documentation to json-schema.
>
> Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
> ---
> .../bindings/net/smsc,lan91c111.yaml | 59 +++++++++++++++++++
> 1 file changed, 59 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/net/smsc,lan91c111.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Error: Documentation/devicetree/bindings/net/smsc,lan91c111.example.dts:27.29-30 syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:378: Documentation/devicetree/bindings/net/smsc,lan91c111.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1398: dt_binding_check] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1610868
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: net: smsc,lan91c111 convert to schema
2022-03-29 21:35 ` Rui Miguel Silva
@ 2022-03-29 23:43 ` Rob Herring
-1 siblings, 0 replies; 16+ messages in thread
From: Rob Herring @ 2022-03-29 23:43 UTC (permalink / raw)
To: Rui Miguel Silva
Cc: Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi,
Krzysztof Kozlowski, linux-arm-kernel, devicetree
On Tue, Mar 29, 2022 at 4:35 PM Rui Miguel Silva <rui.silva@linaro.org> wrote:
>
> Convert the smsc lan91c9x and lan91c1xx controller device tree
> bindings documentation to json-schema.
>
> Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
> ---
> .../bindings/net/smsc,lan91c111.yaml | 59 +++++++++++++++++++
> 1 file changed, 59 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/net/smsc,lan91c111.yaml
>
> diff --git a/Documentation/devicetree/bindings/net/smsc,lan91c111.yaml b/Documentation/devicetree/bindings/net/smsc,lan91c111.yaml
> new file mode 100644
> index 000000000000..5976f4fa4a80
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/smsc,lan91c111.yaml
> @@ -0,0 +1,59 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/net/smsc,lan91c111.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Smart Mixed-Signal Connectivity (SMSC) LAN91C9x/91C1xx Controller
> +
> +maintainers:
> + - Nicolas Pitre <nico@fluxnic.net>
> +
> +allOf:
> + - $ref: ethernet-controller.yaml#
> +
> +properties:
> + compatible:
> + const: smsc,lan91c111
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + reg-shift: true
> +
> + reg-io-width:
> + enum: [ 1, 2, 4 ]
> + default: 2
> +
> + reset-gpios:
> + description: GPIO connected to control RESET pin
> + maxItems: 1
> +
> + power-gpios:
> + description: GPIO connect to control PWRDEWN pin
> + maxItems: 1
> +
> + pxa-u16-align4:
> + description: put in place the workaround the force all u16 writes to be
> + 32 bits aligned
> + type: boolean
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> +
> +additionalProperties: true
This is only allowed on incomplete, common schemas. Instead use:
unevaluatedProperties: false
As that allows for properties defined in ethernet-controller.yaml.
> +
> +examples:
> + - |
> + ethernet@4010000 {
> + compatible = "smsc,lan91c111";
> + reg = <0x40100000 0x10000>;
> + phy-mode = "mii";
> + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
> + reg-io-width = <2>;
> + };
> --
> 2.35.1
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: net: smsc, lan91c111 convert to schema
@ 2022-03-29 23:43 ` Rob Herring
0 siblings, 0 replies; 16+ messages in thread
From: Rob Herring @ 2022-03-29 23:43 UTC (permalink / raw)
To: Rui Miguel Silva
Cc: Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi,
Krzysztof Kozlowski, linux-arm-kernel, devicetree
On Tue, Mar 29, 2022 at 4:35 PM Rui Miguel Silva <rui.silva@linaro.org> wrote:
>
> Convert the smsc lan91c9x and lan91c1xx controller device tree
> bindings documentation to json-schema.
>
> Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
> ---
> .../bindings/net/smsc,lan91c111.yaml | 59 +++++++++++++++++++
> 1 file changed, 59 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/net/smsc,lan91c111.yaml
>
> diff --git a/Documentation/devicetree/bindings/net/smsc,lan91c111.yaml b/Documentation/devicetree/bindings/net/smsc,lan91c111.yaml
> new file mode 100644
> index 000000000000..5976f4fa4a80
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/smsc,lan91c111.yaml
> @@ -0,0 +1,59 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/net/smsc,lan91c111.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Smart Mixed-Signal Connectivity (SMSC) LAN91C9x/91C1xx Controller
> +
> +maintainers:
> + - Nicolas Pitre <nico@fluxnic.net>
> +
> +allOf:
> + - $ref: ethernet-controller.yaml#
> +
> +properties:
> + compatible:
> + const: smsc,lan91c111
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + reg-shift: true
> +
> + reg-io-width:
> + enum: [ 1, 2, 4 ]
> + default: 2
> +
> + reset-gpios:
> + description: GPIO connected to control RESET pin
> + maxItems: 1
> +
> + power-gpios:
> + description: GPIO connect to control PWRDEWN pin
> + maxItems: 1
> +
> + pxa-u16-align4:
> + description: put in place the workaround the force all u16 writes to be
> + 32 bits aligned
> + type: boolean
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> +
> +additionalProperties: true
This is only allowed on incomplete, common schemas. Instead use:
unevaluatedProperties: false
As that allows for properties defined in ethernet-controller.yaml.
> +
> +examples:
> + - |
> + ethernet@4010000 {
> + compatible = "smsc,lan91c111";
> + reg = <0x40100000 0x10000>;
> + phy-mode = "mii";
> + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
> + reg-io-width = <2>;
> + };
> --
> 2.35.1
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: net: smsc,lan91c111 convert to schema
2022-03-29 22:40 ` [PATCH v2 1/3] dt-bindings: net: smsc, lan91c111 " Andrew Lunn
@ 2022-03-30 13:01 ` Rui Miguel Silva
-1 siblings, 0 replies; 16+ messages in thread
From: Rui Miguel Silva @ 2022-03-30 13:01 UTC (permalink / raw)
To: Andrew Lunn
Cc: Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Rob Herring,
Krzysztof Kozlowski, linux-arm-kernel, devicetree
Hi Andrew,
Many thanks for the review.
On Wed, Mar 30, 2022 at 12:40:13AM +0200, Andrew Lunn wrote:
> On Tue, Mar 29, 2022 at 10:35:17PM +0100, Rui Miguel Silva wrote:
> > Convert the smsc lan91c9x and lan91c1xx controller device tree
> > bindings documentation to json-schema.
> >
> > Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
> > ---
> > .../bindings/net/smsc,lan91c111.yaml | 59 +++++++++++++++++++
> > 1 file changed, 59 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/net/smsc,lan91c111.yaml
>
> Hi Rui
>
> It is normal to also remove the contents of the .txt file and add a
> single line that points to the .yaml file.
yeah, I will delete txt file instead, I forgot to do it in this
commit though.
Cheers,
Rui
>
> Andrew
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: net: smsc, lan91c111 convert to schema
@ 2022-03-30 13:01 ` Rui Miguel Silva
0 siblings, 0 replies; 16+ messages in thread
From: Rui Miguel Silva @ 2022-03-30 13:01 UTC (permalink / raw)
To: Andrew Lunn
Cc: Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Rob Herring,
Krzysztof Kozlowski, linux-arm-kernel, devicetree
Hi Andrew,
Many thanks for the review.
On Wed, Mar 30, 2022 at 12:40:13AM +0200, Andrew Lunn wrote:
> On Tue, Mar 29, 2022 at 10:35:17PM +0100, Rui Miguel Silva wrote:
> > Convert the smsc lan91c9x and lan91c1xx controller device tree
> > bindings documentation to json-schema.
> >
> > Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
> > ---
> > .../bindings/net/smsc,lan91c111.yaml | 59 +++++++++++++++++++
> > 1 file changed, 59 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/net/smsc,lan91c111.yaml
>
> Hi Rui
>
> It is normal to also remove the contents of the .txt file and add a
> single line that points to the .yaml file.
yeah, I will delete txt file instead, I forgot to do it in this
commit though.
Cheers,
Rui
>
> Andrew
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2022-03-30 13:03 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-03-29 21:35 [PATCH v2 0/3] arm64: dts: add corstone1000 device tree Rui Miguel Silva
2022-03-29 21:35 ` Rui Miguel Silva
2022-03-29 21:35 ` [PATCH v2 1/3] dt-bindings: net: smsc,lan91c111 convert to schema Rui Miguel Silva
2022-03-29 21:35 ` Rui Miguel Silva
2022-03-29 22:40 ` Andrew Lunn
2022-03-29 22:40 ` [PATCH v2 1/3] dt-bindings: net: smsc, lan91c111 " Andrew Lunn
2022-03-30 13:01 ` [PATCH v2 1/3] dt-bindings: net: smsc,lan91c111 " Rui Miguel Silva
2022-03-30 13:01 ` [PATCH v2 1/3] dt-bindings: net: smsc, lan91c111 " Rui Miguel Silva
2022-03-29 23:39 ` [PATCH v2 1/3] dt-bindings: net: smsc,lan91c111 " Rob Herring
2022-03-29 23:39 ` [PATCH v2 1/3] dt-bindings: net: smsc, lan91c111 " Rob Herring
2022-03-29 23:43 ` [PATCH v2 1/3] dt-bindings: net: smsc,lan91c111 " Rob Herring
2022-03-29 23:43 ` [PATCH v2 1/3] dt-bindings: net: smsc, lan91c111 " Rob Herring
2022-03-29 21:35 ` [PATCH v2 2/3] dt-bindings: arm: add corstone1000 platform Rui Miguel Silva
2022-03-29 21:35 ` Rui Miguel Silva
2022-03-29 21:35 ` [PATCH v2 3/3] arm64: dts: arm: add corstone1000 device tree Rui Miguel Silva
2022-03-29 21:35 ` Rui Miguel Silva
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