* [Intel-gfx] [PATCH v4 1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL
@ 2022-03-29 22:30 José Roberto de Souza
2022-03-29 22:31 ` [Intel-gfx] [PATCH v4 2/4] drm/i915/display/adlp: Adjust MBUS DBOX BW and B credits José Roberto de Souza
` (8 more replies)
0 siblings, 9 replies; 12+ messages in thread
From: José Roberto de Souza @ 2022-03-29 22:30 UTC (permalink / raw)
To: intel-gfx
MBUS_DBOX_B2B_TRANSACTIONS_MAX, MBUS_DBOX_B2B_TRANSACTIONS_DELAY and
MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN were being programmed with
zeros while specification has different default values for this
registers in display 12 and newer.
While at it also converting all MBUS_DBOX macros to use REG_* macros.
BSpec: 50343
BSpec: 20231
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 13 +++++++---
drivers/gpu/drm/i915/i915_reg.h | 26 ++++++++++++--------
2 files changed, 26 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 28bfb73ae6471..234f363aad651 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1829,13 +1829,20 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc, bool joined_mbus)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
- u32 val;
+ u32 val = 0;
+
+ if (DISPLAY_VER(dev_priv) >= 12) {
+ val |= MBUS_DBOX_B2B_TRANSACTIONS_MAX(16);
+ val |= MBUS_DBOX_B2B_TRANSACTIONS_DELAY(1);
+ val |= MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN;
+ }
/* Wa_22010947358:adl-p */
if (IS_ALDERLAKE_P(dev_priv))
- val = joined_mbus ? MBUS_DBOX_A_CREDIT(6) : MBUS_DBOX_A_CREDIT(4);
+ val |= joined_mbus ? MBUS_DBOX_A_CREDIT(6) :
+ MBUS_DBOX_A_CREDIT(4);
else
- val = MBUS_DBOX_A_CREDIT(2);
+ val |= MBUS_DBOX_A_CREDIT(2);
if (DISPLAY_VER(dev_priv) >= 12) {
val |= MBUS_DBOX_BW_CREDIT(2);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a0d652f19ff93..f47f9dfc9b0ce 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1103,16 +1103,22 @@
#define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0)
#define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0)
-#define _PIPEA_MBUS_DBOX_CTL 0x7003C
-#define _PIPEB_MBUS_DBOX_CTL 0x7103C
-#define PIPE_MBUS_DBOX_CTL(pipe) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \
- _PIPEB_MBUS_DBOX_CTL)
-#define MBUS_DBOX_BW_CREDIT_MASK (3 << 14)
-#define MBUS_DBOX_BW_CREDIT(x) ((x) << 14)
-#define MBUS_DBOX_B_CREDIT_MASK (0x1F << 8)
-#define MBUS_DBOX_B_CREDIT(x) ((x) << 8)
-#define MBUS_DBOX_A_CREDIT_MASK (0xF << 0)
-#define MBUS_DBOX_A_CREDIT(x) ((x) << 0)
+#define _PIPEA_MBUS_DBOX_CTL 0x7003C
+#define _PIPEB_MBUS_DBOX_CTL 0x7103C
+#define PIPE_MBUS_DBOX_CTL(pipe) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \
+ _PIPEB_MBUS_DBOX_CTL)
+#define MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK REG_GENMASK(24, 20)
+#define MBUS_DBOX_B2B_TRANSACTIONS_MAX(x) REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK, x)
+#define MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK REG_GENMASK(19, 17)
+#define MBUS_DBOX_B2B_TRANSACTIONS_DELAY(x) REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK, x)
+#define MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK REG_GENMASK(19, 17)
+#define MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN REG_BIT(16)
+#define MBUS_DBOX_BW_CREDIT_MASK REG_GENMASK(15, 14)
+#define MBUS_DBOX_BW_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, x)
+#define MBUS_DBOX_B_CREDIT_MASK REG_GENMASK(12, 8)
+#define MBUS_DBOX_B_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_B_CREDIT_MASK, x)
+#define MBUS_DBOX_A_CREDIT_MASK REG_GENMASK(3, 0)
+#define MBUS_DBOX_A_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_A_CREDIT_MASK, x)
#define MBUS_UBOX_CTL _MMIO(0x4503C)
#define MBUS_BBOX_CTL_S1 _MMIO(0x45040)
--
2.35.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH v4 2/4] drm/i915/display/adlp: Adjust MBUS DBOX BW and B credits
2022-03-29 22:30 [Intel-gfx] [PATCH v4 1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL José Roberto de Souza
@ 2022-03-29 22:31 ` José Roberto de Souza
2022-03-30 10:54 ` Ville Syrjälä
2022-03-29 22:31 ` [Intel-gfx] [PATCH v4 3/4] drm/i915/display: Add HAS_MBUS_JOINING José Roberto de Souza
` (7 subsequent siblings)
8 siblings, 1 reply; 12+ messages in thread
From: José Roberto de Souza @ 2022-03-29 22:31 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
From: Caz Yokoyama <caz.yokoyama@intel.com>
Alderlake-P has different MBUS DBOX BW and B credits than other
platforms, so here setting it properly.
BSpec: 49213
BSpec: 50343
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 234f363aad651..389a3c988dc6f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1844,7 +1844,10 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc, bool joined_mbus)
else
val |= MBUS_DBOX_A_CREDIT(2);
- if (DISPLAY_VER(dev_priv) >= 12) {
+ if (IS_ALDERLAKE_P(dev_priv)) {
+ val |= MBUS_DBOX_BW_CREDIT(2);
+ val |= MBUS_DBOX_B_CREDIT(8);
+ } else if (DISPLAY_VER(dev_priv) >= 12) {
val |= MBUS_DBOX_BW_CREDIT(2);
val |= MBUS_DBOX_B_CREDIT(12);
} else {
--
2.35.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH v4 3/4] drm/i915/display: Add HAS_MBUS_JOINING
2022-03-29 22:30 [Intel-gfx] [PATCH v4 1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL José Roberto de Souza
2022-03-29 22:31 ` [Intel-gfx] [PATCH v4 2/4] drm/i915/display/adlp: Adjust MBUS DBOX BW and B credits José Roberto de Souza
@ 2022-03-29 22:31 ` José Roberto de Souza
2022-03-29 22:31 ` [Intel-gfx] [PATCH v4 4/4] drm/i915/display/adlp: Fix programing of PIPE_MBUS_DBOX_CTL José Roberto de Souza
` (6 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: José Roberto de Souza @ 2022-03-29 22:31 UTC (permalink / raw)
To: intel-gfx
This will make easy to extend MBUS joining support to future platforms
that also supports this feature.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_pm.c | 6 +++---
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 217c09422711b..d7f4a95006c0d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1387,6 +1387,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_PERCTX_PREEMPT_CTRL(i915) \
((GRAPHICS_VER(i915) >= 9) && GRAPHICS_VER_FULL(i915) < IP_VER(12, 55))
+#define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915))
+
static inline bool run_as_guest(void)
{
return !hypervisor_is_type(X86_HYPER_NATIVE);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2c3cd4d775daf..e60c02d760ffa 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6038,7 +6038,7 @@ skl_compute_ddb(struct intel_atomic_state *state)
return ret;
}
- if (IS_ALDERLAKE_P(dev_priv))
+ if (HAS_MBUS_JOINING(dev_priv))
new_dbuf_state->joined_mbus =
adlp_check_mbus_joined(new_dbuf_state->active_pipes);
@@ -6530,7 +6530,7 @@ void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
to_intel_dbuf_state(dev_priv->dbuf.obj.state);
struct intel_crtc *crtc;
- if (IS_ALDERLAKE_P(dev_priv))
+ if (HAS_MBUS_JOINING(dev_priv))
dbuf_state->joined_mbus = intel_de_read(dev_priv, MBUS_CTL) & MBUS_JOIN;
for_each_intel_crtc(&dev_priv->drm, crtc) {
@@ -8192,7 +8192,7 @@ static void update_mbus_pre_enable(struct intel_atomic_state *state)
const struct intel_dbuf_state *dbuf_state =
intel_atomic_get_new_dbuf_state(state);
- if (!IS_ALDERLAKE_P(dev_priv))
+ if (!HAS_MBUS_JOINING(dev_priv))
return;
/*
--
2.35.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH v4 4/4] drm/i915/display/adlp: Fix programing of PIPE_MBUS_DBOX_CTL
2022-03-29 22:30 [Intel-gfx] [PATCH v4 1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL José Roberto de Souza
2022-03-29 22:31 ` [Intel-gfx] [PATCH v4 2/4] drm/i915/display/adlp: Adjust MBUS DBOX BW and B credits José Roberto de Souza
2022-03-29 22:31 ` [Intel-gfx] [PATCH v4 3/4] drm/i915/display: Add HAS_MBUS_JOINING José Roberto de Souza
@ 2022-03-29 22:31 ` José Roberto de Souza
2022-03-30 10:59 ` Ville Syrjälä
2022-03-29 22:41 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v4,1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL Patchwork
` (5 subsequent siblings)
8 siblings, 1 reply; 12+ messages in thread
From: José Roberto de Souza @ 2022-03-29 22:31 UTC (permalink / raw)
To: intel-gfx
PIPE_MBUS_DBOX_CTL was only being programmed when a pipe is being
enabled but that could potentially cause issues as it could have
mismatching values while pipes are being enabled.
So here moving the PIPE_MBUS_DBOX_CTL programming of all pipes to be
executed before the function that enables all pipes, leaving all pipes
with a matching A_CREDIT value.
While at it, also moving it to intel_pm.c as we are trying to reduce
the gigantic size of intel_display.c and intel_pm.c have other MBUS
programing sequences.
v2:
- do not program PIPE_MBUS_DBOX_CTL if pipe will not be active or
when it do not needs modeset
- remove the checks to wait a vblank
v3:
- checking if dbuf state is present in state before using it
v4:
- removing redundant checks
- calling intel_atomic_get_new_dbuf_state instead of
intel_atomic_get_dbuf_state
BSpec: 49213
BSpec: 50343
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 41 +--------------
drivers/gpu/drm/i915/intel_pm.c | 52 ++++++++++++++++++++
drivers/gpu/drm/i915/intel_pm.h | 1 +
3 files changed, 54 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 389a3c988dc6f..1bd869af15bf8 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1825,39 +1825,6 @@ static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val);
}
-static void icl_pipe_mbus_enable(struct intel_crtc *crtc, bool joined_mbus)
-{
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- enum pipe pipe = crtc->pipe;
- u32 val = 0;
-
- if (DISPLAY_VER(dev_priv) >= 12) {
- val |= MBUS_DBOX_B2B_TRANSACTIONS_MAX(16);
- val |= MBUS_DBOX_B2B_TRANSACTIONS_DELAY(1);
- val |= MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN;
- }
-
- /* Wa_22010947358:adl-p */
- if (IS_ALDERLAKE_P(dev_priv))
- val |= joined_mbus ? MBUS_DBOX_A_CREDIT(6) :
- MBUS_DBOX_A_CREDIT(4);
- else
- val |= MBUS_DBOX_A_CREDIT(2);
-
- if (IS_ALDERLAKE_P(dev_priv)) {
- val |= MBUS_DBOX_BW_CREDIT(2);
- val |= MBUS_DBOX_B_CREDIT(8);
- } else if (DISPLAY_VER(dev_priv) >= 12) {
- val |= MBUS_DBOX_BW_CREDIT(2);
- val |= MBUS_DBOX_B_CREDIT(12);
- } else {
- val |= MBUS_DBOX_BW_CREDIT(1);
- val |= MBUS_DBOX_B_CREDIT(8);
- }
-
- intel_de_write(dev_priv, PIPE_MBUS_DBOX_CTL(pipe), val);
-}
-
static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -1994,13 +1961,6 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
intel_initial_watermarks(state, crtc);
- if (DISPLAY_VER(dev_priv) >= 11) {
- const struct intel_dbuf_state *dbuf_state =
- intel_atomic_get_new_dbuf_state(state);
-
- icl_pipe_mbus_enable(crtc, dbuf_state->joined_mbus);
- }
-
if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
intel_crtc_vblank_on(new_crtc_state);
@@ -8612,6 +8572,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
intel_encoders_update_prepare(state);
intel_dbuf_pre_plane_update(state);
+ intel_mbus_dbox_update(state);
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
if (new_crtc_state->do_async_flip)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e60c02d760ffa..90ea5b87b52bb 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8258,3 +8258,55 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
gen9_dbuf_slices_update(dev_priv,
new_dbuf_state->enabled_slices);
}
+
+void intel_mbus_dbox_update(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;
+ struct intel_crtc_state *new_crtc_state;
+ struct intel_crtc *crtc;
+ u32 val = 0;
+ int i;
+
+ if (DISPLAY_VER(i915) < 11)
+ return;
+
+ new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
+ old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
+ if (!new_dbuf_state ||
+ (new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus &&
+ new_dbuf_state->active_pipes == old_dbuf_state->active_pipes))
+ return;
+
+ if (DISPLAY_VER(i915) >= 12) {
+ val |= MBUS_DBOX_B2B_TRANSACTIONS_MAX(16);
+ val |= MBUS_DBOX_B2B_TRANSACTIONS_DELAY(1);
+ val |= MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN;
+ }
+
+ /* Wa_22010947358:adl-p */
+ if (IS_ALDERLAKE_P(i915))
+ val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(6) :
+ MBUS_DBOX_A_CREDIT(4);
+ else
+ val |= MBUS_DBOX_A_CREDIT(2);
+
+ if (IS_ALDERLAKE_P(i915)) {
+ val |= MBUS_DBOX_BW_CREDIT(2);
+ val |= MBUS_DBOX_B_CREDIT(8);
+ } else if (DISPLAY_VER(i915) >= 12) {
+ val |= MBUS_DBOX_BW_CREDIT(2);
+ val |= MBUS_DBOX_B_CREDIT(12);
+ } else {
+ val |= MBUS_DBOX_BW_CREDIT(1);
+ val |= MBUS_DBOX_B_CREDIT(8);
+ }
+
+ for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+ if (!new_crtc_state->hw.active ||
+ !intel_crtc_needs_modeset(new_crtc_state))
+ continue;
+
+ intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe), val);
+ }
+}
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index 51705151b842f..50604cf7398c4 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -94,5 +94,6 @@ intel_atomic_get_dbuf_state(struct intel_atomic_state *state);
int intel_dbuf_init(struct drm_i915_private *dev_priv);
void intel_dbuf_pre_plane_update(struct intel_atomic_state *state);
void intel_dbuf_post_plane_update(struct intel_atomic_state *state);
+void intel_mbus_dbox_update(struct intel_atomic_state *state);
#endif /* __INTEL_PM_H__ */
--
2.35.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v4,1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL
2022-03-29 22:30 [Intel-gfx] [PATCH v4 1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL José Roberto de Souza
` (2 preceding siblings ...)
2022-03-29 22:31 ` [Intel-gfx] [PATCH v4 4/4] drm/i915/display/adlp: Fix programing of PIPE_MBUS_DBOX_CTL José Roberto de Souza
@ 2022-03-29 22:41 ` Patchwork
2022-03-29 22:42 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (4 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2022-03-29 22:41 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v4,1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL
URL : https://patchwork.freedesktop.org/series/101937/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
736622c4b868 drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL
-:74: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#74: FILE: drivers/gpu/drm/i915/i915_reg.h:1111:
+#define MBUS_DBOX_B2B_TRANSACTIONS_MAX(x) REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK, x)
-:76: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#76: FILE: drivers/gpu/drm/i915/i915_reg.h:1113:
+#define MBUS_DBOX_B2B_TRANSACTIONS_DELAY(x) REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK, x)
total: 0 errors, 2 warnings, 0 checks, 55 lines checked
3b609035e3bc drm/i915/display/adlp: Adjust MBUS DBOX BW and B credits
d26e768a064e drm/i915/display: Add HAS_MBUS_JOINING
34348e3c5a7f drm/i915/display/adlp: Fix programing of PIPE_MBUS_DBOX_CTL
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v4,1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL
2022-03-29 22:30 [Intel-gfx] [PATCH v4 1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL José Roberto de Souza
` (3 preceding siblings ...)
2022-03-29 22:41 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v4,1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL Patchwork
@ 2022-03-29 22:42 ` Patchwork
2022-03-29 22:46 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
` (3 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2022-03-29 22:42 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v4,1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL
URL : https://patchwork.freedesktop.org/series/101937/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [v4,1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL
2022-03-29 22:30 [Intel-gfx] [PATCH v4 1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL José Roberto de Souza
` (4 preceding siblings ...)
2022-03-29 22:42 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2022-03-29 22:46 ` Patchwork
2022-03-29 23:19 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2022-03-29 22:46 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v4,1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL
URL : https://patchwork.freedesktop.org/series/101937/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not found
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_disable' not found
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v4,1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL
2022-03-29 22:30 [Intel-gfx] [PATCH v4 1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL José Roberto de Souza
` (5 preceding siblings ...)
2022-03-29 22:46 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
@ 2022-03-29 23:19 ` Patchwork
2022-03-30 0:37 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-03-30 10:30 ` [Intel-gfx] [PATCH v4 1/4] " Ville Syrjälä
8 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2022-03-29 23:19 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 13198 bytes --]
== Series Details ==
Series: series starting with [v4,1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL
URL : https://patchwork.freedesktop.org/series/101937/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11416 -> Patchwork_22726
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/index.html
Participating hosts (43 -> 44)
------------------------------
Additional (5): fi-tgl-u2 fi-skl-guc fi-cfl-8700k bat-adlp-4 fi-ivb-3770
Missing (4): fi-bsw-cyan shard-rkl shard-tglu fi-bdw-samus
Known issues
------------
Here are the changes found in Patchwork_22726 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@query-info:
- fi-bsw-kefka: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/fi-bsw-kefka/igt@amdgpu/amd_basic@query-info.html
* igt@amdgpu/amd_basic@semaphore:
- fi-hsw-4770: NOTRUN -> [SKIP][2] ([fdo#109271] / [fdo#109315]) +17 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/fi-hsw-4770/igt@amdgpu/amd_basic@semaphore.html
* igt@amdgpu/amd_basic@userptr:
- fi-cfl-8700k: NOTRUN -> [SKIP][3] ([fdo#109271]) +29 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/fi-cfl-8700k/igt@amdgpu/amd_basic@userptr.html
* igt@gem_huc_copy@huc-copy:
- fi-tgl-u2: NOTRUN -> [SKIP][4] ([i915#2190])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/fi-tgl-u2/igt@gem_huc_copy@huc-copy.html
- fi-cfl-8700k: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/fi-cfl-8700k/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@random-engines:
- fi-skl-guc: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613]) +3 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/fi-skl-guc/igt@gem_lmem_swapping@random-engines.html
- fi-ivb-3770: NOTRUN -> [SKIP][7] ([fdo#109271]) +36 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/fi-ivb-3770/igt@gem_lmem_swapping@random-engines.html
- fi-cfl-8700k: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613]) +3 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/fi-cfl-8700k/igt@gem_lmem_swapping@random-engines.html
* igt@gem_lmem_swapping@verify-random:
- fi-tgl-u2: NOTRUN -> [SKIP][9] ([i915#4613]) +3 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/fi-tgl-u2/igt@gem_lmem_swapping@verify-random.html
* igt@i915_selftest@live@gt_engines:
- bat-dg1-6: [PASS][10] -> [INCOMPLETE][11] ([i915#4418])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-dg1-6/igt@i915_selftest@live@gt_engines.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/bat-dg1-6/igt@i915_selftest@live@gt_engines.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-tgl-u2: NOTRUN -> [SKIP][12] ([fdo#109284] / [fdo#111827]) +8 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/fi-tgl-u2/igt@kms_chamelium@common-hpd-after-suspend.html
- fi-skl-guc: NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +8 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/fi-skl-guc/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@dp-crc-fast:
- fi-cfl-8700k: NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827]) +8 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/fi-cfl-8700k/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_chamelium@dp-hpd-fast:
- fi-ivb-3770: NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#111827]) +8 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/fi-ivb-3770/igt@kms_chamelium@dp-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-u2: NOTRUN -> [SKIP][16] ([i915#4103]) +1 similar issue
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/fi-tgl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_flip@basic-flip-vs-dpms@a-edp1:
- fi-tgl-u2: NOTRUN -> [DMESG-WARN][17] ([i915#402]) +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/fi-tgl-u2/igt@kms_flip@basic-flip-vs-dpms@a-edp1.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-u2: NOTRUN -> [SKIP][18] ([fdo#109285])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/fi-tgl-u2/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-skl-guc: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#533])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/fi-skl-guc/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
- fi-cfl-8700k: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#533])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/fi-cfl-8700k/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_psr@primary_mmap_gtt:
- fi-skl-guc: NOTRUN -> [SKIP][21] ([fdo#109271]) +29 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/fi-skl-guc/igt@kms_psr@primary_mmap_gtt.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-tgl-u2: NOTRUN -> [SKIP][22] ([i915#3555])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/fi-tgl-u2/igt@kms_setmode@basic-clone-single-crtc.html
* igt@runner@aborted:
- bat-adlp-4: NOTRUN -> [FAIL][23] ([i915#5457])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/bat-adlp-4/igt@runner@aborted.html
- bat-dg1-6: NOTRUN -> [FAIL][24] ([i915#4312] / [i915#5257])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/bat-dg1-6/igt@runner@aborted.html
#### Possible fixes ####
* igt@i915_pm_rps@basic-api:
- {fi-jsl-1}: [DMESG-WARN][25] -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/fi-jsl-1/igt@i915_pm_rps@basic-api.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/fi-jsl-1/igt@i915_pm_rps@basic-api.html
* igt@i915_selftest@live@execlists:
- fi-bsw-kefka: [INCOMPLETE][27] ([i915#2940]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@gt_lrc:
- {bat-adlp-6}: [INCOMPLETE][29] -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-adlp-6/igt@i915_selftest@live@gt_lrc.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/bat-adlp-6/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@gt_timelines:
- {bat-rpls-2}: [DMESG-WARN][31] ([i915#4391]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-rpls-2/igt@i915_selftest@live@gt_timelines.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/bat-rpls-2/igt@i915_selftest@live@gt_timelines.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770: [INCOMPLETE][33] ([i915#4785]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
- {fi-ehl-2}: [INCOMPLETE][35] -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/fi-ehl-2/igt@i915_selftest@live@hangcheck.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/fi-ehl-2/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@requests:
- {bat-rpls-2}: [DMESG-FAIL][37] ([i915#5087]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-rpls-2/igt@i915_selftest@live@requests.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/bat-rpls-2/igt@i915_selftest@live@requests.html
* igt@i915_selftest@live@workarounds:
- {bat-adlp-6}: [DMESG-WARN][39] ([i915#5068]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-adlp-6/igt@i915_selftest@live@workarounds.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/bat-adlp-6/igt@i915_selftest@live@workarounds.html
* igt@kms_busy@basic@flip:
- {bat-adlp-6}: [DMESG-WARN][41] ([i915#3576]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-adlp-6/igt@kms_busy@basic@flip.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/bat-adlp-6/igt@kms_busy@basic@flip.html
- {bat-dg2-9}: [DMESG-WARN][43] ([i915#5291]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-dg2-9/igt@kms_busy@basic@flip.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/bat-dg2-9/igt@kms_busy@basic@flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4418]: https://gitlab.freedesktop.org/drm/intel/issues/4418
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4897]: https://gitlab.freedesktop.org/drm/intel/issues/4897
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5068]: https://gitlab.freedesktop.org/drm/intel/issues/5068
[i915#5087]: https://gitlab.freedesktop.org/drm/intel/issues/5087
[i915#5127]: https://gitlab.freedesktop.org/drm/intel/issues/5127
[i915#5153]: https://gitlab.freedesktop.org/drm/intel/issues/5153
[i915#5193]: https://gitlab.freedesktop.org/drm/intel/issues/5193
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5270]: https://gitlab.freedesktop.org/drm/intel/issues/5270
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5275]: https://gitlab.freedesktop.org/drm/intel/issues/5275
[i915#5278]: https://gitlab.freedesktop.org/drm/intel/issues/5278
[i915#5291]: https://gitlab.freedesktop.org/drm/intel/issues/5291
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5356]: https://gitlab.freedesktop.org/drm/intel/issues/5356
[i915#5457]: https://gitlab.freedesktop.org/drm/intel/issues/5457
Build changes
-------------
* Linux: CI_DRM_11416 -> Patchwork_22726
CI-20190529: 20190529
CI_DRM_11416: 1dc2c6953e2689a0e5b7cca8450da14059d35f03 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6399: 9ba6cb16f04319226383b57975db203561c75781 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22726: 34348e3c5a7f988d4a5ec89c7d290ae542e07a20 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
34348e3c5a7f drm/i915/display/adlp: Fix programing of PIPE_MBUS_DBOX_CTL
d26e768a064e drm/i915/display: Add HAS_MBUS_JOINING
3b609035e3bc drm/i915/display/adlp: Adjust MBUS DBOX BW and B credits
736622c4b868 drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/index.html
[-- Attachment #2: Type: text/html, Size: 14577 bytes --]
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v4,1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL
2022-03-29 22:30 [Intel-gfx] [PATCH v4 1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL José Roberto de Souza
` (6 preceding siblings ...)
2022-03-29 23:19 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2022-03-30 0:37 ` Patchwork
2022-03-30 10:30 ` [Intel-gfx] [PATCH v4 1/4] " Ville Syrjälä
8 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2022-03-30 0:37 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30335 bytes --]
== Series Details ==
Series: series starting with [v4,1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL
URL : https://patchwork.freedesktop.org/series/101937/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11416_full -> Patchwork_22726_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_22726_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_psr_stress_test@flip-primary-invalidate-overlay}:
- shard-tglb: [PASS][1] -> [SKIP][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-tglb6/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-tglb7/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
Known issues
------------
Here are the changes found in Patchwork_22726_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ccs@ctrl-surf-copy:
- shard-iclb: NOTRUN -> [SKIP][3] ([i915#5327])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-iclb6/igt@gem_ccs@ctrl-surf-copy.html
* igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-kbl: [PASS][4] -> [DMESG-WARN][5] ([i915#180]) +2 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-kbl6/igt@gem_ctx_isolation@preservation-s3@bcs0.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-kbl7/igt@gem_ctx_isolation@preservation-s3@bcs0.html
* igt@gem_ctx_persistence@legacy-engines-queued:
- shard-snb: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1099]) +1 similar issue
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-snb7/igt@gem_ctx_persistence@legacy-engines-queued.html
* igt@gem_ctx_sseu@invalid-sseu:
- shard-tglb: NOTRUN -> [SKIP][7] ([i915#280])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-tglb3/igt@gem_ctx_sseu@invalid-sseu.html
* igt@gem_eio@suspend:
- shard-tglb: [PASS][8] -> [DMESG-WARN][9] ([i915#2867])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-tglb5/igt@gem_eio@suspend.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-tglb2/igt@gem_eio@suspend.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][10] -> [TIMEOUT][11] ([i915#3063] / [i915#3648])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-tglb7/igt@gem_eio@unwedge-stress.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-tglb6/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-apl: [PASS][12] -> [FAIL][13] ([i915#2842])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-apl8/igt@gem_exec_fair@basic-none@vcs0.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-apl7/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-iclb: [PASS][14] -> [FAIL][15] ([i915#2842])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-iclb7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-iclb1/igt@gem_exec_fair@basic-pace-solo@rcs0.html
- shard-glk: [PASS][16] -> [FAIL][17] ([i915#2842])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-glk8/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-glk8/igt@gem_exec_fair@basic-pace-solo@rcs0.html
- shard-apl: NOTRUN -> [FAIL][18] ([i915#2842])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-apl4/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_schedule@submit-early-slice@vcs0:
- shard-skl: NOTRUN -> [INCOMPLETE][19] ([i915#3797])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-skl6/igt@gem_exec_schedule@submit-early-slice@vcs0.html
* igt@gem_lmem_swapping@heavy-random:
- shard-iclb: NOTRUN -> [SKIP][20] ([i915#4613])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-iclb6/igt@gem_lmem_swapping@heavy-random.html
* igt@gem_lmem_swapping@parallel-random:
- shard-tglb: NOTRUN -> [SKIP][21] ([i915#4613])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-tglb3/igt@gem_lmem_swapping@parallel-random.html
* igt@gem_lmem_swapping@smem-oom:
- shard-apl: NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#4613])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-apl6/igt@gem_lmem_swapping@smem-oom.html
- shard-skl: NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#4613])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-skl6/igt@gem_lmem_swapping@smem-oom.html
* igt@gem_pread@exhaustion:
- shard-snb: NOTRUN -> [WARN][24] ([i915#2658])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-snb7/igt@gem_pread@exhaustion.html
* igt@gem_pxp@reject-modify-context-protection-off-2:
- shard-iclb: NOTRUN -> [SKIP][25] ([i915#4270])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-iclb8/igt@gem_pxp@reject-modify-context-protection-off-2.html
* igt@gem_pxp@verify-pxp-stale-buf-optout-execution:
- shard-tglb: NOTRUN -> [SKIP][26] ([i915#4270])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-tglb3/igt@gem_pxp@verify-pxp-stale-buf-optout-execution.html
* igt@gem_render_copy@linear-to-vebox-y-tiled:
- shard-iclb: NOTRUN -> [SKIP][27] ([i915#768]) +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-iclb8/igt@gem_render_copy@linear-to-vebox-y-tiled.html
* igt@gem_userptr_blits@create-destroy-unsync:
- shard-iclb: NOTRUN -> [SKIP][28] ([i915#3297])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-iclb6/igt@gem_userptr_blits@create-destroy-unsync.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-skl: NOTRUN -> [SKIP][29] ([fdo#109271] / [i915#3323])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-skl2/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@input-checking:
- shard-kbl: NOTRUN -> [DMESG-WARN][30] ([i915#4991])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-kbl4/igt@gem_userptr_blits@input-checking.html
* igt@gen7_exec_parse@basic-allocation:
- shard-iclb: NOTRUN -> [SKIP][31] ([fdo#109289])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-iclb6/igt@gen7_exec_parse@basic-allocation.html
* igt@gen7_exec_parse@basic-allowed:
- shard-tglb: NOTRUN -> [SKIP][32] ([fdo#109289]) +1 similar issue
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-tglb3/igt@gen7_exec_parse@basic-allowed.html
* igt@gen9_exec_parse@basic-rejected-ctx-param:
- shard-iclb: NOTRUN -> [SKIP][33] ([i915#2856])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-iclb8/igt@gen9_exec_parse@basic-rejected-ctx-param.html
* igt@gen9_exec_parse@cmd-crossing-page:
- shard-tglb: NOTRUN -> [SKIP][34] ([i915#2527] / [i915#2856])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-tglb3/igt@gen9_exec_parse@cmd-crossing-page.html
* igt@i915_pm_rpm@dpms-non-lpsp:
- shard-iclb: NOTRUN -> [SKIP][35] ([fdo#110892])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-iclb6/igt@i915_pm_rpm@dpms-non-lpsp.html
* igt@i915_selftest@live@gt_lrc:
- shard-tglb: NOTRUN -> [DMESG-FAIL][36] ([i915#2373])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-tglb3/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@gt_pm:
- shard-tglb: NOTRUN -> [DMESG-FAIL][37] ([i915#1759])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-tglb3/igt@i915_selftest@live@gt_pm.html
* igt@kms_async_flips@crc:
- shard-skl: NOTRUN -> [FAIL][38] ([i915#4272])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-skl6/igt@kms_async_flips@crc.html
* igt@kms_atomic_transition@plane-all-modeset-transition:
- shard-iclb: NOTRUN -> [SKIP][39] ([i915#1769])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-iclb6/igt@kms_atomic_transition@plane-all-modeset-transition.html
* igt@kms_big_fb@4-tiled-8bpp-rotate-180:
- shard-tglb: NOTRUN -> [SKIP][40] ([i915#5286])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-tglb3/igt@kms_big_fb@4-tiled-8bpp-rotate-180.html
* igt@kms_big_fb@4-tiled-addfb-size-offset-overflow:
- shard-iclb: NOTRUN -> [SKIP][41] ([i915#5286])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-iclb6/igt@kms_big_fb@4-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@linear-32bpp-rotate-270:
- shard-tglb: NOTRUN -> [SKIP][42] ([fdo#111614])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-tglb3/igt@kms_big_fb@linear-32bpp-rotate-270.html
* igt@kms_big_fb@linear-8bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][43] ([fdo#110725] / [fdo#111614])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-iclb8/igt@kms_big_fb@linear-8bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-kbl: [PASS][44] -> [DMESG-WARN][45] ([i915#62] / [i915#92]) +22 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-kbl1/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-kbl6/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
- shard-skl: NOTRUN -> [FAIL][46] ([i915#3743]) +1 similar issue
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-skl6/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
- shard-apl: NOTRUN -> [SKIP][47] ([fdo#109271] / [i915#3777])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-apl6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
- shard-skl: NOTRUN -> [SKIP][48] ([fdo#109271] / [i915#3777]) +3 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-skl6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
- shard-tglb: NOTRUN -> [SKIP][49] ([fdo#111615])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-tglb3/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html
* igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][50] ([fdo#109271] / [i915#3886]) +5 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-skl8/igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs:
- shard-iclb: NOTRUN -> [SKIP][51] ([fdo#109278]) +13 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-iclb8/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][52] ([i915#3689] / [i915#3886])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-tglb3/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-bad-rotation-90-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][53] ([fdo#111615] / [i915#3689])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-tglb3/igt@kms_ccs@pipe-b-bad-rotation-90-yf_tiled_ccs.html
* igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-iclb: NOTRUN -> [SKIP][54] ([fdo#109278] / [i915#3886])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-iclb6/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
- shard-kbl: NOTRUN -> [SKIP][55] ([fdo#109271] / [i915#3886]) +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-kbl4/igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][56] ([i915#3689]) +1 similar issue
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-tglb3/igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_ccs.html
* igt@kms_chamelium@hdmi-hpd-storm-disable:
- shard-skl: NOTRUN -> [SKIP][57] ([fdo#109271] / [fdo#111827]) +10 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-skl2/igt@kms_chamelium@hdmi-hpd-storm-disable.html
* igt@kms_color@pipe-d-ctm-0-5:
- shard-skl: NOTRUN -> [SKIP][58] ([fdo#109271]) +164 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-skl2/igt@kms_color@pipe-d-ctm-0-5.html
* igt@kms_color_chamelium@pipe-b-ctm-blue-to-red:
- shard-kbl: NOTRUN -> [SKIP][59] ([fdo#109271] / [fdo#111827])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-kbl6/igt@kms_color_chamelium@pipe-b-ctm-blue-to-red.html
* igt@kms_color_chamelium@pipe-c-ctm-0-25:
- shard-tglb: NOTRUN -> [SKIP][60] ([fdo#109284] / [fdo#111827]) +3 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-tglb3/igt@kms_color_chamelium@pipe-c-ctm-0-25.html
* igt@kms_color_chamelium@pipe-c-ctm-max:
- shard-iclb: NOTRUN -> [SKIP][61] ([fdo#109284] / [fdo#111827]) +1 similar issue
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-iclb6/igt@kms_color_chamelium@pipe-c-ctm-max.html
* igt@kms_color_chamelium@pipe-d-ctm-limited-range:
- shard-apl: NOTRUN -> [SKIP][62] ([fdo#109271] / [fdo#111827]) +5 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-apl6/igt@kms_color_chamelium@pipe-d-ctm-limited-range.html
* igt@kms_color_chamelium@pipe-d-ctm-negative:
- shard-iclb: NOTRUN -> [SKIP][63] ([fdo#109278] / [fdo#109284] / [fdo#111827]) +1 similar issue
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-iclb8/igt@kms_color_chamelium@pipe-d-ctm-negative.html
* igt@kms_content_protection@dp-mst-lic-type-1:
- shard-tglb: NOTRUN -> [SKIP][64] ([i915#3116] / [i915#3299])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-tglb3/igt@kms_content_protection@dp-mst-lic-type-1.html
* igt@kms_content_protection@mei_interface:
- shard-iclb: NOTRUN -> [SKIP][65] ([fdo#109300] / [fdo#111066])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-iclb6/igt@kms_content_protection@mei_interface.html
* igt@kms_cursor_crc@pipe-b-cursor-32x10-sliding:
- shard-tglb: NOTRUN -> [SKIP][66] ([i915#3359]) +1 similar issue
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-tglb3/igt@kms_cursor_crc@pipe-b-cursor-32x10-sliding.html
* igt@kms_cursor_edge_walk@pipe-a-256x256-bottom-edge:
- shard-skl: [PASS][67] -> [DMESG-WARN][68] ([i915#1982])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-skl6/igt@kms_cursor_edge_walk@pipe-a-256x256-bottom-edge.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-skl8/igt@kms_cursor_edge_walk@pipe-a-256x256-bottom-edge.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
- shard-tglb: NOTRUN -> [SKIP][69] ([i915#4103])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-tglb3/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-kbl: [PASS][70] -> [FAIL][71] ([i915#2346] / [i915#533])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-kbl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-kbl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_draw_crc@draw-method-rgb565-render-4tiled:
- shard-iclb: NOTRUN -> [SKIP][72] ([i915#5287])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-iclb6/igt@kms_draw_crc@draw-method-rgb565-render-4tiled.html
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-4tiled:
- shard-tglb: NOTRUN -> [SKIP][73] ([i915#5287])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-tglb3/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-4tiled.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: NOTRUN -> [INCOMPLETE][74] ([i915#180])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-apl2/igt@kms_fbcon_fbt@fbc-suspend.html
- shard-kbl: NOTRUN -> [INCOMPLETE][75] ([i915#180] / [i915#636])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-kbl6/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@2x-dpms-vs-vblank-race-interruptible:
- shard-tglb: NOTRUN -> [SKIP][76] ([fdo#109274] / [fdo#111825]) +2 similar issues
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-tglb3/igt@kms_flip@2x-dpms-vs-vblank-race-interruptible.html
* igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible:
- shard-apl: NOTRUN -> [SKIP][77] ([fdo#109271]) +73 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-apl7/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html
* igt@kms_flip@2x-flip-vs-wf_vblank:
- shard-iclb: NOTRUN -> [SKIP][78] ([fdo#109274]) +2 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-iclb6/igt@kms_flip@2x-flip-vs-wf_vblank.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff:
- shard-iclb: NOTRUN -> [SKIP][79] ([fdo#109280]) +6 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-tglb: NOTRUN -> [SKIP][80] ([fdo#109280] / [fdo#111825]) +6 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-tglb3/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc:
- shard-kbl: NOTRUN -> [SKIP][81] ([fdo#109271]) +51 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-kbl6/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc.html
* igt@kms_hdr@bpc-switch-dpms@bpc-switch-dpms-edp-1-pipe-a:
- shard-skl: NOTRUN -> [FAIL][82] ([i915#1188])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-skl6/igt@kms_hdr@bpc-switch-dpms@bpc-switch-dpms-edp-1-pipe-a.html
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-d:
- shard-skl: NOTRUN -> [SKIP][83] ([fdo#109271] / [i915#533]) +1 similar issue
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-skl6/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html
- shard-apl: NOTRUN -> [SKIP][84] ([fdo#109271] / [i915#533])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-apl6/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
- shard-apl: [PASS][85] -> [DMESG-WARN][86] ([i915#180]) +2 similar issues
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-apl2/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: NOTRUN -> [FAIL][87] ([fdo#108145] / [i915#265])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-kbl: NOTRUN -> [FAIL][88] ([fdo#108145] / [i915#265])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-kbl4/igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
- shard-skl: NOTRUN -> [FAIL][89] ([i915#265])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
* igt@kms_plane_lowres@pipe-a-tiling-4:
- shard-tglb: NOTRUN -> [SKIP][90] ([i915#5288])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-tglb3/igt@kms_plane_lowres@pipe-a-tiling-4.html
* igt@kms_plane_lowres@pipe-b-tiling-y:
- shard-iclb: NOTRUN -> [SKIP][91] ([i915#3536])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-iclb8/igt@kms_plane_lowres@pipe-b-tiling-y.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area:
- shard-skl: NOTRUN -> [SKIP][92] ([fdo#109271] / [i915#658])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-skl2/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-apl: NOTRUN -> [SKIP][93] ([fdo#109271] / [i915#658])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-apl4/igt@kms_psr2_su@frontbuffer-xrgb8888.html
- shard-iclb: NOTRUN -> [SKIP][94] ([fdo#109642] / [fdo#111068] / [i915#658])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-iclb8/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr@psr2_cursor_plane_move:
- shard-iclb: NOTRUN -> [SKIP][95] ([fdo#109441])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-iclb6/igt@kms_psr@psr2_cursor_plane_move.html
* igt@kms_psr@psr2_primary_mmap_gtt:
- shard-tglb: NOTRUN -> [FAIL][96] ([i915#132] / [i915#3467])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-tglb3/igt@kms_psr@psr2_primary_mmap_gtt.html
* igt@kms_psr@psr2_sprite_render:
- shard-iclb: [PASS][97] -> [SKIP][98] ([fdo#109441]) +1 similar issue
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-iclb2/igt@kms_psr@psr2_sprite_render.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-iclb5/igt@kms_psr@psr2_sprite_render.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-0:
- shard-snb: NOTRUN -> [SKIP][99] ([fdo#109271]) +76 similar issues
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-snb7/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-tglb: NOTRUN -> [SKIP][100] ([i915#2437])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-tglb3/igt@kms_writeback@writeback-pixel-formats.html
* igt@nouveau_crc@pipe-a-ctx-flip-detection:
- shard-iclb: NOTRUN -> [SKIP][101] ([i915#2530]) +1 similar issue
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-iclb6/igt@nouveau_crc@pipe-a-ctx-flip-detection.html
* igt@nouveau_crc@pipe-d-source-outp-complete:
- shard-iclb: NOTRUN -> [SKIP][102] ([fdo#109278] / [i915#2530])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-iclb6/igt@nouveau_crc@pipe-d-source-outp-complete.html
* igt@prime_nv_api@i915_nv_import_twice:
- shard-iclb: NOTRUN -> [SKIP][103] ([fdo#109291])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-iclb8/igt@prime_nv_api@i915_nv_import_twice.html
* igt@prime_nv_pcopy@test3_2:
- shard-tglb: NOTRUN -> [SKIP][104] ([fdo#109291])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-tglb3/igt@prime_nv_pcopy@test3_2.html
* igt@syncobj_timeline@transfer-timeline-point:
- shard-apl: NOTRUN -> [DMESG-FAIL][105] ([i915#5098])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-apl7/igt@syncobj_timeline@transfer-timeline-point.html
* igt@sysfs_clients@busy:
- shard-kbl: NOTRUN -> [SKIP][106] ([fdo#109271] / [i915#2994])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-kbl4/igt@sysfs_clients@busy.html
* igt@sysfs_clients@fair-7:
- shard-iclb: NOTRUN -> [SKIP][107] ([i915#2994])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-iclb8/igt@sysfs_clients@fair-7.html
* igt@sysfs_clients@sema-10:
- shard-skl: NOTRUN -> [SKIP][108] ([fdo#109271] / [i915#2994]) +1 similar issue
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-skl6/igt@sysfs_clients@sema-10.html
* igt@sysfs_clients@split-25:
- shard-tglb: NOTRUN -> [SKIP][109] ([i915#2994])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-tglb3/igt@sysfs_clients@split-25.html
* igt@tools_test@sysfs_l3_parity:
- shard-tglb: NOTRUN -> [SKIP][110] ([fdo#109307])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-tglb3/igt@tools_test@sysfs_l3_parity.html
#### Possible fixes ####
* igt@gem_caching@reads:
- shard-glk: [DMESG-WARN][111] ([i915#118]) -> [PASS][112]
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-glk5/igt@gem_caching@reads.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-glk5/igt@gem_caching@reads.html
* igt@gem_eio@unwedge-stress:
- {shard-tglu}: [TIMEOUT][113] ([i915#3063] / [i915#3648]) -> [PASS][114]
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-tglu-1/igt@gem_eio@unwedge-stress.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-tglu-3/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_balancer@parallel-balancer:
- shard-iclb: [SKIP][115] ([i915#4525]) -> [PASS][116]
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-iclb5/igt@gem_exec_balancer@parallel-balancer.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-iclb4/igt@gem_exec_balancer@parallel-balancer.html
* igt@gem_exec_fair@basic-deadline:
- shard-kbl: [FAIL][117] ([i915#2846]) -> [PASS][118]
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-kbl1/igt@gem_exec_fair@basic-deadline.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-kbl7/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [FAIL][119] ([i915#2842]) -> [PASS][120]
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-iclb8/igt@gem_exec_fair@basic-none-share@rcs0.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-iclb6/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-apl: [FAIL][121] ([i915#2842]) -> [PASS][122]
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-apl8/igt@gem_exec_fair@basic-none@vecs0.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-apl7/igt@gem_exec_fair@basic-none@vecs0.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: [INCOMPLETE][123] ([i915#3921]) -> [PASS][124]
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-snb2/igt@i915_selftest@live@hangcheck.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-snb7/igt@i915_selftest@live@hangcheck.html
* igt@i915_suspend@debugfs-reader:
- shard-kbl: [DMESG-WARN][125] ([i915#180]) -> [PASS][126] +3 similar issues
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-kbl7/igt@i915_suspend@debugfs-reader.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-kbl4/igt@i915_suspend@debugfs-reader.html
* igt@kms_async_flips@alternate-sync-async-flip:
- shard-skl: [FAIL][127] ([i915#2521]) -> [PASS][128]
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-skl8/igt@kms_async_flips@alternate-sync-async-flip.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-skl9/igt@kms_async_flips@alternate-sync-async-flip.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-0:
- {shard-tglu}: [DMESG-WARN][129] ([i915#402]) -> [PASS][130]
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-tglu-2/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-tglu-3/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-apl: [DMESG-WARN][131] ([i915#180]) -> [PASS][132] +4 similar issues
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[132]: https://intel-gfx-ci.01.org/tr
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/index.html
[-- Attachment #2: Type: text/html, Size: 33899 bytes --]
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH v4 1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL
2022-03-29 22:30 [Intel-gfx] [PATCH v4 1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL José Roberto de Souza
` (7 preceding siblings ...)
2022-03-30 0:37 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2022-03-30 10:30 ` Ville Syrjälä
8 siblings, 0 replies; 12+ messages in thread
From: Ville Syrjälä @ 2022-03-30 10:30 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
On Tue, Mar 29, 2022 at 03:30:59PM -0700, José Roberto de Souza wrote:
> MBUS_DBOX_B2B_TRANSACTIONS_MAX, MBUS_DBOX_B2B_TRANSACTIONS_DELAY and
> MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN were being programmed with
> zeros while specification has different default values for this
> registers in display 12 and newer.
>
> While at it also converting all MBUS_DBOX macros to use REG_* macros.
>
> BSpec: 50343
> BSpec: 20231
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 13 +++++++---
> drivers/gpu/drm/i915/i915_reg.h | 26 ++++++++++++--------
> 2 files changed, 26 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 28bfb73ae6471..234f363aad651 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1829,13 +1829,20 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc, bool joined_mbus)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
> - u32 val;
> + u32 val = 0;
> +
> + if (DISPLAY_VER(dev_priv) >= 12) {
> + val |= MBUS_DBOX_B2B_TRANSACTIONS_MAX(16);
> + val |= MBUS_DBOX_B2B_TRANSACTIONS_DELAY(1);
> + val |= MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN;
> + }
>
> /* Wa_22010947358:adl-p */
> if (IS_ALDERLAKE_P(dev_priv))
> - val = joined_mbus ? MBUS_DBOX_A_CREDIT(6) : MBUS_DBOX_A_CREDIT(4);
> + val |= joined_mbus ? MBUS_DBOX_A_CREDIT(6) :
> + MBUS_DBOX_A_CREDIT(4);
> else
> - val = MBUS_DBOX_A_CREDIT(2);
> + val |= MBUS_DBOX_A_CREDIT(2);
It might make sense to have per-platform functions to determine
the whole register value. But that's a separate topic.
>
> if (DISPLAY_VER(dev_priv) >= 12) {
> val |= MBUS_DBOX_BW_CREDIT(2);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a0d652f19ff93..f47f9dfc9b0ce 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1103,16 +1103,22 @@
> #define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0)
> #define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0)
>
> -#define _PIPEA_MBUS_DBOX_CTL 0x7003C
> -#define _PIPEB_MBUS_DBOX_CTL 0x7103C
> -#define PIPE_MBUS_DBOX_CTL(pipe) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \
> - _PIPEB_MBUS_DBOX_CTL)
> -#define MBUS_DBOX_BW_CREDIT_MASK (3 << 14)
> -#define MBUS_DBOX_BW_CREDIT(x) ((x) << 14)
> -#define MBUS_DBOX_B_CREDIT_MASK (0x1F << 8)
> -#define MBUS_DBOX_B_CREDIT(x) ((x) << 8)
> -#define MBUS_DBOX_A_CREDIT_MASK (0xF << 0)
> -#define MBUS_DBOX_A_CREDIT(x) ((x) << 0)
> +#define _PIPEA_MBUS_DBOX_CTL 0x7003C
> +#define _PIPEB_MBUS_DBOX_CTL 0x7103C
> +#define PIPE_MBUS_DBOX_CTL(pipe) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \
> + _PIPEB_MBUS_DBOX_CTL)
> +#define MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK REG_GENMASK(24, 20)
Could throw in some tgl+ comments onto these b2b defines.
> +#define MBUS_DBOX_B2B_TRANSACTIONS_MAX(x) REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK, x)
> +#define MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK REG_GENMASK(19, 17)
> +#define MBUS_DBOX_B2B_TRANSACTIONS_DELAY(x) REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK, x)
> +#define MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK REG_GENMASK(19, 17)
Second MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK define.
with that removed:
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> +#define MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN REG_BIT(16)
> +#define MBUS_DBOX_BW_CREDIT_MASK REG_GENMASK(15, 14)
> +#define MBUS_DBOX_BW_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, x)
> +#define MBUS_DBOX_B_CREDIT_MASK REG_GENMASK(12, 8)
> +#define MBUS_DBOX_B_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_B_CREDIT_MASK, x)
> +#define MBUS_DBOX_A_CREDIT_MASK REG_GENMASK(3, 0)
> +#define MBUS_DBOX_A_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_A_CREDIT_MASK, x)
>
> #define MBUS_UBOX_CTL _MMIO(0x4503C)
> #define MBUS_BBOX_CTL_S1 _MMIO(0x45040)
> --
> 2.35.1
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH v4 2/4] drm/i915/display/adlp: Adjust MBUS DBOX BW and B credits
2022-03-29 22:31 ` [Intel-gfx] [PATCH v4 2/4] drm/i915/display/adlp: Adjust MBUS DBOX BW and B credits José Roberto de Souza
@ 2022-03-30 10:54 ` Ville Syrjälä
0 siblings, 0 replies; 12+ messages in thread
From: Ville Syrjälä @ 2022-03-30 10:54 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: Jani Nikula, intel-gfx
On Tue, Mar 29, 2022 at 03:31:00PM -0700, José Roberto de Souza wrote:
> From: Caz Yokoyama <caz.yokoyama@intel.com>
>
> Alderlake-P has different MBUS DBOX BW and B credits than other
> platforms, so here setting it properly.
Hmm. No explicit table for these so I guess we're going by the register
defaults here.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> BSpec: 49213
> BSpec: 50343
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 234f363aad651..389a3c988dc6f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1844,7 +1844,10 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc, bool joined_mbus)
> else
> val |= MBUS_DBOX_A_CREDIT(2);
>
> - if (DISPLAY_VER(dev_priv) >= 12) {
> + if (IS_ALDERLAKE_P(dev_priv)) {
> + val |= MBUS_DBOX_BW_CREDIT(2);
> + val |= MBUS_DBOX_B_CREDIT(8);
> + } else if (DISPLAY_VER(dev_priv) >= 12) {
> val |= MBUS_DBOX_BW_CREDIT(2);
> val |= MBUS_DBOX_B_CREDIT(12);
> } else {
> --
> 2.35.1
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH v4 4/4] drm/i915/display/adlp: Fix programing of PIPE_MBUS_DBOX_CTL
2022-03-29 22:31 ` [Intel-gfx] [PATCH v4 4/4] drm/i915/display/adlp: Fix programing of PIPE_MBUS_DBOX_CTL José Roberto de Souza
@ 2022-03-30 10:59 ` Ville Syrjälä
0 siblings, 0 replies; 12+ messages in thread
From: Ville Syrjälä @ 2022-03-30 10:59 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
On Tue, Mar 29, 2022 at 03:31:02PM -0700, José Roberto de Souza wrote:
> PIPE_MBUS_DBOX_CTL was only being programmed when a pipe is being
> enabled but that could potentially cause issues as it could have
> mismatching values while pipes are being enabled.
>
> So here moving the PIPE_MBUS_DBOX_CTL programming of all pipes to be
> executed before the function that enables all pipes, leaving all pipes
> with a matching A_CREDIT value.
>
> While at it, also moving it to intel_pm.c as we are trying to reduce
> the gigantic size of intel_display.c and intel_pm.c have other MBUS
> programing sequences.
>
> v2:
> - do not program PIPE_MBUS_DBOX_CTL if pipe will not be active or
> when it do not needs modeset
> - remove the checks to wait a vblank
>
> v3:
> - checking if dbuf state is present in state before using it
>
> v4:
> - removing redundant checks
> - calling intel_atomic_get_new_dbuf_state instead of
> intel_atomic_get_dbuf_state
>
> BSpec: 49213
> BSpec: 50343
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 41 +--------------
> drivers/gpu/drm/i915/intel_pm.c | 52 ++++++++++++++++++++
> drivers/gpu/drm/i915/intel_pm.h | 1 +
> 3 files changed, 54 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 389a3c988dc6f..1bd869af15bf8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1825,39 +1825,6 @@ static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
> intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val);
> }
>
> -static void icl_pipe_mbus_enable(struct intel_crtc *crtc, bool joined_mbus)
> -{
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - enum pipe pipe = crtc->pipe;
> - u32 val = 0;
> -
> - if (DISPLAY_VER(dev_priv) >= 12) {
> - val |= MBUS_DBOX_B2B_TRANSACTIONS_MAX(16);
> - val |= MBUS_DBOX_B2B_TRANSACTIONS_DELAY(1);
> - val |= MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN;
> - }
> -
> - /* Wa_22010947358:adl-p */
> - if (IS_ALDERLAKE_P(dev_priv))
> - val |= joined_mbus ? MBUS_DBOX_A_CREDIT(6) :
> - MBUS_DBOX_A_CREDIT(4);
> - else
> - val |= MBUS_DBOX_A_CREDIT(2);
> -
> - if (IS_ALDERLAKE_P(dev_priv)) {
> - val |= MBUS_DBOX_BW_CREDIT(2);
> - val |= MBUS_DBOX_B_CREDIT(8);
> - } else if (DISPLAY_VER(dev_priv) >= 12) {
> - val |= MBUS_DBOX_BW_CREDIT(2);
> - val |= MBUS_DBOX_B_CREDIT(12);
> - } else {
> - val |= MBUS_DBOX_BW_CREDIT(1);
> - val |= MBUS_DBOX_B_CREDIT(8);
> - }
> -
> - intel_de_write(dev_priv, PIPE_MBUS_DBOX_CTL(pipe), val);
> -}
> -
> static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -1994,13 +1961,6 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
>
> intel_initial_watermarks(state, crtc);
>
> - if (DISPLAY_VER(dev_priv) >= 11) {
> - const struct intel_dbuf_state *dbuf_state =
> - intel_atomic_get_new_dbuf_state(state);
> -
> - icl_pipe_mbus_enable(crtc, dbuf_state->joined_mbus);
> - }
> -
> if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
> intel_crtc_vblank_on(new_crtc_state);
>
> @@ -8612,6 +8572,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> intel_encoders_update_prepare(state);
>
> intel_dbuf_pre_plane_update(state);
> + intel_mbus_dbox_update(state);
>
> for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> if (new_crtc_state->do_async_flip)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index e60c02d760ffa..90ea5b87b52bb 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -8258,3 +8258,55 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
> gen9_dbuf_slices_update(dev_priv,
> new_dbuf_state->enabled_slices);
> }
> +
> +void intel_mbus_dbox_update(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> + struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;
> + struct intel_crtc_state *new_crtc_state;
Make the crtc/dbuf states const please.
With that
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> + struct intel_crtc *crtc;
> + u32 val = 0;
> + int i;
> +
> + if (DISPLAY_VER(i915) < 11)
> + return;
> +
> + new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
> + old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
> + if (!new_dbuf_state ||
> + (new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus &&
> + new_dbuf_state->active_pipes == old_dbuf_state->active_pipes))
> + return;
> +
> + if (DISPLAY_VER(i915) >= 12) {
> + val |= MBUS_DBOX_B2B_TRANSACTIONS_MAX(16);
> + val |= MBUS_DBOX_B2B_TRANSACTIONS_DELAY(1);
> + val |= MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN;
> + }
> +
> + /* Wa_22010947358:adl-p */
> + if (IS_ALDERLAKE_P(i915))
> + val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(6) :
> + MBUS_DBOX_A_CREDIT(4);
> + else
> + val |= MBUS_DBOX_A_CREDIT(2);
> +
> + if (IS_ALDERLAKE_P(i915)) {
> + val |= MBUS_DBOX_BW_CREDIT(2);
> + val |= MBUS_DBOX_B_CREDIT(8);
> + } else if (DISPLAY_VER(i915) >= 12) {
> + val |= MBUS_DBOX_BW_CREDIT(2);
> + val |= MBUS_DBOX_B_CREDIT(12);
> + } else {
> + val |= MBUS_DBOX_BW_CREDIT(1);
> + val |= MBUS_DBOX_B_CREDIT(8);
> + }
> +
> + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> + if (!new_crtc_state->hw.active ||
> + !intel_crtc_needs_modeset(new_crtc_state))
> + continue;
> +
> + intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe), val);
> + }
> +}
> diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
> index 51705151b842f..50604cf7398c4 100644
> --- a/drivers/gpu/drm/i915/intel_pm.h
> +++ b/drivers/gpu/drm/i915/intel_pm.h
> @@ -94,5 +94,6 @@ intel_atomic_get_dbuf_state(struct intel_atomic_state *state);
> int intel_dbuf_init(struct drm_i915_private *dev_priv);
> void intel_dbuf_pre_plane_update(struct intel_atomic_state *state);
> void intel_dbuf_post_plane_update(struct intel_atomic_state *state);
> +void intel_mbus_dbox_update(struct intel_atomic_state *state);
>
> #endif /* __INTEL_PM_H__ */
> --
> 2.35.1
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2022-03-30 10:59 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-03-29 22:30 [Intel-gfx] [PATCH v4 1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL José Roberto de Souza
2022-03-29 22:31 ` [Intel-gfx] [PATCH v4 2/4] drm/i915/display/adlp: Adjust MBUS DBOX BW and B credits José Roberto de Souza
2022-03-30 10:54 ` Ville Syrjälä
2022-03-29 22:31 ` [Intel-gfx] [PATCH v4 3/4] drm/i915/display: Add HAS_MBUS_JOINING José Roberto de Souza
2022-03-29 22:31 ` [Intel-gfx] [PATCH v4 4/4] drm/i915/display/adlp: Fix programing of PIPE_MBUS_DBOX_CTL José Roberto de Souza
2022-03-30 10:59 ` Ville Syrjälä
2022-03-29 22:41 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v4,1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL Patchwork
2022-03-29 22:42 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-03-29 22:46 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2022-03-29 23:19 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-03-30 0:37 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-03-30 10:30 ` [Intel-gfx] [PATCH v4 1/4] " Ville Syrjälä
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