From: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
To: Borislav Petkov <bp@alien8.de>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>,
Dave Hansen <dave.hansen@linux.intel.com>,
x86@kernel.org, "H. Peter Anvin" <hpa@zytor.com>,
Andi Kleen <ak@linux.intel.com>, Tony Luck <tony.luck@intel.com>,
linux-kernel@vger.kernel.org,
antonio.gomez.iglesias@linux.intel.com,
neelima.krishnan@intel.com, stable@vger.kernel.org,
Andrew Cooper <Andrew.Cooper3@citrix.com>,
Josh Poimboeuf <jpoimboe@redhat.com>
Subject: Re: [PATCH v2 2/2] x86/tsx: Disable TSX development mode at boot
Date: Tue, 29 Mar 2022 15:47:35 -0700 [thread overview]
Message-ID: <20220329224735.4pyst64r4dsfz2ea@guptapa-desk> (raw)
In-Reply-To: <YkMyo2Jw8iYx9wAU@zn.tnic>
On Tue, Mar 29, 2022 at 06:24:03PM +0200, Borislav Petkov wrote:
>On Thu, Mar 10, 2022 at 02:02:09PM -0800, Pawan Gupta wrote:
>> A microcode update on some Intel processors causes all TSX transactions
>> to always abort by default [*]. Microcode also added functionality to
>> re-enable TSX for development purpose. With this microcode loaded, if
>> tsx=on was passed on the cmdline, and TSX development mode was already
>> enabled before the kernel boot, it may make the system vulnerable to TSX
>> Asynchronous Abort (TAA).
>>
>> To be on safer side, unconditionally disable TSX development mode at
>> boot. If needed, a user can enable it using msr-tools.
>>
>> [*] Intel Transactional Synchronization Extension (Intel TSX) Disable Update for Selected Processors
>> https://cdrdv2.intel.com/v1/dl/getContent/643557
>>
>> Suggested-by: Andrew Cooper <andrew.cooper3@citrix.com>
>> Suggested-by: Borislav Petkov <bp@alien8.de>
>> Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
>> Cc: <stable@vger.kernel.org>
>> ---
>> arch/x86/include/asm/msr-index.h | 4 +--
>> arch/x86/kernel/cpu/cpu.h | 1 +
>> arch/x86/kernel/cpu/intel.c | 4 +++
>> arch/x86/kernel/cpu/tsx.c | 34 ++++++++++++++++++++++++++
>> tools/arch/x86/include/asm/msr-index.h | 4 +--
>> 5 files changed, 43 insertions(+), 4 deletions(-)
>
>Does this a lot more encapsulated version work too?
It look good to me.
Thanks,
Pawan
next prev parent reply other threads:[~2022-03-29 22:47 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-10 21:59 [PATCH v2 0/2] TSX update Pawan Gupta
2022-03-10 22:00 ` [PATCH v2 1/2] x86/tsx: Use MSR_TSX_CTRL to clear CPUID bits Pawan Gupta
2022-03-10 22:02 ` [PATCH v2 2/2] x86/tsx: Disable TSX development mode at boot Pawan Gupta
2022-03-29 16:24 ` Borislav Petkov
2022-03-29 22:47 ` Pawan Gupta [this message]
2022-03-30 5:27 ` Pawan Gupta
2022-04-06 19:13 ` Krishnan, Neelima
2022-03-22 23:32 ` [PATCH v2 0/2] TSX update Pawan Gupta
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