On 30.03.2022 09:46:08, Ondrej Ille wrote:
> sorry for the late reply, my work duties are keeping me very busy.

Known problem :)

> Let me just quickly comment on topics discussed in the emails above.
> 
> *1. Separation of PROP and TSEG1*
> 
> IMHO there is no real benefit. The reason why CTU CAN FD has this
> split is legacy. First implementation back in 2015 had this split
> since I wanted to follow the standard. In HW, the first thing done in
> bit timing logic (prescaler module), these two numbers are added, and
> all further resynchronization/hard-synchronization is done with TSEG1
> value...

Thanks for the insight. It's not easy to get in touch with the
developers of the proprietary IP cores :)

Never the less, there's another IP core which has different sizes for
the prop and tseg1 register. So an update of the bit timing constant
would help both.

> *2. Number of TXT Buffers and RX Buffer size:*
> 
> Pavel already replied with TXTB_INFO. The same role has the RX_MEM_INFO
> register, when it comes to RX side.

Thanks for the clarification.

regards,
Marc

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