From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C4CD9C433EF for ; Thu, 31 Mar 2022 15:15:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238068AbiCaPQp (ORCPT ); Thu, 31 Mar 2022 11:16:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43674 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238016AbiCaPQf (ORCPT ); Thu, 31 Mar 2022 11:16:35 -0400 Received: from ssl.serverraum.org (ssl.serverraum.org [176.9.125.105]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C26C55F4E2; Thu, 31 Mar 2022 08:14:47 -0700 (PDT) Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 0A11D22248; Thu, 31 Mar 2022 17:14:46 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1648739686; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=7Oo6DCwxDAZatTppGQauKS8CvTXIgeG2hnCjTf6RjvA=; b=eUJ8LOrg9M+lRLxcTwdkRi5rMDCYS0iTZ3/RiXTA4Ykscueszho7OQHpQtWuxvHWglPKV1 +IGSua63KaIV37YILYtZDEj2pfunK4WX72/LJAGKHHUXEja2/3rypFZrG/rnNX7WRH340T 862hT+kEdlDtEXzG7HyOsFvmpzc/VF4= From: Michael Walle To: "David S . Miller" , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Andrew Lunn , Heiner Kallweit , Russell King , Alexandre Belloni Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Walle Subject: [PATCH RFC net-next 2/3] dt-bindings: net: mscc-miim: add clock and clock-frequency Date: Thu, 31 Mar 2022 17:14:39 +0200 Message-Id: <20220331151440.3643482-2-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220331151440.3643482-1-michael@walle.cc> References: <20220331151440.3643482-1-michael@walle.cc> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the (optional) clock input of the MDIO controller and indicate that the common clock-frequency property is supported. The driver can use it to set the desired MDIO bus frequency. Signed-off-by: Michael Walle --- Documentation/devicetree/bindings/net/mscc,miim.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/net/mscc,miim.yaml b/Documentation/devicetree/bindings/net/mscc,miim.yaml index b52bf1732755..e9e8ddcdade9 100644 --- a/Documentation/devicetree/bindings/net/mscc,miim.yaml +++ b/Documentation/devicetree/bindings/net/mscc,miim.yaml @@ -32,6 +32,11 @@ properties: interrupts: true + clocks: + maxItems: 1 + + clock-frequency: true + required: - compatible - reg -- 2.30.2