From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 65A55C433EF for ; Tue, 5 Apr 2022 08:57:57 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id E88E8839D7; Tue, 5 Apr 2022 10:57:54 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="CgHe0l4J"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 7C28083AF5; Tue, 5 Apr 2022 10:57:53 +0200 (CEST) Received: from sin.source.kernel.org (sin.source.kernel.org [IPv6:2604:1380:40e1:4800::1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 9CA9183110 for ; Tue, 5 Apr 2022 10:57:45 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id 636C1CE1C74; Tue, 5 Apr 2022 08:57:42 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A792AC385A0; Tue, 5 Apr 2022 08:57:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1649149060; bh=KL30Vs0T10+INdeXsIuwAaomwSLjBjZBP4aLlnqR16E=; h=Date:From:To:Subject:From; b=CgHe0l4JHPoP2V15mYyOa8GIhcSB6gpBAjdbIX5rCGX6aSsmrqADwfnSeLuR3KhnE PprANM+THUrWNdDnJjvhnOOk6qUJEl/sozDoYzXKxIT6Bzm4b3QZGcUZWZEDt5xn2t 3PhZ5VDbZgnE+Pp8zYzru2ncQGHtl9ivXvztFHL1scUfrfRr781XAW2qKfktG7I2gb 0ZSZk+xkvSwnJIBx22aWo+TZITjQJdNiL84ZcU3UW1Bt/RE/pcO2xl1eAt/4cFRSeI zQwfHsXpFFmVPA7swLQgme6/p943BtRwGJyqtBydfWIthlNiAMwJFTUBpx8d/xwao/ dICjSTm9xtrUQ== Received: by pali.im (Postfix) id CCD1A7B2; Tue, 5 Apr 2022 10:57:37 +0200 (CEST) Date: Tue, 5 Apr 2022 10:57:37 +0200 From: Pali =?utf-8?B?Um9ow6Fy?= To: Priyanka Jain , Wolfgang Denk , u-boot@lists.denx.de Subject: Bug in p1_p2_rdb_pc? Caching-inhibited bit for initial L2 SRAM entry in TLB Message-ID: <20220405085737.s34rfws7rg2zhe2n@pali> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: NeoMutt/20180716 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Hello! I suspect that there is a bug in board/freescale/p1_p2_rdb_pc/tlb.c code which configures TLB entry for initial L2 SRAM. When L2 is 512 kB long (e.g. on P2020) then U-Boot *unsets* MAS2_I bit for first half of L2 and for second half of L2 U-Boot *sets* this bit. See code: https://source.denx.de/u-boot/u-boot/-/blob/v2022.04/board/freescale/p1_p2_rdb_pc/tlb.c#L99-104 I do not think that one part of L2 SRAM should be configured differently as second part. Therefore I think that this is a bug in U-Boot code. Do you know is correct configuration of TLB entries for initial L2 SRAM? MAS2_I is Caching-inhibited bit which is described as: Caching-inhibited: * 0 - Accesses to this page are considered cacheable. * 1 - The page is considered caching-inhibited. All loads and stores to the page bypass the caches and are performed directly to main memory. A read or write to a caching-inhibited page affects only the memory element specified by the operation.