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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Apr 2022 06:35:56.7496 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1f0e4fe8-0caa-4973-82c9-08da1797b4e2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT051.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4997 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Extend the logic of handling Intel's corrected machine check interrupt storms to AMD's threshold interrupts. First two patches are from Tony which cleans up the existing storm handling for Intel and proposes per CPU per bank storm handling. Third and fourth patches do some cleanup and refactoring on the CMCI storm handling in order to extend similar workaround for AMD's threshold interrupt storms. These two patches could be merged into Tony's second patch of CMCI storm mitigation. AMD's storm mitigation for threshold interrupts also relies on per CPU per bank approach similar to Intel. But unlike CMCI storm handling it does not set thresholds to reduce rate of interrupts on a storm. Rather it turns off the interrupt on the current CPU and bank if there is a storm and re-enables back the interrupts when the storm subsides. It is okay to turn off threshold interrupts on AMD systems as other error severities continue to be handled even if the threshold interrupts are turned off. Uncorrected errors will generate a #MC and deferred errors have a unique separate deferred error interrupt. The final patch adds support for handling threshold interrupt storms on AMD systems. Smita Koralahalli (3): x86/mce: Introduce a function pointer mce_handle_storm x86/mce: Move storm handling to core. x86/mce: Handle AMD threshold interrupt storms Tony Luck (2): x86/mce: Remove old CMCI storm mitigation code x86/mce: Add per-bank CMCI storm mitigation arch/x86/kernel/cpu/mce/amd.c | 49 ++++++++ arch/x86/kernel/cpu/mce/core.c | 129 +++++++++++++++++---- arch/x86/kernel/cpu/mce/intel.c | 179 +++++++---------------------- arch/x86/kernel/cpu/mce/internal.h | 42 +++++-- 4 files changed, 231 insertions(+), 168 deletions(-) -- 2.17.1