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Date:   Wed, 6 Apr 2022 09:49:08 +0200
From:   Miquel Raynal <miquel.raynal@bootlin.com>
To:     Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc:     Magnus Damm <magnus.damm@gmail.com>,
        Gareth Williams <gareth.williams.jx@renesas.com>,
        Phil Edworthy <phil.edworthy@renesas.com>,
        Geert Uytterhoeven <geert@linux-m68k.org>,
        Vinod Koul <vkoul@kernel.org>,
        linux-renesas-soc@vger.kernel.org, dmaengine@vger.kernel.org,
        Milan Stevanovic <milan.stevanovic@se.com>,
        Jimmy Lalande <jimmy.lalande@se.com>,
        Pascal Eberhard <pascal.eberhard@se.com>,
        Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
        Herve Codina <herve.codina@bootlin.com>,
        Clement Leger <clement.leger@bootlin.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Michael Turquette <mturquette@baylibre.com>,
        linux-clk@vger.kernel.org, Viresh Kumar <vireshk@kernel.org>,
        Ilpo Jarvinen <ilpo.jarvinen@linux.intel.com>
Subject: Re: [PATCH v7 5/9] dmaengine: dw: dmamux: Introduce RZN1 DMA router
 support
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        <20220405081911.1349563-6-miquel.raynal@bootlin.com>
        <YkxXUdMA75b8keSd@smile.fi.intel.com>
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Hi Andy,

andriy.shevchenko@linux.intel.com wrote on Tue, 5 Apr 2022 17:50:57
+0300:

> On Tue, Apr 05, 2022 at 10:19:07AM +0200, Miquel Raynal wrote:
> > The Renesas RZN1 DMA IP is based on a DW core, with eg. an additional
> > dmamux register located in the system control area which can take up to
> > 32 requests (16 per DMA controller). Each DMA channel can be wired to
> > two different peripherals.
> >=20
> > We need two additional information from the 'dmas' property: the channel
> > (bit in the dmamux register) that must be accessed and the value of the
> > mux for this channel. =20
>=20
> ...
>=20
> >  dw_dmac-y			:=3D platform.o
> >  dw_dmac-$(CONFIG_OF)		+=3D of.o =20
>=20
> > +obj-$(CONFIG_RZN1_DMAMUX)	+=3D rzn1-dmamux.o =20
>=20
> I would move it down in the file to distinguish more generic drivers
> from specific quirks.

Ok.

>=20
> >  obj-$(CONFIG_DW_DMAC_PCI)	+=3D dw_dmac_pci.o
> >  dw_dmac_pci-y			:=3D pci.o =20
>=20
> ...
>=20
> > +#define RZN1_DMAMUX_SPLIT 16 =20
>=20
> I would name it more explicitly:
>=20
> #define RZN1_DMAMUX_SPLIT_1_0	 16

I am sorry but I don't understand this suffix, which probably means
that it is not as clear as we wish. Do you mind if I stick to
RZN1_DMAMUX_SPLIT?

> ...
>=20
> > +	dmac_idx =3D map->req_idx < RZN1_DMAMUX_SPLIT ? 0 : 1; =20
>=20
> ...and hence use positive conditional:
>=20
> 	dmac_idx =3D map->req_idx >=3D RZN1_DMAMUX_SPLIT_1_0 ? 1 : 0;

I will.

>=20
> With above addressed
> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
>=20


Thanks,
Miqu=C3=A8l