* [RESEND v17 0/7] Add Mediatek Soc DRM (vdosys0) support for mt8195
@ 2022-04-07 3:04 ` jason-jh.lin
0 siblings, 0 replies; 49+ messages in thread
From: jason-jh.lin @ 2022-04-07 3:04 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: David Airlie, singo.chang, Alexandre Torgue, postmaster,
Fabien Parent, John 'Warthog9' Hawley, linux-stm32,
roy-cw.yeh, Project_Global_Chrome_Upstream_Group, CK Hu,
Philipp Zabel, devicetree, Daniel Vetter, nancy.lin,
linux-mediatek, hsinyi, linux-arm-kernel, jason-jh . lin,
linux-kernel, moudy.ho, Maxime Coquelin
Change in v17:
- change compatible name from 2 vdosys to 1 mmsys
- add get driver data by clk name function to get corresponding
driver data for mt8195 vdosys0
- add all routing table setting for mt8195 vdosys0
- remove useless mutex define
Change in v16:
- rebase on linu-next tag: 'next-20220303'
- rebase on series: 'Fix MediaTek display dt-bindings issues'
Change in v15:
- remove mt8195-mmsys.h comment for mux settings
- define the mask macro to replace using value as mask
to fix zero mask problem
- add EOF setting comment for MUTEX sof register
Change in v14:
- rebase on mediatek-drm-next-5.17
- rebase on "Add mmsys and mutex support for MDP" series
- rebase on "media: mediatek: support mdp3 on mt8183 platform" series
Change in v13:
- remove dts patch
- rebase on kernel-5.16-rc1
- rebase on mediatek-drm-next
Change in v12:
- add clock-names property to merge yaml
- using BIT(nr) macro to define the settings of mmsys routing table
- fix clk_get and clk_prepare_enable error handling issue
Change in v11:
- rebase on kernel-5.15-rc1
- change mbox label to gce0 for dts node of vdosys0
- change ovl compatibale to mt8192 to set smi_id_en=true in driver data
- move common module from display folder to common folder,
such as AAL, COCLOR, CCORR and MUTEX
Change in v10:
- rebase on "drm/mediatek: add support for mediatek SOC MT8192" series
- rebase on "soc: mediatek: mmsys: add mt8192 mmsys support" series
- fix some typo and "mediatek" start with capital in every dt-bindings
- move mutex yaml from dfisplay folder to soc folder
- separate merge additional propoerties to an individual dt-bindings patch
Change in v9:
- separate power and gce properties of mmsys into another dt-binding patch
- rebase on "Separate aal module" series
- keep mtk_ddp_clk_enable/disable in the same place
- change mtk_dsc_start config register to mtk_drm_ddp_write_mask
- remove the 0 setting of merge fifo config function
- add CCORR driver data for mt8195
Change in v8:
- add DP_INTF0 mux into mmsys routing table
- add DP_INTF0 mutex mod and enum into add/remove comp function
- remove bypass DSC enum in mtk_ddp_comp_init
Change in v7:
- add dt=binding of mmsys and disp path into this series
- separate th modidfication of alphabetic order, remove unused define and
rename the define of register offset to individual patch
- add comment for MERGE ultra and preultra setting
Change in v6:
- adjust alphabetic order for mediatek-drm
- move the patch that add mt8195 support for mediatek-drm as
the lastest patch
- add MERGE define for const varriable
Change in v5:
- add power-domain property into vdosys0 and vdosys1 dts node.
- add MT8195 prifix and remove unused VDO1 define in mt8195-mmsys.h
Change in v4:
- extract dt-binding patches to another patch series
- squash DSC module into mtk_drm_ddp_comp.c
- add coment and simplify MERGE config function
Change in v3:
- change mmsys and display dt-bindings document from txt to yaml
- add MERGE additional description in display dt-bindings document
- fix mboxes-cells number of vdosys0 node in dts
- drop mutex eof convert define
- remove pm_runtime apis in DSC and MERGE
- change DSC and MERGE enum to alphabetic order
Change in v2:
- add DSC yaml file
- add mt8195 drm driver porting parts in to one patch
- remove useless define, variable, structure member and function
- simplify DSC and MERGE file and switch threre order
jason-jh.lin (7):
dt-bindings: arm: mediatek: mmsys: add power and gce properties
dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
soc: mediatek: add mtk-mutex support for mt8195 vdosys0
drm/mediatek: add DSC support for mediatek-drm
drm/mediatek: add MERGE support for mediatek-drm
drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
.../bindings/arm/mediatek/mediatek,mmsys.yaml | 35 ++
drivers/gpu/drm/mediatek/Makefile | 1 +
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 246 ++++++++++++
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 65 ++-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 2 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 90 ++++-
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 3 +
drivers/soc/mediatek/mt8167-mmsys.h | 2 +-
drivers/soc/mediatek/mt8183-mmsys.h | 2 +-
drivers/soc/mediatek/mt8186-mmsys.h | 4 +-
drivers/soc/mediatek/mt8192-mmsys.h | 4 +-
drivers/soc/mediatek/mt8195-mmsys.h | 370 ++++++++++++++++++
drivers/soc/mediatek/mt8365-mmsys.h | 4 +-
drivers/soc/mediatek/mtk-mmsys.c | 62 +++
drivers/soc/mediatek/mtk-mmsys.h | 1 +
drivers/soc/mediatek/mtk-mutex.c | 95 ++++-
include/linux/soc/mediatek/mtk-mmsys.h | 13 +-
19 files changed, 992 insertions(+), 21 deletions(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 49+ messages in thread
* [RESEND v17 0/7] Add Mediatek Soc DRM (vdosys0) support for mt8195
@ 2022-04-07 3:04 ` jason-jh.lin
0 siblings, 0 replies; 49+ messages in thread
From: jason-jh.lin @ 2022-04-07 3:04 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: Philipp Zabel, Maxime Coquelin, David Airlie, Daniel Vetter,
Alexandre Torgue, John 'Warthog9' Hawley, postmaster,
jason-jh . lin, hsinyi, fshao, moudy.ho, roy-cw.yeh, CK Hu,
Fabien Parent, nancy.lin, singo.chang, devicetree, linux-stm32,
linux-arm-kernel, linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group
Change in v17:
- change compatible name from 2 vdosys to 1 mmsys
- add get driver data by clk name function to get corresponding
driver data for mt8195 vdosys0
- add all routing table setting for mt8195 vdosys0
- remove useless mutex define
Change in v16:
- rebase on linu-next tag: 'next-20220303'
- rebase on series: 'Fix MediaTek display dt-bindings issues'
Change in v15:
- remove mt8195-mmsys.h comment for mux settings
- define the mask macro to replace using value as mask
to fix zero mask problem
- add EOF setting comment for MUTEX sof register
Change in v14:
- rebase on mediatek-drm-next-5.17
- rebase on "Add mmsys and mutex support for MDP" series
- rebase on "media: mediatek: support mdp3 on mt8183 platform" series
Change in v13:
- remove dts patch
- rebase on kernel-5.16-rc1
- rebase on mediatek-drm-next
Change in v12:
- add clock-names property to merge yaml
- using BIT(nr) macro to define the settings of mmsys routing table
- fix clk_get and clk_prepare_enable error handling issue
Change in v11:
- rebase on kernel-5.15-rc1
- change mbox label to gce0 for dts node of vdosys0
- change ovl compatibale to mt8192 to set smi_id_en=true in driver data
- move common module from display folder to common folder,
such as AAL, COCLOR, CCORR and MUTEX
Change in v10:
- rebase on "drm/mediatek: add support for mediatek SOC MT8192" series
- rebase on "soc: mediatek: mmsys: add mt8192 mmsys support" series
- fix some typo and "mediatek" start with capital in every dt-bindings
- move mutex yaml from dfisplay folder to soc folder
- separate merge additional propoerties to an individual dt-bindings patch
Change in v9:
- separate power and gce properties of mmsys into another dt-binding patch
- rebase on "Separate aal module" series
- keep mtk_ddp_clk_enable/disable in the same place
- change mtk_dsc_start config register to mtk_drm_ddp_write_mask
- remove the 0 setting of merge fifo config function
- add CCORR driver data for mt8195
Change in v8:
- add DP_INTF0 mux into mmsys routing table
- add DP_INTF0 mutex mod and enum into add/remove comp function
- remove bypass DSC enum in mtk_ddp_comp_init
Change in v7:
- add dt=binding of mmsys and disp path into this series
- separate th modidfication of alphabetic order, remove unused define and
rename the define of register offset to individual patch
- add comment for MERGE ultra and preultra setting
Change in v6:
- adjust alphabetic order for mediatek-drm
- move the patch that add mt8195 support for mediatek-drm as
the lastest patch
- add MERGE define for const varriable
Change in v5:
- add power-domain property into vdosys0 and vdosys1 dts node.
- add MT8195 prifix and remove unused VDO1 define in mt8195-mmsys.h
Change in v4:
- extract dt-binding patches to another patch series
- squash DSC module into mtk_drm_ddp_comp.c
- add coment and simplify MERGE config function
Change in v3:
- change mmsys and display dt-bindings document from txt to yaml
- add MERGE additional description in display dt-bindings document
- fix mboxes-cells number of vdosys0 node in dts
- drop mutex eof convert define
- remove pm_runtime apis in DSC and MERGE
- change DSC and MERGE enum to alphabetic order
Change in v2:
- add DSC yaml file
- add mt8195 drm driver porting parts in to one patch
- remove useless define, variable, structure member and function
- simplify DSC and MERGE file and switch threre order
jason-jh.lin (7):
dt-bindings: arm: mediatek: mmsys: add power and gce properties
dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
soc: mediatek: add mtk-mutex support for mt8195 vdosys0
drm/mediatek: add DSC support for mediatek-drm
drm/mediatek: add MERGE support for mediatek-drm
drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
.../bindings/arm/mediatek/mediatek,mmsys.yaml | 35 ++
drivers/gpu/drm/mediatek/Makefile | 1 +
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 246 ++++++++++++
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 65 ++-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 2 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 90 ++++-
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 3 +
drivers/soc/mediatek/mt8167-mmsys.h | 2 +-
drivers/soc/mediatek/mt8183-mmsys.h | 2 +-
drivers/soc/mediatek/mt8186-mmsys.h | 4 +-
drivers/soc/mediatek/mt8192-mmsys.h | 4 +-
drivers/soc/mediatek/mt8195-mmsys.h | 370 ++++++++++++++++++
drivers/soc/mediatek/mt8365-mmsys.h | 4 +-
drivers/soc/mediatek/mtk-mmsys.c | 62 +++
drivers/soc/mediatek/mtk-mmsys.h | 1 +
drivers/soc/mediatek/mtk-mutex.c | 95 ++++-
include/linux/soc/mediatek/mtk-mmsys.h | 13 +-
19 files changed, 992 insertions(+), 21 deletions(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 49+ messages in thread
* [RESEND v17 1/7] dt-bindings: arm: mediatek: mmsys: add power and gce properties
2022-04-07 3:04 ` jason-jh.lin
@ 2022-04-07 3:04 ` jason-jh.lin
-1 siblings, 0 replies; 49+ messages in thread
From: jason-jh.lin @ 2022-04-07 3:04 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: David Airlie, singo.chang, Alexandre Torgue, postmaster,
Fabien Parent, John 'Warthog9' Hawley, linux-stm32,
roy-cw.yeh, Project_Global_Chrome_Upstream_Group, CK Hu,
Philipp Zabel, devicetree, Daniel Vetter, nancy.lin,
linux-mediatek, hsinyi, linux-arm-kernel, jason-jh . lin,
linux-kernel, moudy.ho, Maxime Coquelin
Power:
1. Add description for power-domains property.
GCE:
1. Add description for mboxes property.
2. Add description for mediatek,gce-client-reg property.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
---
.../bindings/arm/mediatek/mediatek,mmsys.yaml | 31 +++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index b31d90dc9eb4..6c2c3edcd443 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -41,6 +41,30 @@ properties:
reg:
maxItems: 1
+ power-domains:
+ description:
+ A phandle and PM domain specifier as defined by bindings
+ of the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+ mboxes:
+ description:
+ Using mailbox to communicate with GCE, it should have this
+ property and list of phandle, mailbox specifiers. See
+ Documentation/devicetree/bindings/mailbox/mtk-gce.txt for details.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+
+ mediatek,gce-client-reg:
+ description:
+ The register of client driver can be configured by gce with 4 arguments
+ defined in this property, such as phandle of gce, subsys id,
+ register offset and size.
+ Each subsys id is mapping to a base address of display function blocks
+ register which is defined in the gce header
+ include/dt-bindings/gce/<chip>-gce.h.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+
"#clock-cells":
const: 1
@@ -56,9 +80,16 @@ additionalProperties: false
examples:
- |
+ #include <dt-bindings/power/mt8173-power.h>
+ #include <dt-bindings/gce/mt8173-gce.h>
+
mmsys: syscon@14000000 {
compatible = "mediatek,mt8173-mmsys", "syscon";
reg = <0x14000000 0x1000>;
+ power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
#clock-cells = <1>;
#reset-cells = <1>;
+ mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
+ <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
};
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [RESEND v17 1/7] dt-bindings: arm: mediatek: mmsys: add power and gce properties
@ 2022-04-07 3:04 ` jason-jh.lin
0 siblings, 0 replies; 49+ messages in thread
From: jason-jh.lin @ 2022-04-07 3:04 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: Philipp Zabel, Maxime Coquelin, David Airlie, Daniel Vetter,
Alexandre Torgue, John 'Warthog9' Hawley, postmaster,
jason-jh . lin, hsinyi, fshao, moudy.ho, roy-cw.yeh, CK Hu,
Fabien Parent, nancy.lin, singo.chang, devicetree, linux-stm32,
linux-arm-kernel, linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group
Power:
1. Add description for power-domains property.
GCE:
1. Add description for mboxes property.
2. Add description for mediatek,gce-client-reg property.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
---
.../bindings/arm/mediatek/mediatek,mmsys.yaml | 31 +++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index b31d90dc9eb4..6c2c3edcd443 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -41,6 +41,30 @@ properties:
reg:
maxItems: 1
+ power-domains:
+ description:
+ A phandle and PM domain specifier as defined by bindings
+ of the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+ mboxes:
+ description:
+ Using mailbox to communicate with GCE, it should have this
+ property and list of phandle, mailbox specifiers. See
+ Documentation/devicetree/bindings/mailbox/mtk-gce.txt for details.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+
+ mediatek,gce-client-reg:
+ description:
+ The register of client driver can be configured by gce with 4 arguments
+ defined in this property, such as phandle of gce, subsys id,
+ register offset and size.
+ Each subsys id is mapping to a base address of display function blocks
+ register which is defined in the gce header
+ include/dt-bindings/gce/<chip>-gce.h.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+
"#clock-cells":
const: 1
@@ -56,9 +80,16 @@ additionalProperties: false
examples:
- |
+ #include <dt-bindings/power/mt8173-power.h>
+ #include <dt-bindings/gce/mt8173-gce.h>
+
mmsys: syscon@14000000 {
compatible = "mediatek,mt8173-mmsys", "syscon";
reg = <0x14000000 0x1000>;
+ power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
#clock-cells = <1>;
#reset-cells = <1>;
+ mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
+ <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
};
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [RESEND v17 2/7] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
2022-04-07 3:04 ` jason-jh.lin
@ 2022-04-07 3:04 ` jason-jh.lin
-1 siblings, 0 replies; 49+ messages in thread
From: jason-jh.lin @ 2022-04-07 3:04 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: David Airlie, singo.chang, Alexandre Torgue, postmaster,
Fabien Parent, John 'Warthog9' Hawley, linux-stm32,
roy-cw.yeh, Project_Global_Chrome_Upstream_Group, CK Hu,
Philipp Zabel, devicetree, Daniel Vetter, nancy.lin,
linux-mediatek, hsinyi, linux-arm-kernel, jason-jh . lin,
linux-kernel, moudy.ho, Maxime Coquelin
In the SoC before, such as mt8173, it has 2 pipelines binding to one
mmsys with the same clock driver and the same power domain.
In mt8195, there are 4 pipelines binding to 4 different mmsys, such as
vdosys0, vdosys1, vppsys0 and vppsys1.
Each mmsys uses different clock drivers and different power domain.
Since each mmsys has its own clock, they could be identified
by the different name of their clock.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
.../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index 6c2c3edcd443..f71c8dd07bf9 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -31,6 +31,7 @@ properties:
- mediatek,mt8183-mmsys
- mediatek,mt8186-mmsys
- mediatek,mt8192-mmsys
+ - mediatek,mt8195-mmsys
- mediatek,mt8365-mmsys
- const: syscon
- items:
@@ -65,6 +66,9 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 1
+ clocks:
+ maxItems: 1
+
"#clock-cells":
const: 1
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [RESEND v17 2/7] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
@ 2022-04-07 3:04 ` jason-jh.lin
0 siblings, 0 replies; 49+ messages in thread
From: jason-jh.lin @ 2022-04-07 3:04 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: Philipp Zabel, Maxime Coquelin, David Airlie, Daniel Vetter,
Alexandre Torgue, John 'Warthog9' Hawley, postmaster,
jason-jh . lin, hsinyi, fshao, moudy.ho, roy-cw.yeh, CK Hu,
Fabien Parent, nancy.lin, singo.chang, devicetree, linux-stm32,
linux-arm-kernel, linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group
In the SoC before, such as mt8173, it has 2 pipelines binding to one
mmsys with the same clock driver and the same power domain.
In mt8195, there are 4 pipelines binding to 4 different mmsys, such as
vdosys0, vdosys1, vppsys0 and vppsys1.
Each mmsys uses different clock drivers and different power domain.
Since each mmsys has its own clock, they could be identified
by the different name of their clock.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
.../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index 6c2c3edcd443..f71c8dd07bf9 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -31,6 +31,7 @@ properties:
- mediatek,mt8183-mmsys
- mediatek,mt8186-mmsys
- mediatek,mt8192-mmsys
+ - mediatek,mt8195-mmsys
- mediatek,mt8365-mmsys
- const: syscon
- items:
@@ -65,6 +66,9 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 1
+ clocks:
+ maxItems: 1
+
"#clock-cells":
const: 1
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [RESEND v17 3/7] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
2022-04-07 3:04 ` jason-jh.lin
@ 2022-04-07 3:04 ` jason-jh.lin
-1 siblings, 0 replies; 49+ messages in thread
From: jason-jh.lin @ 2022-04-07 3:04 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: David Airlie, singo.chang, Alexandre Torgue, postmaster,
Fabien Parent, John 'Warthog9' Hawley, linux-stm32,
roy-cw.yeh, Project_Global_Chrome_Upstream_Group, CK Hu,
Philipp Zabel, devicetree, Daniel Vetter, nancy.lin,
linux-mediatek, hsinyi, linux-arm-kernel, jason-jh . lin,
linux-kernel, moudy.ho, Maxime Coquelin
1. Add mt8195 mmsys compatible for vdosys0.
2. Add mt8195 routing table settings and fix build fail.
3. Add clock name, clock driver name and routing table into the driver data
of mt8195 vdosys0.
4. Add get match data by clock name function and clock platform labels
to identify which mmsys node is corresponding to vdosys0.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 6 +-
drivers/soc/mediatek/mt8167-mmsys.h | 2 +-
drivers/soc/mediatek/mt8183-mmsys.h | 2 +-
drivers/soc/mediatek/mt8186-mmsys.h | 4 +-
drivers/soc/mediatek/mt8192-mmsys.h | 4 +-
drivers/soc/mediatek/mt8195-mmsys.h | 370 ++++++++++++++++++++
drivers/soc/mediatek/mt8365-mmsys.h | 4 +-
drivers/soc/mediatek/mtk-mmsys.c | 62 ++++
drivers/soc/mediatek/mtk-mmsys.h | 1 +
drivers/soc/mediatek/mtk-mutex.c | 8 +-
include/linux/soc/mediatek/mtk-mmsys.h | 13 +-
12 files changed, 461 insertions(+), 17 deletions(-)
create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 2e99aee13dfe..f543d3eb9439 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -366,7 +366,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr },
[DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color },
[DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color },
- [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither },
+ [DDP_COMPONENT_DITHER0] = { MTK_DISP_DITHER, 0, &ddp_dither },
[DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi },
[DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi },
[DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi },
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 247c6ff277ef..6a0a167320f0 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -116,7 +116,7 @@ static enum mtk_ddp_comp_id mt8167_mtk_ddp_main[] = {
DDP_COMPONENT_CCORR,
DDP_COMPONENT_AAL0,
DDP_COMPONENT_GAMMA,
- DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DITHER0,
DDP_COMPONENT_RDMA0,
DDP_COMPONENT_DSI0,
};
@@ -148,7 +148,7 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_main[] = {
DDP_COMPONENT_CCORR,
DDP_COMPONENT_AAL0,
DDP_COMPONENT_GAMMA,
- DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DITHER0,
DDP_COMPONENT_DSI0,
};
@@ -167,7 +167,7 @@ static const enum mtk_ddp_comp_id mt8192_mtk_ddp_main[] = {
DDP_COMPONENT_AAL0,
DDP_COMPONENT_GAMMA,
DDP_COMPONENT_POSTMASK0,
- DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DITHER0,
DDP_COMPONENT_DSI0,
};
diff --git a/drivers/soc/mediatek/mt8167-mmsys.h b/drivers/soc/mediatek/mt8167-mmsys.h
index 2772ef5e3934..f7a35b3656bb 100644
--- a/drivers/soc/mediatek/mt8167-mmsys.h
+++ b/drivers/soc/mediatek/mt8167-mmsys.h
@@ -18,7 +18,7 @@ static const struct mtk_mmsys_routes mt8167_mmsys_routing_table[] = {
DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
}, {
- DDP_COMPONENT_DITHER, DDP_COMPONENT_RDMA0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_RDMA0,
MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_RDMA0
}, {
DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
diff --git a/drivers/soc/mediatek/mt8183-mmsys.h b/drivers/soc/mediatek/mt8183-mmsys.h
index 0c021f4b76d2..ff6be1703469 100644
--- a/drivers/soc/mediatek/mt8183-mmsys.h
+++ b/drivers/soc/mediatek/mt8183-mmsys.h
@@ -41,7 +41,7 @@ static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1,
MT8183_OVL1_2L_MOUT_EN_RDMA1
}, {
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0,
MT8183_DITHER0_MOUT_IN_DSI0
}, {
diff --git a/drivers/soc/mediatek/mt8186-mmsys.h b/drivers/soc/mediatek/mt8186-mmsys.h
index c72ccf86ea28..eb1ad9c37a9c 100644
--- a/drivers/soc/mediatek/mt8186-mmsys.h
+++ b/drivers/soc/mediatek/mt8186-mmsys.h
@@ -76,12 +76,12 @@ static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = {
MT8186_RDMA0_SOUT_TO_COLOR0
},
{
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK,
MT8186_DITHER0_MOUT_TO_DSI0,
},
{
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK,
MT8186_DSI0_FROM_DITHER0
},
diff --git a/drivers/soc/mediatek/mt8192-mmsys.h b/drivers/soc/mediatek/mt8192-mmsys.h
index 6aae0b12b6ff..a016d80b4bc1 100644
--- a/drivers/soc/mediatek/mt8192-mmsys.h
+++ b/drivers/soc/mediatek/mt8192-mmsys.h
@@ -40,7 +40,7 @@ static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4,
MT8192_OVL2_2L_MOUT_EN_RDMA4
}, {
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0,
MT8192_DITHER0_MOUT_IN_DSI0
}, {
@@ -52,7 +52,7 @@ static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0,
MT8192_AAL0_SEL_IN_CCORR0
}, {
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0,
MT8192_DSI0_SEL_IN_DITHER0
}, {
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
new file mode 100644
index 000000000000..abfe94a30248
--- /dev/null
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -0,0 +1,370 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
+#define __SOC_MEDIATEK_MT8195_MMSYS_H
+
+#define MT8195_VDO0_OVL_MOUT_EN 0xf14
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0)
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1)
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(4)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(5)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6)
+
+#define MT8195_VDO0_SEL_IN 0xf34
+#define MT8195_SEL_IN_VPP_MERGE_FROM_MASK GENMASK(1, 0)
+#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0)
+#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 << 0)
+#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << 0)
+#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK GENMASK(4, 4)
+#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 << 4)
+#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << 4)
+#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK GENMASK(5, 5)
+#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 (0 << 5)
+#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 << 5)
+#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK GENMASK(8, 8)
+#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << 8)
+#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT (1 << 8)
+#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK GENMASK(9, 9)
+#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT (0 << 9)
+#define MT8195_SEL_IN_DP_INTF0_FROM_MASK GENMASK(13, 12)
+#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 << 0)
+#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 12)
+#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 << 12)
+#define MT8195_SEL_IN_DSI0_FROM_MASK GENMASK(16, 16)
+#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT (0 << 16)
+#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << 16)
+#define MT8195_SEL_IN_DSI1_FROM_MASK GENMASK(17, 17)
+#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT (0 << 17)
+#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE (1 << 17)
+#define MT8195_SEL_IN_DISP_WDMA1_FROM_MASK GENMASK(20, 20)
+#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 (0 << 20)
+#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE (1 << 20)
+#define MT8195_SEL_IN_DSC_WRAP1_FROM_MASK GENMASK(21, 21)
+#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN (0 << 21)
+#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 (1 << 21)
+#define MT8195_SEL_IN_DISP_WDMA0_FROM_MASK GENMASK(22, 22)
+#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 (0 << 22)
+
+#define MT8195_VDO0_SEL_OUT 0xf38
+#define MT8195_SOUT_DISP_DITHER0_TO_MASK BIT(0)
+#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0)
+#define MT8195_SOUT_DISP_DITHER0_TO_DSI0 (1 << 0)
+#define MT8195_SOUT_DISP_DITHER1_TO_MASK GENMASK(2, 1)
+#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 << 1)
+#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE (1 << 1)
+#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT (2 << 1)
+#define MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK GENMASK(4, 4)
+#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE (0 << 4)
+#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 (1 << 4)
+#define MT8195_SOUT_VPP_MERGE_TO_MASK GENMASK(10, 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DSI1 (0 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 (1 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 (2 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1 (3 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN (4 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK GENMASK(11, 11)
+#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN (0 << 11)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK GENMASK(13, 12)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 (0 << 12)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 (1 << 12)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE (2 << 12)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK GENMASK(17, 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 (0 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 (1 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16)
+
+static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
+ {
+ DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
+ MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0,
+ MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
+ }, {
+ DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
+ MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0,
+ MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0
+ }, {
+ DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL1,
+ MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1,
+ MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1
+ }, {
+ DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
+ MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1,
+ MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1
+ }, {
+ DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
+ MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1,
+ MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1
+ }, {
+ DDP_COMPONENT_OVL1, DDP_COMPONENT_OVL0,
+ MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0,
+ MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
+ MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
+ MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
+ MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0
+ }, {
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
+ MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
+ MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
+ MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
+ MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
+ }, {
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
+ MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
+ MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
+ MT8195_SEL_IN_DSI1_FROM_VPP_MERGE
+ }, {
+ DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
+ MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
+ MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
+ }, {
+ DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,
+ MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
+ }, {
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
+ MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
+ }, {
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
+ MT8195_SOUT_DISP_DITHER0_TO_DSI0
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+ MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+ MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+ MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+ MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+ MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+ MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+ MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
+ MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
+ MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+ MT8195_SOUT_VPP_MERGE_TO_DSI1
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+ MT8195_SOUT_VPP_MERGE_TO_DP_INTF0
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+ MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+ MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+ MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+ MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+ MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK,
+ MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE
+ }
+};
+
+#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
diff --git a/drivers/soc/mediatek/mt8365-mmsys.h b/drivers/soc/mediatek/mt8365-mmsys.h
index 690e3fe2dee0..24129a6c25f8 100644
--- a/drivers/soc/mediatek/mt8365-mmsys.h
+++ b/drivers/soc/mediatek/mt8365-mmsys.h
@@ -41,12 +41,12 @@ static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = {
MT8365_DISP_COLOR_SEL_IN_COLOR0,MT8365_DISP_COLOR_SEL_IN_COLOR0
},
{
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN,
MT8365_DITHER_MOUT_EN_DSI0, MT8365_DITHER_MOUT_EN_DSI0
},
{
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN,
MT8365_DSI0_SEL_IN_DITHER, MT8365_DSI0_SEL_IN_DITHER
},
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 4fc4c2c9ea20..b2fa239c5f5f 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -4,6 +4,8 @@
* Author: James Liao <jamesjj.liao@mediatek.com>
*/
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/io.h>
@@ -17,6 +19,7 @@
#include "mt8183-mmsys.h"
#include "mt8186-mmsys.h"
#include "mt8192-mmsys.h"
+#include "mt8195-mmsys.h"
#include "mt8365-mmsys.h"
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
@@ -72,12 +75,24 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
.num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
};
+static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
+ .clk_name = "cfg_vdo0",
+ .clk_driver = "clk-mt8195-vdo0",
+ .routes = mmsys_mt8195_routing_table,
+ .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
+};
+
static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
.clk_driver = "clk-mt8365-mm",
.routes = mt8365_mmsys_routing_table,
.num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
};
+static const struct of_device_id mtk_clk_platform_labels[] = {
+ { .compatible = "mediatek,mt8195-mmsys",
+ .data = (void *)"clk-mt8195"},
+};
+
struct mtk_mmsys {
void __iomem *regs;
const struct mtk_mmsys_driver_data *data;
@@ -85,6 +100,45 @@ struct mtk_mmsys {
struct reset_controller_dev rcdev;
};
+static int mtk_mmsys_get_match_data_by_clk_name(const struct mtk_mmsys_driver_data **data,
+ struct device *dev)
+{
+ int i;
+ struct clk *clk;
+ const char *clk_name;
+ const struct of_device_id *of_id = of_match_node(mtk_clk_platform_labels,
+ dev->of_node);
+ const struct mtk_mmsys_driver_data *drvdata[] = {
+ &mt8195_vdosys0_driver_data,
+ };
+
+ if (!of_id || !of_id->data) {
+ dev_err(dev, "Can't find match clk platform labels\n");
+ return -EINVAL;
+ }
+
+ clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(clk)) {
+ dev_err(dev, "failed to get mmsys clk\n");
+ return PTR_ERR(clk);
+ }
+
+ clk_name = __clk_get_name(clk);
+ if (!clk_name) {
+ dev_err(dev, "invalid mmsys clk name\n");
+ return -EINVAL;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(drvdata); i++)
+ if (strncmp(drvdata[i]->clk_name, clk_name, strlen(clk_name)) == 0 &&
+ strncmp(drvdata[i]->clk_driver, of_id->data, strlen(of_id->data)) == 0) {
+ *data = drvdata[i];
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next)
@@ -206,6 +260,11 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
}
mmsys->data = of_device_get_match_data(&pdev->dev);
+ if (!mmsys->data && mtk_mmsys_get_match_data_by_clk_name(&mmsys->data, dev) < 0) {
+ dev_err(dev, "Couldn't get match driver data\n");
+ return -EINVAL;
+ }
+
platform_set_drvdata(pdev, mmsys);
clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
@@ -260,6 +319,9 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
.compatible = "mediatek,mt8192-mmsys",
.data = &mt8192_mmsys_driver_data,
},
+ {
+ .compatible = "mediatek,mt8195-mmsys",
+ },
{
.compatible = "mediatek,mt8365-mmsys",
.data = &mt8365_mmsys_driver_data,
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 77f37f8c715b..b119af6646bf 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -87,6 +87,7 @@ struct mtk_mmsys_routes {
};
struct mtk_mmsys_driver_data {
+ const char *clk_name;
const char *clk_driver;
const struct mtk_mmsys_routes *routes;
const unsigned int num_routes;
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index aaf8fc1abb43..d9790140cfa9 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -200,7 +200,7 @@ static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR,
[DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR,
- [DDP_COMPONENT_DITHER] = MT8167_MUTEX_MOD_DISP_DITHER,
+ [DDP_COMPONENT_DITHER0] = MT8167_MUTEX_MOD_DISP_DITHER,
[DDP_COMPONENT_GAMMA] = MT8167_MUTEX_MOD_DISP_GAMMA,
[DDP_COMPONENT_OVL0] = MT8167_MUTEX_MOD_DISP_OVL0,
[DDP_COMPONENT_OVL1] = MT8167_MUTEX_MOD_DISP_OVL1,
@@ -233,7 +233,7 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
[DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
- [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0,
+ [DDP_COMPONENT_DITHER0] = MT8183_MUTEX_MOD_DISP_DITHER0,
[DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
[DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
[DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
@@ -247,7 +247,7 @@ static const unsigned int mt8186_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8186_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8186_MUTEX_MOD_DISP_CCORR0,
[DDP_COMPONENT_COLOR0] = MT8186_MUTEX_MOD_DISP_COLOR0,
- [DDP_COMPONENT_DITHER] = MT8186_MUTEX_MOD_DISP_DITHER0,
+ [DDP_COMPONENT_DITHER0] = MT8186_MUTEX_MOD_DISP_DITHER0,
[DDP_COMPONENT_GAMMA] = MT8186_MUTEX_MOD_DISP_GAMMA0,
[DDP_COMPONENT_OVL0] = MT8186_MUTEX_MOD_DISP_OVL0,
[DDP_COMPONENT_OVL_2L0] = MT8186_MUTEX_MOD_DISP_OVL0_2L,
@@ -260,7 +260,7 @@ static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
[DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0,
- [DDP_COMPONENT_DITHER] = MT8192_MUTEX_MOD_DISP_DITHER0,
+ [DDP_COMPONENT_DITHER0] = MT8192_MUTEX_MOD_DISP_DITHER0,
[DDP_COMPONENT_GAMMA] = MT8192_MUTEX_MOD_DISP_GAMMA0,
[DDP_COMPONENT_POSTMASK0] = MT8192_MUTEX_MOD_DISP_POSTMASK0,
[DDP_COMPONENT_OVL0] = MT8192_MUTEX_MOD_DISP_OVL0,
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 4bba275e235a..fb719fd1281c 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -16,14 +16,25 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_CCORR,
DDP_COMPONENT_COLOR0,
DDP_COMPONENT_COLOR1,
- DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DITHER0,
+ DDP_COMPONENT_DITHER1,
+ DDP_COMPONENT_DP_INTF0,
+ DDP_COMPONENT_DP_INTF1,
DDP_COMPONENT_DPI0,
DDP_COMPONENT_DPI1,
+ DDP_COMPONENT_DSC0,
+ DDP_COMPONENT_DSC1,
DDP_COMPONENT_DSI0,
DDP_COMPONENT_DSI1,
DDP_COMPONENT_DSI2,
DDP_COMPONENT_DSI3,
DDP_COMPONENT_GAMMA,
+ DDP_COMPONENT_MERGE0,
+ DDP_COMPONENT_MERGE1,
+ DDP_COMPONENT_MERGE2,
+ DDP_COMPONENT_MERGE3,
+ DDP_COMPONENT_MERGE4,
+ DDP_COMPONENT_MERGE5,
DDP_COMPONENT_OD0,
DDP_COMPONENT_OD1,
DDP_COMPONENT_OVL0,
--
2.18.0
_______________________________________________
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Linux-mediatek@lists.infradead.org
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^ permalink raw reply related [flat|nested] 49+ messages in thread
* [RESEND v17 3/7] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
@ 2022-04-07 3:04 ` jason-jh.lin
0 siblings, 0 replies; 49+ messages in thread
From: jason-jh.lin @ 2022-04-07 3:04 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: Philipp Zabel, Maxime Coquelin, David Airlie, Daniel Vetter,
Alexandre Torgue, John 'Warthog9' Hawley, postmaster,
jason-jh . lin, hsinyi, fshao, moudy.ho, roy-cw.yeh, CK Hu,
Fabien Parent, nancy.lin, singo.chang, devicetree, linux-stm32,
linux-arm-kernel, linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group
1. Add mt8195 mmsys compatible for vdosys0.
2. Add mt8195 routing table settings and fix build fail.
3. Add clock name, clock driver name and routing table into the driver data
of mt8195 vdosys0.
4. Add get match data by clock name function and clock platform labels
to identify which mmsys node is corresponding to vdosys0.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 6 +-
drivers/soc/mediatek/mt8167-mmsys.h | 2 +-
drivers/soc/mediatek/mt8183-mmsys.h | 2 +-
drivers/soc/mediatek/mt8186-mmsys.h | 4 +-
drivers/soc/mediatek/mt8192-mmsys.h | 4 +-
drivers/soc/mediatek/mt8195-mmsys.h | 370 ++++++++++++++++++++
drivers/soc/mediatek/mt8365-mmsys.h | 4 +-
drivers/soc/mediatek/mtk-mmsys.c | 62 ++++
drivers/soc/mediatek/mtk-mmsys.h | 1 +
drivers/soc/mediatek/mtk-mutex.c | 8 +-
include/linux/soc/mediatek/mtk-mmsys.h | 13 +-
12 files changed, 461 insertions(+), 17 deletions(-)
create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 2e99aee13dfe..f543d3eb9439 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -366,7 +366,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr },
[DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color },
[DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color },
- [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither },
+ [DDP_COMPONENT_DITHER0] = { MTK_DISP_DITHER, 0, &ddp_dither },
[DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi },
[DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi },
[DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi },
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 247c6ff277ef..6a0a167320f0 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -116,7 +116,7 @@ static enum mtk_ddp_comp_id mt8167_mtk_ddp_main[] = {
DDP_COMPONENT_CCORR,
DDP_COMPONENT_AAL0,
DDP_COMPONENT_GAMMA,
- DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DITHER0,
DDP_COMPONENT_RDMA0,
DDP_COMPONENT_DSI0,
};
@@ -148,7 +148,7 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_main[] = {
DDP_COMPONENT_CCORR,
DDP_COMPONENT_AAL0,
DDP_COMPONENT_GAMMA,
- DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DITHER0,
DDP_COMPONENT_DSI0,
};
@@ -167,7 +167,7 @@ static const enum mtk_ddp_comp_id mt8192_mtk_ddp_main[] = {
DDP_COMPONENT_AAL0,
DDP_COMPONENT_GAMMA,
DDP_COMPONENT_POSTMASK0,
- DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DITHER0,
DDP_COMPONENT_DSI0,
};
diff --git a/drivers/soc/mediatek/mt8167-mmsys.h b/drivers/soc/mediatek/mt8167-mmsys.h
index 2772ef5e3934..f7a35b3656bb 100644
--- a/drivers/soc/mediatek/mt8167-mmsys.h
+++ b/drivers/soc/mediatek/mt8167-mmsys.h
@@ -18,7 +18,7 @@ static const struct mtk_mmsys_routes mt8167_mmsys_routing_table[] = {
DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
}, {
- DDP_COMPONENT_DITHER, DDP_COMPONENT_RDMA0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_RDMA0,
MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_RDMA0
}, {
DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
diff --git a/drivers/soc/mediatek/mt8183-mmsys.h b/drivers/soc/mediatek/mt8183-mmsys.h
index 0c021f4b76d2..ff6be1703469 100644
--- a/drivers/soc/mediatek/mt8183-mmsys.h
+++ b/drivers/soc/mediatek/mt8183-mmsys.h
@@ -41,7 +41,7 @@ static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1,
MT8183_OVL1_2L_MOUT_EN_RDMA1
}, {
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0,
MT8183_DITHER0_MOUT_IN_DSI0
}, {
diff --git a/drivers/soc/mediatek/mt8186-mmsys.h b/drivers/soc/mediatek/mt8186-mmsys.h
index c72ccf86ea28..eb1ad9c37a9c 100644
--- a/drivers/soc/mediatek/mt8186-mmsys.h
+++ b/drivers/soc/mediatek/mt8186-mmsys.h
@@ -76,12 +76,12 @@ static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = {
MT8186_RDMA0_SOUT_TO_COLOR0
},
{
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK,
MT8186_DITHER0_MOUT_TO_DSI0,
},
{
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK,
MT8186_DSI0_FROM_DITHER0
},
diff --git a/drivers/soc/mediatek/mt8192-mmsys.h b/drivers/soc/mediatek/mt8192-mmsys.h
index 6aae0b12b6ff..a016d80b4bc1 100644
--- a/drivers/soc/mediatek/mt8192-mmsys.h
+++ b/drivers/soc/mediatek/mt8192-mmsys.h
@@ -40,7 +40,7 @@ static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4,
MT8192_OVL2_2L_MOUT_EN_RDMA4
}, {
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0,
MT8192_DITHER0_MOUT_IN_DSI0
}, {
@@ -52,7 +52,7 @@ static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0,
MT8192_AAL0_SEL_IN_CCORR0
}, {
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0,
MT8192_DSI0_SEL_IN_DITHER0
}, {
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
new file mode 100644
index 000000000000..abfe94a30248
--- /dev/null
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -0,0 +1,370 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
+#define __SOC_MEDIATEK_MT8195_MMSYS_H
+
+#define MT8195_VDO0_OVL_MOUT_EN 0xf14
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0)
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1)
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(4)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(5)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6)
+
+#define MT8195_VDO0_SEL_IN 0xf34
+#define MT8195_SEL_IN_VPP_MERGE_FROM_MASK GENMASK(1, 0)
+#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0)
+#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 << 0)
+#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << 0)
+#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK GENMASK(4, 4)
+#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 << 4)
+#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << 4)
+#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK GENMASK(5, 5)
+#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 (0 << 5)
+#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 << 5)
+#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK GENMASK(8, 8)
+#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << 8)
+#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT (1 << 8)
+#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK GENMASK(9, 9)
+#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT (0 << 9)
+#define MT8195_SEL_IN_DP_INTF0_FROM_MASK GENMASK(13, 12)
+#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 << 0)
+#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 12)
+#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 << 12)
+#define MT8195_SEL_IN_DSI0_FROM_MASK GENMASK(16, 16)
+#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT (0 << 16)
+#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << 16)
+#define MT8195_SEL_IN_DSI1_FROM_MASK GENMASK(17, 17)
+#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT (0 << 17)
+#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE (1 << 17)
+#define MT8195_SEL_IN_DISP_WDMA1_FROM_MASK GENMASK(20, 20)
+#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 (0 << 20)
+#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE (1 << 20)
+#define MT8195_SEL_IN_DSC_WRAP1_FROM_MASK GENMASK(21, 21)
+#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN (0 << 21)
+#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 (1 << 21)
+#define MT8195_SEL_IN_DISP_WDMA0_FROM_MASK GENMASK(22, 22)
+#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 (0 << 22)
+
+#define MT8195_VDO0_SEL_OUT 0xf38
+#define MT8195_SOUT_DISP_DITHER0_TO_MASK BIT(0)
+#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0)
+#define MT8195_SOUT_DISP_DITHER0_TO_DSI0 (1 << 0)
+#define MT8195_SOUT_DISP_DITHER1_TO_MASK GENMASK(2, 1)
+#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 << 1)
+#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE (1 << 1)
+#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT (2 << 1)
+#define MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK GENMASK(4, 4)
+#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE (0 << 4)
+#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 (1 << 4)
+#define MT8195_SOUT_VPP_MERGE_TO_MASK GENMASK(10, 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DSI1 (0 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 (1 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 (2 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1 (3 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN (4 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK GENMASK(11, 11)
+#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN (0 << 11)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK GENMASK(13, 12)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 (0 << 12)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 (1 << 12)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE (2 << 12)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK GENMASK(17, 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 (0 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 (1 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16)
+
+static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
+ {
+ DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
+ MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0,
+ MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
+ }, {
+ DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
+ MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0,
+ MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0
+ }, {
+ DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL1,
+ MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1,
+ MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1
+ }, {
+ DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
+ MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1,
+ MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1
+ }, {
+ DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
+ MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1,
+ MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1
+ }, {
+ DDP_COMPONENT_OVL1, DDP_COMPONENT_OVL0,
+ MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0,
+ MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
+ MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
+ MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
+ MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0
+ }, {
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
+ MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
+ MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
+ MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
+ MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
+ }, {
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
+ MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
+ MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
+ MT8195_SEL_IN_DSI1_FROM_VPP_MERGE
+ }, {
+ DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
+ MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
+ MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
+ }, {
+ DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,
+ MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
+ }, {
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
+ MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
+ }, {
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
+ MT8195_SOUT_DISP_DITHER0_TO_DSI0
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+ MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+ MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+ MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+ MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+ MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+ MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+ MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
+ MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
+ MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+ MT8195_SOUT_VPP_MERGE_TO_DSI1
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+ MT8195_SOUT_VPP_MERGE_TO_DP_INTF0
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+ MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+ MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+ MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+ MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+ MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK,
+ MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE
+ }
+};
+
+#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
diff --git a/drivers/soc/mediatek/mt8365-mmsys.h b/drivers/soc/mediatek/mt8365-mmsys.h
index 690e3fe2dee0..24129a6c25f8 100644
--- a/drivers/soc/mediatek/mt8365-mmsys.h
+++ b/drivers/soc/mediatek/mt8365-mmsys.h
@@ -41,12 +41,12 @@ static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = {
MT8365_DISP_COLOR_SEL_IN_COLOR0,MT8365_DISP_COLOR_SEL_IN_COLOR0
},
{
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN,
MT8365_DITHER_MOUT_EN_DSI0, MT8365_DITHER_MOUT_EN_DSI0
},
{
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN,
MT8365_DSI0_SEL_IN_DITHER, MT8365_DSI0_SEL_IN_DITHER
},
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 4fc4c2c9ea20..b2fa239c5f5f 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -4,6 +4,8 @@
* Author: James Liao <jamesjj.liao@mediatek.com>
*/
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/io.h>
@@ -17,6 +19,7 @@
#include "mt8183-mmsys.h"
#include "mt8186-mmsys.h"
#include "mt8192-mmsys.h"
+#include "mt8195-mmsys.h"
#include "mt8365-mmsys.h"
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
@@ -72,12 +75,24 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
.num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
};
+static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
+ .clk_name = "cfg_vdo0",
+ .clk_driver = "clk-mt8195-vdo0",
+ .routes = mmsys_mt8195_routing_table,
+ .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
+};
+
static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
.clk_driver = "clk-mt8365-mm",
.routes = mt8365_mmsys_routing_table,
.num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
};
+static const struct of_device_id mtk_clk_platform_labels[] = {
+ { .compatible = "mediatek,mt8195-mmsys",
+ .data = (void *)"clk-mt8195"},
+};
+
struct mtk_mmsys {
void __iomem *regs;
const struct mtk_mmsys_driver_data *data;
@@ -85,6 +100,45 @@ struct mtk_mmsys {
struct reset_controller_dev rcdev;
};
+static int mtk_mmsys_get_match_data_by_clk_name(const struct mtk_mmsys_driver_data **data,
+ struct device *dev)
+{
+ int i;
+ struct clk *clk;
+ const char *clk_name;
+ const struct of_device_id *of_id = of_match_node(mtk_clk_platform_labels,
+ dev->of_node);
+ const struct mtk_mmsys_driver_data *drvdata[] = {
+ &mt8195_vdosys0_driver_data,
+ };
+
+ if (!of_id || !of_id->data) {
+ dev_err(dev, "Can't find match clk platform labels\n");
+ return -EINVAL;
+ }
+
+ clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(clk)) {
+ dev_err(dev, "failed to get mmsys clk\n");
+ return PTR_ERR(clk);
+ }
+
+ clk_name = __clk_get_name(clk);
+ if (!clk_name) {
+ dev_err(dev, "invalid mmsys clk name\n");
+ return -EINVAL;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(drvdata); i++)
+ if (strncmp(drvdata[i]->clk_name, clk_name, strlen(clk_name)) == 0 &&
+ strncmp(drvdata[i]->clk_driver, of_id->data, strlen(of_id->data)) == 0) {
+ *data = drvdata[i];
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next)
@@ -206,6 +260,11 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
}
mmsys->data = of_device_get_match_data(&pdev->dev);
+ if (!mmsys->data && mtk_mmsys_get_match_data_by_clk_name(&mmsys->data, dev) < 0) {
+ dev_err(dev, "Couldn't get match driver data\n");
+ return -EINVAL;
+ }
+
platform_set_drvdata(pdev, mmsys);
clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
@@ -260,6 +319,9 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
.compatible = "mediatek,mt8192-mmsys",
.data = &mt8192_mmsys_driver_data,
},
+ {
+ .compatible = "mediatek,mt8195-mmsys",
+ },
{
.compatible = "mediatek,mt8365-mmsys",
.data = &mt8365_mmsys_driver_data,
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 77f37f8c715b..b119af6646bf 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -87,6 +87,7 @@ struct mtk_mmsys_routes {
};
struct mtk_mmsys_driver_data {
+ const char *clk_name;
const char *clk_driver;
const struct mtk_mmsys_routes *routes;
const unsigned int num_routes;
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index aaf8fc1abb43..d9790140cfa9 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -200,7 +200,7 @@ static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR,
[DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR,
- [DDP_COMPONENT_DITHER] = MT8167_MUTEX_MOD_DISP_DITHER,
+ [DDP_COMPONENT_DITHER0] = MT8167_MUTEX_MOD_DISP_DITHER,
[DDP_COMPONENT_GAMMA] = MT8167_MUTEX_MOD_DISP_GAMMA,
[DDP_COMPONENT_OVL0] = MT8167_MUTEX_MOD_DISP_OVL0,
[DDP_COMPONENT_OVL1] = MT8167_MUTEX_MOD_DISP_OVL1,
@@ -233,7 +233,7 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
[DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
- [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0,
+ [DDP_COMPONENT_DITHER0] = MT8183_MUTEX_MOD_DISP_DITHER0,
[DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
[DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
[DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
@@ -247,7 +247,7 @@ static const unsigned int mt8186_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8186_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8186_MUTEX_MOD_DISP_CCORR0,
[DDP_COMPONENT_COLOR0] = MT8186_MUTEX_MOD_DISP_COLOR0,
- [DDP_COMPONENT_DITHER] = MT8186_MUTEX_MOD_DISP_DITHER0,
+ [DDP_COMPONENT_DITHER0] = MT8186_MUTEX_MOD_DISP_DITHER0,
[DDP_COMPONENT_GAMMA] = MT8186_MUTEX_MOD_DISP_GAMMA0,
[DDP_COMPONENT_OVL0] = MT8186_MUTEX_MOD_DISP_OVL0,
[DDP_COMPONENT_OVL_2L0] = MT8186_MUTEX_MOD_DISP_OVL0_2L,
@@ -260,7 +260,7 @@ static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
[DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0,
- [DDP_COMPONENT_DITHER] = MT8192_MUTEX_MOD_DISP_DITHER0,
+ [DDP_COMPONENT_DITHER0] = MT8192_MUTEX_MOD_DISP_DITHER0,
[DDP_COMPONENT_GAMMA] = MT8192_MUTEX_MOD_DISP_GAMMA0,
[DDP_COMPONENT_POSTMASK0] = MT8192_MUTEX_MOD_DISP_POSTMASK0,
[DDP_COMPONENT_OVL0] = MT8192_MUTEX_MOD_DISP_OVL0,
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 4bba275e235a..fb719fd1281c 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -16,14 +16,25 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_CCORR,
DDP_COMPONENT_COLOR0,
DDP_COMPONENT_COLOR1,
- DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DITHER0,
+ DDP_COMPONENT_DITHER1,
+ DDP_COMPONENT_DP_INTF0,
+ DDP_COMPONENT_DP_INTF1,
DDP_COMPONENT_DPI0,
DDP_COMPONENT_DPI1,
+ DDP_COMPONENT_DSC0,
+ DDP_COMPONENT_DSC1,
DDP_COMPONENT_DSI0,
DDP_COMPONENT_DSI1,
DDP_COMPONENT_DSI2,
DDP_COMPONENT_DSI3,
DDP_COMPONENT_GAMMA,
+ DDP_COMPONENT_MERGE0,
+ DDP_COMPONENT_MERGE1,
+ DDP_COMPONENT_MERGE2,
+ DDP_COMPONENT_MERGE3,
+ DDP_COMPONENT_MERGE4,
+ DDP_COMPONENT_MERGE5,
DDP_COMPONENT_OD0,
DDP_COMPONENT_OD1,
DDP_COMPONENT_OVL0,
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [RESEND v17 4/7] soc: mediatek: add mtk-mutex support for mt8195 vdosys0
2022-04-07 3:04 ` jason-jh.lin
@ 2022-04-07 3:04 ` jason-jh.lin
-1 siblings, 0 replies; 49+ messages in thread
From: jason-jh.lin @ 2022-04-07 3:04 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: David Airlie, singo.chang, Alexandre Torgue, postmaster,
Fabien Parent, John 'Warthog9' Hawley, linux-stm32,
roy-cw.yeh, Project_Global_Chrome_Upstream_Group, CK Hu,
Philipp Zabel, devicetree, Daniel Vetter, nancy.lin,
linux-mediatek, hsinyi, linux-arm-kernel, jason-jh . lin,
linux-kernel, moudy.ho, Maxime Coquelin
Add mtk-mutex support for mt8195 vdosys0.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Fei Shao <fshao@chromium.org>
---
drivers/soc/mediatek/mtk-mutex.c | 87 ++++++++++++++++++++++++++++++--
1 file changed, 84 insertions(+), 3 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index d9790140cfa9..9184684baf1d 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -17,6 +17,9 @@
#define MT8183_MUTEX0_MOD0 0x30
#define MT8183_MUTEX0_SOF0 0x2c
+#define MT8195_DISP_MUTEX0_MOD0 0x30
+#define MT8195_DISP_MUTEX0_SOF 0x2c
+
#define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
#define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
#define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
@@ -96,6 +99,20 @@
#define MT8173_MUTEX_MOD_DISP_PWM1 24
#define MT8173_MUTEX_MOD_DISP_OD 25
+#define MT8195_MUTEX_MOD_DISP_OVL0 0
+#define MT8195_MUTEX_MOD_DISP_WDMA0 1
+#define MT8195_MUTEX_MOD_DISP_RDMA0 2
+#define MT8195_MUTEX_MOD_DISP_COLOR0 3
+#define MT8195_MUTEX_MOD_DISP_CCORR0 4
+#define MT8195_MUTEX_MOD_DISP_AAL0 5
+#define MT8195_MUTEX_MOD_DISP_GAMMA0 6
+#define MT8195_MUTEX_MOD_DISP_DITHER0 7
+#define MT8195_MUTEX_MOD_DISP_DSI0 8
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
+#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20
+#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21
+#define MT8195_MUTEX_MOD_DISP_PWM0 27
+
#define MT2712_MUTEX_MOD_DISP_PWM2 10
#define MT2712_MUTEX_MOD_DISP_OVL0 11
#define MT2712_MUTEX_MOD_DISP_OVL1 12
@@ -132,9 +149,21 @@
#define MT8167_MUTEX_SOF_DPI1 3
#define MT8183_MUTEX_SOF_DSI0 1
#define MT8183_MUTEX_SOF_DPI0 2
+#define MT8195_MUTEX_SOF_DSI0 1
+#define MT8195_MUTEX_SOF_DSI1 2
+#define MT8195_MUTEX_SOF_DP_INTF0 3
+#define MT8195_MUTEX_SOF_DP_INTF1 4
+#define MT8195_MUTEX_SOF_DPI0 6 /* for HDMI_TX */
+#define MT8195_MUTEX_SOF_DPI1 5 /* for digital video out */
#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6)
#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
+#define MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_SOF_DSI0 << 7)
+#define MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_SOF_DSI1 << 7)
+#define MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_INTF0 << 7)
+#define MT8195_MUTEX_EOF_DP_INTF1 (MT8195_MUTEX_SOF_DP_INTF1 << 7)
+#define MT8195_MUTEX_EOF_DPI0 (MT8195_MUTEX_SOF_DPI0 << 7)
+#define MT8195_MUTEX_EOF_DPI1 (MT8195_MUTEX_SOF_DPI1 << 7)
struct mtk_mutex {
int id;
@@ -149,6 +178,9 @@ enum mtk_mutex_sof_id {
MUTEX_SOF_DPI1,
MUTEX_SOF_DSI2,
MUTEX_SOF_DSI3,
+ MUTEX_SOF_DP_INTF0,
+ MUTEX_SOF_DP_INTF1,
+ DDP_MUTEX_SOF_MAX,
};
struct mtk_mutex_data {
@@ -270,7 +302,23 @@ static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4,
};
-static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+ [DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
+ [DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
+ [DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
+ [DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0,
+ [DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
+ [DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
+ [DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
+ [DDP_COMPONENT_DITHER0] = MT8195_MUTEX_MOD_DISP_DITHER0,
+ [DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
+ [DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
+ [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
+ [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
+ [DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0,
+};
+
+static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
[MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
@@ -280,7 +328,7 @@ static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
[MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
};
-static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = {
[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
[MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
@@ -288,7 +336,7 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
};
/* Add EOF setting so overlay hardware can receive frame done irq */
-static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = {
[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
[MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
@@ -300,6 +348,26 @@ static const unsigned int mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
[MUTEX_SOF_DPI0] = MT8186_MUTEX_SOF_DPI0 | MT8186_MUTEX_EOF_DPI0,
};
+/*
+ * To support refresh mode(video mode), DISP_REG_MUTEX_SOF should
+ * select the EOF source and configure the EOF plus timing from the
+ * module that provides the timing signal.
+ * So that MUTEX can not only send a STREAM_DONE event to GCE
+ * but also detect the error at end of frame(EAEOF) when EOF signal
+ * arrives.
+ */
+static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
+ [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
+ [MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0,
+ [MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1,
+ [MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0,
+ [MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1,
+ [MUTEX_SOF_DP_INTF0] =
+ MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0,
+ [MUTEX_SOF_DP_INTF1] =
+ MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1,
+};
+
static const struct mtk_mutex_data mt2701_mutex_driver_data = {
.mutex_mod = mt2701_mutex_mod,
.mutex_sof = mt2712_mutex_sof,
@@ -351,6 +419,13 @@ static const struct mtk_mutex_data mt8192_mutex_driver_data = {
.mutex_sof_reg = MT8183_MUTEX0_SOF0,
};
+static const struct mtk_mutex_data mt8195_mutex_driver_data = {
+ .mutex_mod = mt8195_mutex_mod,
+ .mutex_sof = mt8195_mutex_sof,
+ .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
+ .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
+};
+
struct mtk_mutex *mtk_mutex_get(struct device *dev)
{
struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
@@ -423,6 +498,9 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
case DDP_COMPONENT_DPI1:
sof_id = MUTEX_SOF_DPI1;
break;
+ case DDP_COMPONENT_DP_INTF0:
+ sof_id = MUTEX_SOF_DP_INTF0;
+ break;
default:
if (mtx->data->mutex_mod[id] < 32) {
offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
@@ -462,6 +540,7 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
case DDP_COMPONENT_DSI3:
case DDP_COMPONENT_DPI0:
case DDP_COMPONENT_DPI1:
+ case DDP_COMPONENT_DP_INTF0:
writel_relaxed(MUTEX_SOF_SINGLE_MODE,
mtx->regs +
DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,
@@ -587,6 +666,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
.data = &mt8186_mutex_driver_data},
{ .compatible = "mediatek,mt8192-disp-mutex",
.data = &mt8192_mutex_driver_data},
+ { .compatible = "mediatek,mt8195-disp-mutex",
+ .data = &mt8195_mutex_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [RESEND v17 4/7] soc: mediatek: add mtk-mutex support for mt8195 vdosys0
@ 2022-04-07 3:04 ` jason-jh.lin
0 siblings, 0 replies; 49+ messages in thread
From: jason-jh.lin @ 2022-04-07 3:04 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: Philipp Zabel, Maxime Coquelin, David Airlie, Daniel Vetter,
Alexandre Torgue, John 'Warthog9' Hawley, postmaster,
jason-jh . lin, hsinyi, fshao, moudy.ho, roy-cw.yeh, CK Hu,
Fabien Parent, nancy.lin, singo.chang, devicetree, linux-stm32,
linux-arm-kernel, linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group
Add mtk-mutex support for mt8195 vdosys0.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Fei Shao <fshao@chromium.org>
---
drivers/soc/mediatek/mtk-mutex.c | 87 ++++++++++++++++++++++++++++++--
1 file changed, 84 insertions(+), 3 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index d9790140cfa9..9184684baf1d 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -17,6 +17,9 @@
#define MT8183_MUTEX0_MOD0 0x30
#define MT8183_MUTEX0_SOF0 0x2c
+#define MT8195_DISP_MUTEX0_MOD0 0x30
+#define MT8195_DISP_MUTEX0_SOF 0x2c
+
#define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
#define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
#define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
@@ -96,6 +99,20 @@
#define MT8173_MUTEX_MOD_DISP_PWM1 24
#define MT8173_MUTEX_MOD_DISP_OD 25
+#define MT8195_MUTEX_MOD_DISP_OVL0 0
+#define MT8195_MUTEX_MOD_DISP_WDMA0 1
+#define MT8195_MUTEX_MOD_DISP_RDMA0 2
+#define MT8195_MUTEX_MOD_DISP_COLOR0 3
+#define MT8195_MUTEX_MOD_DISP_CCORR0 4
+#define MT8195_MUTEX_MOD_DISP_AAL0 5
+#define MT8195_MUTEX_MOD_DISP_GAMMA0 6
+#define MT8195_MUTEX_MOD_DISP_DITHER0 7
+#define MT8195_MUTEX_MOD_DISP_DSI0 8
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
+#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20
+#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21
+#define MT8195_MUTEX_MOD_DISP_PWM0 27
+
#define MT2712_MUTEX_MOD_DISP_PWM2 10
#define MT2712_MUTEX_MOD_DISP_OVL0 11
#define MT2712_MUTEX_MOD_DISP_OVL1 12
@@ -132,9 +149,21 @@
#define MT8167_MUTEX_SOF_DPI1 3
#define MT8183_MUTEX_SOF_DSI0 1
#define MT8183_MUTEX_SOF_DPI0 2
+#define MT8195_MUTEX_SOF_DSI0 1
+#define MT8195_MUTEX_SOF_DSI1 2
+#define MT8195_MUTEX_SOF_DP_INTF0 3
+#define MT8195_MUTEX_SOF_DP_INTF1 4
+#define MT8195_MUTEX_SOF_DPI0 6 /* for HDMI_TX */
+#define MT8195_MUTEX_SOF_DPI1 5 /* for digital video out */
#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6)
#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
+#define MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_SOF_DSI0 << 7)
+#define MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_SOF_DSI1 << 7)
+#define MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_INTF0 << 7)
+#define MT8195_MUTEX_EOF_DP_INTF1 (MT8195_MUTEX_SOF_DP_INTF1 << 7)
+#define MT8195_MUTEX_EOF_DPI0 (MT8195_MUTEX_SOF_DPI0 << 7)
+#define MT8195_MUTEX_EOF_DPI1 (MT8195_MUTEX_SOF_DPI1 << 7)
struct mtk_mutex {
int id;
@@ -149,6 +178,9 @@ enum mtk_mutex_sof_id {
MUTEX_SOF_DPI1,
MUTEX_SOF_DSI2,
MUTEX_SOF_DSI3,
+ MUTEX_SOF_DP_INTF0,
+ MUTEX_SOF_DP_INTF1,
+ DDP_MUTEX_SOF_MAX,
};
struct mtk_mutex_data {
@@ -270,7 +302,23 @@ static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4,
};
-static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+ [DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
+ [DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
+ [DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
+ [DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0,
+ [DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
+ [DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
+ [DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
+ [DDP_COMPONENT_DITHER0] = MT8195_MUTEX_MOD_DISP_DITHER0,
+ [DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
+ [DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
+ [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
+ [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
+ [DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0,
+};
+
+static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
[MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
@@ -280,7 +328,7 @@ static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
[MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
};
-static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = {
[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
[MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
@@ -288,7 +336,7 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
};
/* Add EOF setting so overlay hardware can receive frame done irq */
-static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = {
[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
[MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
@@ -300,6 +348,26 @@ static const unsigned int mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
[MUTEX_SOF_DPI0] = MT8186_MUTEX_SOF_DPI0 | MT8186_MUTEX_EOF_DPI0,
};
+/*
+ * To support refresh mode(video mode), DISP_REG_MUTEX_SOF should
+ * select the EOF source and configure the EOF plus timing from the
+ * module that provides the timing signal.
+ * So that MUTEX can not only send a STREAM_DONE event to GCE
+ * but also detect the error at end of frame(EAEOF) when EOF signal
+ * arrives.
+ */
+static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
+ [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
+ [MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0,
+ [MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1,
+ [MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0,
+ [MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1,
+ [MUTEX_SOF_DP_INTF0] =
+ MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0,
+ [MUTEX_SOF_DP_INTF1] =
+ MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1,
+};
+
static const struct mtk_mutex_data mt2701_mutex_driver_data = {
.mutex_mod = mt2701_mutex_mod,
.mutex_sof = mt2712_mutex_sof,
@@ -351,6 +419,13 @@ static const struct mtk_mutex_data mt8192_mutex_driver_data = {
.mutex_sof_reg = MT8183_MUTEX0_SOF0,
};
+static const struct mtk_mutex_data mt8195_mutex_driver_data = {
+ .mutex_mod = mt8195_mutex_mod,
+ .mutex_sof = mt8195_mutex_sof,
+ .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
+ .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
+};
+
struct mtk_mutex *mtk_mutex_get(struct device *dev)
{
struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
@@ -423,6 +498,9 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
case DDP_COMPONENT_DPI1:
sof_id = MUTEX_SOF_DPI1;
break;
+ case DDP_COMPONENT_DP_INTF0:
+ sof_id = MUTEX_SOF_DP_INTF0;
+ break;
default:
if (mtx->data->mutex_mod[id] < 32) {
offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
@@ -462,6 +540,7 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
case DDP_COMPONENT_DSI3:
case DDP_COMPONENT_DPI0:
case DDP_COMPONENT_DPI1:
+ case DDP_COMPONENT_DP_INTF0:
writel_relaxed(MUTEX_SOF_SINGLE_MODE,
mtx->regs +
DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,
@@ -587,6 +666,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
.data = &mt8186_mutex_driver_data},
{ .compatible = "mediatek,mt8192-disp-mutex",
.data = &mt8192_mutex_driver_data},
+ { .compatible = "mediatek,mt8195-disp-mutex",
+ .data = &mt8195_mutex_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [RESEND v17 5/7] drm/mediatek: add DSC support for mediatek-drm
2022-04-07 3:04 ` jason-jh.lin
@ 2022-04-07 3:04 ` jason-jh.lin
-1 siblings, 0 replies; 49+ messages in thread
From: jason-jh.lin @ 2022-04-07 3:04 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: David Airlie, singo.chang, Alexandre Torgue, postmaster,
Fabien Parent, John 'Warthog9' Hawley, linux-stm32,
roy-cw.yeh, Project_Global_Chrome_Upstream_Group, CK Hu,
Philipp Zabel, devicetree, Daniel Vetter, nancy.lin,
linux-mediatek, hsinyi, linux-arm-kernel, jason-jh . lin,
linux-kernel, moudy.ho, Maxime Coquelin
DSC is designed for real-time systems with real-time compression,
transmission, decompression and display.
The DSC standard is a specification of the algorithms used for
compressing and decompressing image display streams, including
the specification of the syntax and semantics of the compressed
video bit stream.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 47 +++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
2 files changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index f543d3eb9439..b3d26a05741f 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -40,6 +40,12 @@
#define DITHER_LSB_ERR_SHIFT_G(x) (((x) & 0x7) << 12)
#define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4)
+#define DISP_REG_DSC_CON 0x0000
+#define DSC_EN BIT(0)
+#define DSC_DUAL_INOUT BIT(2)
+#define DSC_BYPASS BIT(4)
+#define DSC_UFOE_SEL BIT(16)
+
#define DISP_REG_OD_EN 0x0000
#define DISP_REG_OD_CFG 0x0020
#define OD_RELAYMODE BIT(0)
@@ -181,6 +187,36 @@ static void mtk_dither_set(struct device *dev, unsigned int bpc,
DISP_DITHERING, cmdq_pkt);
}
+static void mtk_dsc_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+ /* dsc bypass mode */
+ mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg, priv->regs,
+ DISP_REG_DSC_CON, DSC_BYPASS);
+ mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, priv->regs,
+ DISP_REG_DSC_CON, DSC_UFOE_SEL);
+ mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv->cmdq_reg, priv->regs,
+ DISP_REG_DSC_CON, DSC_DUAL_INOUT);
+}
+
+static void mtk_dsc_start(struct device *dev)
+{
+ struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+ /* write with mask to reserve the value set in mtk_dsc_config */
+ mtk_ddp_write_mask(NULL, DSC_EN, &priv->cmdq_reg, priv->regs, DISP_REG_DSC_CON, DSC_EN);
+}
+
+static void mtk_dsc_stop(struct device *dev)
+{
+ struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+ writel_relaxed(0x0, priv->regs + DISP_REG_DSC_CON);
+}
+
static void mtk_od_config(struct device *dev, unsigned int w,
unsigned int h, unsigned int vrefresh,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
@@ -270,6 +306,14 @@ static const struct mtk_ddp_comp_funcs ddp_dpi = {
.stop = mtk_dpi_stop,
};
+static const struct mtk_ddp_comp_funcs ddp_dsc = {
+ .clk_enable = mtk_ddp_clk_enable,
+ .clk_disable = mtk_ddp_clk_disable,
+ .config = mtk_dsc_config,
+ .start = mtk_dsc_start,
+ .stop = mtk_dsc_stop,
+};
+
static const struct mtk_ddp_comp_funcs ddp_dsi = {
.start = mtk_dsi_ddp_start,
.stop = mtk_dsi_ddp_stop,
@@ -339,6 +383,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_CCORR] = "ccorr",
[MTK_DISP_COLOR] = "color",
[MTK_DISP_DITHER] = "dither",
+ [MTK_DISP_DSC] = "dsc",
[MTK_DISP_GAMMA] = "gamma",
[MTK_DISP_MUTEX] = "mutex",
[MTK_DISP_OD] = "od",
@@ -369,6 +414,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_DITHER0] = { MTK_DISP_DITHER, 0, &ddp_dither },
[DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi },
[DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi },
+ [DDP_COMPONENT_DSC0] = { MTK_DISP_DSC, 0, &ddp_dsc },
+ [DDP_COMPONENT_DSC1] = { MTK_DISP_DSC, 1, &ddp_dsc },
[DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi },
[DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi },
[DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index ad267bb8fc9b..763725fe72b3 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -23,6 +23,7 @@ enum mtk_ddp_comp_type {
MTK_DISP_CCORR,
MTK_DISP_COLOR,
MTK_DISP_DITHER,
+ MTK_DISP_DSC,
MTK_DISP_GAMMA,
MTK_DISP_MUTEX,
MTK_DISP_OD,
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [RESEND v17 5/7] drm/mediatek: add DSC support for mediatek-drm
@ 2022-04-07 3:04 ` jason-jh.lin
0 siblings, 0 replies; 49+ messages in thread
From: jason-jh.lin @ 2022-04-07 3:04 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: Philipp Zabel, Maxime Coquelin, David Airlie, Daniel Vetter,
Alexandre Torgue, John 'Warthog9' Hawley, postmaster,
jason-jh . lin, hsinyi, fshao, moudy.ho, roy-cw.yeh, CK Hu,
Fabien Parent, nancy.lin, singo.chang, devicetree, linux-stm32,
linux-arm-kernel, linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group
DSC is designed for real-time systems with real-time compression,
transmission, decompression and display.
The DSC standard is a specification of the algorithms used for
compressing and decompressing image display streams, including
the specification of the syntax and semantics of the compressed
video bit stream.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 47 +++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
2 files changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index f543d3eb9439..b3d26a05741f 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -40,6 +40,12 @@
#define DITHER_LSB_ERR_SHIFT_G(x) (((x) & 0x7) << 12)
#define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4)
+#define DISP_REG_DSC_CON 0x0000
+#define DSC_EN BIT(0)
+#define DSC_DUAL_INOUT BIT(2)
+#define DSC_BYPASS BIT(4)
+#define DSC_UFOE_SEL BIT(16)
+
#define DISP_REG_OD_EN 0x0000
#define DISP_REG_OD_CFG 0x0020
#define OD_RELAYMODE BIT(0)
@@ -181,6 +187,36 @@ static void mtk_dither_set(struct device *dev, unsigned int bpc,
DISP_DITHERING, cmdq_pkt);
}
+static void mtk_dsc_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+ /* dsc bypass mode */
+ mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg, priv->regs,
+ DISP_REG_DSC_CON, DSC_BYPASS);
+ mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, priv->regs,
+ DISP_REG_DSC_CON, DSC_UFOE_SEL);
+ mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv->cmdq_reg, priv->regs,
+ DISP_REG_DSC_CON, DSC_DUAL_INOUT);
+}
+
+static void mtk_dsc_start(struct device *dev)
+{
+ struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+ /* write with mask to reserve the value set in mtk_dsc_config */
+ mtk_ddp_write_mask(NULL, DSC_EN, &priv->cmdq_reg, priv->regs, DISP_REG_DSC_CON, DSC_EN);
+}
+
+static void mtk_dsc_stop(struct device *dev)
+{
+ struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+ writel_relaxed(0x0, priv->regs + DISP_REG_DSC_CON);
+}
+
static void mtk_od_config(struct device *dev, unsigned int w,
unsigned int h, unsigned int vrefresh,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
@@ -270,6 +306,14 @@ static const struct mtk_ddp_comp_funcs ddp_dpi = {
.stop = mtk_dpi_stop,
};
+static const struct mtk_ddp_comp_funcs ddp_dsc = {
+ .clk_enable = mtk_ddp_clk_enable,
+ .clk_disable = mtk_ddp_clk_disable,
+ .config = mtk_dsc_config,
+ .start = mtk_dsc_start,
+ .stop = mtk_dsc_stop,
+};
+
static const struct mtk_ddp_comp_funcs ddp_dsi = {
.start = mtk_dsi_ddp_start,
.stop = mtk_dsi_ddp_stop,
@@ -339,6 +383,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_CCORR] = "ccorr",
[MTK_DISP_COLOR] = "color",
[MTK_DISP_DITHER] = "dither",
+ [MTK_DISP_DSC] = "dsc",
[MTK_DISP_GAMMA] = "gamma",
[MTK_DISP_MUTEX] = "mutex",
[MTK_DISP_OD] = "od",
@@ -369,6 +414,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_DITHER0] = { MTK_DISP_DITHER, 0, &ddp_dither },
[DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi },
[DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi },
+ [DDP_COMPONENT_DSC0] = { MTK_DISP_DSC, 0, &ddp_dsc },
+ [DDP_COMPONENT_DSC1] = { MTK_DISP_DSC, 1, &ddp_dsc },
[DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi },
[DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi },
[DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index ad267bb8fc9b..763725fe72b3 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -23,6 +23,7 @@ enum mtk_ddp_comp_type {
MTK_DISP_CCORR,
MTK_DISP_COLOR,
MTK_DISP_DITHER,
+ MTK_DISP_DSC,
MTK_DISP_GAMMA,
MTK_DISP_MUTEX,
MTK_DISP_OD,
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [RESEND v17 6/7] drm/mediatek: add MERGE support for mediatek-drm
2022-04-07 3:04 ` jason-jh.lin
@ 2022-04-07 3:04 ` jason-jh.lin
-1 siblings, 0 replies; 49+ messages in thread
From: jason-jh.lin @ 2022-04-07 3:04 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: David Airlie, singo.chang, Alexandre Torgue, postmaster,
Fabien Parent, John 'Warthog9' Hawley, linux-stm32,
roy-cw.yeh, Project_Global_Chrome_Upstream_Group, CK Hu,
Philipp Zabel, devicetree, Daniel Vetter, nancy.lin,
linux-mediatek, hsinyi, linux-arm-kernel, jason-jh . lin,
linux-kernel, moudy.ho, Maxime Coquelin
Add MERGE engine file:
MERGE module is used to merge two slice-per-line inputs
into one side-by-side output.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
drivers/gpu/drm/mediatek/Makefile | 1 +
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 246 ++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 16 ++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +-
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
7 files changed, 276 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 29098d7c8307..a38e88e82d12 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -4,6 +4,7 @@ mediatek-drm-y := mtk_disp_aal.o \
mtk_disp_ccorr.o \
mtk_disp_color.o \
mtk_disp_gamma.o \
+ mtk_disp_merge.o \
mtk_disp_ovl.o \
mtk_disp_rdma.o \
mtk_drm_crtc.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 86c3068894b1..a33b13fe2b6e 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -55,6 +55,14 @@ void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state);
void mtk_gamma_start(struct device *dev);
void mtk_gamma_stop(struct device *dev);
+int mtk_merge_clk_enable(struct device *dev);
+void mtk_merge_clk_disable(struct device *dev);
+void mtk_merge_config(struct device *dev, unsigned int width,
+ unsigned int height, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_merge_start(struct device *dev);
+void mtk_merge_stop(struct device *dev);
+
void mtk_ovl_bgclr_in_on(struct device *dev);
void mtk_ovl_bgclr_in_off(struct device *dev);
void mtk_ovl_bypass_shadow(struct device *dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
new file mode 100644
index 000000000000..45face638153
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
@@ -0,0 +1,246 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_drm_drv.h"
+#include "mtk_disp_drv.h"
+
+#define DISP_REG_MERGE_CTRL 0x000
+#define MERGE_EN 1
+#define DISP_REG_MERGE_CFG_0 0x010
+#define DISP_REG_MERGE_CFG_4 0x020
+#define DISP_REG_MERGE_CFG_10 0x038
+/* no swap */
+#define SWAP_MODE 0
+#define FLD_SWAP_MODE GENMASK(4, 0)
+#define DISP_REG_MERGE_CFG_12 0x040
+#define CFG_10_10_1PI_2PO_BUF_MODE 6
+#define CFG_10_10_2PI_2PO_BUF_MODE 8
+#define FLD_CFG_MERGE_MODE GENMASK(4, 0)
+#define DISP_REG_MERGE_CFG_24 0x070
+#define DISP_REG_MERGE_CFG_25 0x074
+#define DISP_REG_MERGE_CFG_36 0x0a0
+#define ULTRA_EN BIT(0)
+#define PREULTRA_EN BIT(4)
+#define DISP_REG_MERGE_CFG_37 0x0a4
+/* 0: Off, 1: SRAM0, 2: SRAM1, 3: SRAM0 + SRAM1 */
+#define BUFFER_MODE 3
+#define FLD_BUFFER_MODE GENMASK(1, 0)
+/*
+ * For the ultra and preultra settings, 6us ~ 9us is experience value
+ * and the maximum frequency of mmsys clock is 594MHz.
+ */
+#define DISP_REG_MERGE_CFG_40 0x0b0
+/* 6 us, 594M pixel/sec */
+#define ULTRA_TH_LOW (6 * 594)
+/* 8 us, 594M pixel/sec */
+#define ULTRA_TH_HIGH (8 * 594)
+#define FLD_ULTRA_TH_LOW GENMASK(15, 0)
+#define FLD_ULTRA_TH_HIGH GENMASK(31, 16)
+#define DISP_REG_MERGE_CFG_41 0x0b4
+/* 8 us, 594M pixel/sec */
+#define PREULTRA_TH_LOW (8 * 594)
+/* 9 us, 594M pixel/sec */
+#define PREULTRA_TH_HIGH (9 * 594)
+#define FLD_PREULTRA_TH_LOW GENMASK(15, 0)
+#define FLD_PREULTRA_TH_HIGH GENMASK(31, 16)
+
+struct mtk_disp_merge {
+ void __iomem *regs;
+ struct clk *clk;
+ struct clk *async_clk;
+ struct cmdq_client_reg cmdq_reg;
+ bool fifo_en;
+};
+
+void mtk_merge_start(struct device *dev)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ writel(MERGE_EN, priv->regs + DISP_REG_MERGE_CTRL);
+}
+
+void mtk_merge_stop(struct device *dev)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ writel(0x0, priv->regs + DISP_REG_MERGE_CTRL);
+}
+
+static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ mtk_ddp_write(cmdq_pkt, ULTRA_EN | PREULTRA_EN,
+ &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_36);
+
+ mtk_ddp_write_mask(cmdq_pkt, BUFFER_MODE,
+ &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_37,
+ FLD_BUFFER_MODE);
+
+ mtk_ddp_write_mask(cmdq_pkt, ULTRA_TH_LOW | ULTRA_TH_HIGH << 16,
+ &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_40,
+ FLD_ULTRA_TH_LOW | FLD_ULTRA_TH_HIGH);
+
+ mtk_ddp_write_mask(cmdq_pkt, PREULTRA_TH_LOW | PREULTRA_TH_HIGH << 16,
+ &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_41,
+ FLD_PREULTRA_TH_LOW | FLD_PREULTRA_TH_HIGH);
+}
+
+void mtk_merge_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+ unsigned int mode = CFG_10_10_1PI_2PO_BUF_MODE;
+
+ if (!h || !w) {
+ dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, w, h);
+ return;
+ }
+
+ if (priv->fifo_en) {
+ mtk_merge_fifo_setting(priv, cmdq_pkt);
+ mode = CFG_10_10_2PI_2PO_BUF_MODE;
+ }
+
+ mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_0);
+ mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_4);
+ mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_24);
+ mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_25);
+ mtk_ddp_write_mask(cmdq_pkt, SWAP_MODE, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_10, FLD_SWAP_MODE);
+ mtk_ddp_write_mask(cmdq_pkt, mode, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_12, FLD_CFG_MERGE_MODE);
+}
+
+int mtk_merge_clk_enable(struct device *dev)
+{
+ int ret = 0;
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ ret = clk_prepare_enable(priv->clk);
+ if (ret) {
+ dev_err(dev, "merge clk prepare enable failed\n");
+ return ret;
+ }
+
+ ret = clk_prepare_enable(priv->async_clk);
+ if (ret) {
+ /* should clean up the state of priv->clk */
+ clk_disable_unprepare(priv->clk);
+
+ dev_err(dev, "async clk prepare enable failed\n");
+ return ret;
+ }
+
+ return ret;
+}
+
+void mtk_merge_clk_disable(struct device *dev)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ clk_disable_unprepare(priv->async_clk);
+ clk_disable_unprepare(priv->clk);
+}
+
+static int mtk_disp_merge_bind(struct device *dev, struct device *master,
+ void *data)
+{
+ return 0;
+}
+
+static void mtk_disp_merge_unbind(struct device *dev, struct device *master,
+ void *data)
+{
+}
+
+static const struct component_ops mtk_disp_merge_component_ops = {
+ .bind = mtk_disp_merge_bind,
+ .unbind = mtk_disp_merge_unbind,
+};
+
+static int mtk_disp_merge_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+ struct mtk_disp_merge *priv;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ priv->regs = devm_ioremap_resource(dev, res);
+ if (IS_ERR(priv->regs)) {
+ dev_err(dev, "failed to ioremap merge\n");
+ return PTR_ERR(priv->regs);
+ }
+
+ priv->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(priv->clk)) {
+ dev_err(dev, "failed to get merge clk\n");
+ return PTR_ERR(priv->clk);
+ }
+
+ priv->async_clk = devm_clk_get_optional(dev, "merge_async");
+ if (IS_ERR(priv->async_clk)) {
+ dev_err(dev, "failed to get merge async clock\n");
+ return PTR_ERR(priv->async_clk);
+ }
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
+ if (ret)
+ dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+
+ priv->fifo_en = of_property_read_bool(dev->of_node,
+ "mediatek,merge-fifo-en");
+
+ platform_set_drvdata(pdev, priv);
+
+ ret = component_add(dev, &mtk_disp_merge_component_ops);
+ if (ret != 0)
+ dev_err(dev, "Failed to add component: %d\n", ret);
+
+ return ret;
+}
+
+static int mtk_disp_merge_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &mtk_disp_merge_component_ops);
+
+ return 0;
+}
+
+static const struct of_device_id mtk_disp_merge_driver_dt_match[] = {
+ { .compatible = "mediatek,mt8195-disp-merge", },
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, mtk_disp_merge_driver_dt_match);
+
+struct platform_driver mtk_disp_merge_driver = {
+ .probe = mtk_disp_merge_probe,
+ .remove = mtk_disp_merge_remove,
+ .driver = {
+ .name = "mediatek-disp-merge",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_disp_merge_driver_dt_match,
+ },
+};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index b3d26a05741f..95722de4986b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -328,6 +328,14 @@ static const struct mtk_ddp_comp_funcs ddp_gamma = {
.stop = mtk_gamma_stop,
};
+static const struct mtk_ddp_comp_funcs ddp_merge = {
+ .clk_enable = mtk_merge_clk_enable,
+ .clk_disable = mtk_merge_clk_disable,
+ .start = mtk_merge_start,
+ .stop = mtk_merge_stop,
+ .config = mtk_merge_config,
+};
+
static const struct mtk_ddp_comp_funcs ddp_od = {
.clk_enable = mtk_ddp_clk_enable,
.clk_disable = mtk_ddp_clk_disable,
@@ -385,6 +393,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_DITHER] = "dither",
[MTK_DISP_DSC] = "dsc",
[MTK_DISP_GAMMA] = "gamma",
+ [MTK_DISP_MERGE] = "merge",
[MTK_DISP_MUTEX] = "mutex",
[MTK_DISP_OD] = "od",
[MTK_DISP_OVL] = "ovl",
@@ -421,6 +430,12 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
[DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi },
[DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
+ [DDP_COMPONENT_MERGE0] = { MTK_DISP_MERGE, 0, &ddp_merge },
+ [DDP_COMPONENT_MERGE1] = { MTK_DISP_MERGE, 1, &ddp_merge },
+ [DDP_COMPONENT_MERGE2] = { MTK_DISP_MERGE, 2, &ddp_merge },
+ [DDP_COMPONENT_MERGE3] = { MTK_DISP_MERGE, 3, &ddp_merge },
+ [DDP_COMPONENT_MERGE4] = { MTK_DISP_MERGE, 4, &ddp_merge },
+ [DDP_COMPONENT_MERGE5] = { MTK_DISP_MERGE, 5, &ddp_merge },
[DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od },
[DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od },
[DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl },
@@ -523,6 +538,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
type == MTK_DISP_CCORR ||
type == MTK_DISP_COLOR ||
type == MTK_DISP_GAMMA ||
+ type == MTK_DISP_MERGE ||
type == MTK_DISP_OVL ||
type == MTK_DISP_OVL_2L ||
type == MTK_DISP_PWM ||
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 763725fe72b3..09ac9496547d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -25,6 +25,7 @@ enum mtk_ddp_comp_type {
MTK_DISP_DITHER,
MTK_DISP_DSC,
MTK_DISP_GAMMA,
+ MTK_DISP_MERGE,
MTK_DISP_MUTEX,
MTK_DISP_OD,
MTK_DISP_OVL,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 6a0a167320f0..230b8aee12b2 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -597,7 +597,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
private->comp_node[comp_id] = of_node_get(node);
/*
- * Currently only the AAL, CCORR, COLOR, GAMMA, OVL, RDMA, DSI, and DPI
+ * Currently only the AAL, CCORR, COLOR, GAMMA, MERGE, OVL, RDMA, DSI, and DPI
* blocks have separate component platform drivers and initialize their own
* DDP component structure. The others are initialized here.
*/
@@ -605,6 +605,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
comp_type == MTK_DISP_CCORR ||
comp_type == MTK_DISP_COLOR ||
comp_type == MTK_DISP_GAMMA ||
+ comp_type == MTK_DISP_MERGE ||
comp_type == MTK_DISP_OVL ||
comp_type == MTK_DISP_OVL_2L ||
comp_type == MTK_DISP_RDMA ||
@@ -703,6 +704,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
&mtk_disp_ccorr_driver,
&mtk_disp_color_driver,
&mtk_disp_gamma_driver,
+ &mtk_disp_merge_driver,
&mtk_disp_ovl_driver,
&mtk_disp_rdma_driver,
&mtk_dpi_driver,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 3e7d1e6fbe01..a58cebd01d35 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -50,6 +50,7 @@ extern struct platform_driver mtk_disp_aal_driver;
extern struct platform_driver mtk_disp_ccorr_driver;
extern struct platform_driver mtk_disp_color_driver;
extern struct platform_driver mtk_disp_gamma_driver;
+extern struct platform_driver mtk_disp_merge_driver;
extern struct platform_driver mtk_disp_ovl_driver;
extern struct platform_driver mtk_disp_rdma_driver;
extern struct platform_driver mtk_dpi_driver;
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [RESEND v17 6/7] drm/mediatek: add MERGE support for mediatek-drm
@ 2022-04-07 3:04 ` jason-jh.lin
0 siblings, 0 replies; 49+ messages in thread
From: jason-jh.lin @ 2022-04-07 3:04 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: Philipp Zabel, Maxime Coquelin, David Airlie, Daniel Vetter,
Alexandre Torgue, John 'Warthog9' Hawley, postmaster,
jason-jh . lin, hsinyi, fshao, moudy.ho, roy-cw.yeh, CK Hu,
Fabien Parent, nancy.lin, singo.chang, devicetree, linux-stm32,
linux-arm-kernel, linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group
Add MERGE engine file:
MERGE module is used to merge two slice-per-line inputs
into one side-by-side output.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
drivers/gpu/drm/mediatek/Makefile | 1 +
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 246 ++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 16 ++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +-
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
7 files changed, 276 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 29098d7c8307..a38e88e82d12 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -4,6 +4,7 @@ mediatek-drm-y := mtk_disp_aal.o \
mtk_disp_ccorr.o \
mtk_disp_color.o \
mtk_disp_gamma.o \
+ mtk_disp_merge.o \
mtk_disp_ovl.o \
mtk_disp_rdma.o \
mtk_drm_crtc.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 86c3068894b1..a33b13fe2b6e 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -55,6 +55,14 @@ void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state);
void mtk_gamma_start(struct device *dev);
void mtk_gamma_stop(struct device *dev);
+int mtk_merge_clk_enable(struct device *dev);
+void mtk_merge_clk_disable(struct device *dev);
+void mtk_merge_config(struct device *dev, unsigned int width,
+ unsigned int height, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_merge_start(struct device *dev);
+void mtk_merge_stop(struct device *dev);
+
void mtk_ovl_bgclr_in_on(struct device *dev);
void mtk_ovl_bgclr_in_off(struct device *dev);
void mtk_ovl_bypass_shadow(struct device *dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
new file mode 100644
index 000000000000..45face638153
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
@@ -0,0 +1,246 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_drm_drv.h"
+#include "mtk_disp_drv.h"
+
+#define DISP_REG_MERGE_CTRL 0x000
+#define MERGE_EN 1
+#define DISP_REG_MERGE_CFG_0 0x010
+#define DISP_REG_MERGE_CFG_4 0x020
+#define DISP_REG_MERGE_CFG_10 0x038
+/* no swap */
+#define SWAP_MODE 0
+#define FLD_SWAP_MODE GENMASK(4, 0)
+#define DISP_REG_MERGE_CFG_12 0x040
+#define CFG_10_10_1PI_2PO_BUF_MODE 6
+#define CFG_10_10_2PI_2PO_BUF_MODE 8
+#define FLD_CFG_MERGE_MODE GENMASK(4, 0)
+#define DISP_REG_MERGE_CFG_24 0x070
+#define DISP_REG_MERGE_CFG_25 0x074
+#define DISP_REG_MERGE_CFG_36 0x0a0
+#define ULTRA_EN BIT(0)
+#define PREULTRA_EN BIT(4)
+#define DISP_REG_MERGE_CFG_37 0x0a4
+/* 0: Off, 1: SRAM0, 2: SRAM1, 3: SRAM0 + SRAM1 */
+#define BUFFER_MODE 3
+#define FLD_BUFFER_MODE GENMASK(1, 0)
+/*
+ * For the ultra and preultra settings, 6us ~ 9us is experience value
+ * and the maximum frequency of mmsys clock is 594MHz.
+ */
+#define DISP_REG_MERGE_CFG_40 0x0b0
+/* 6 us, 594M pixel/sec */
+#define ULTRA_TH_LOW (6 * 594)
+/* 8 us, 594M pixel/sec */
+#define ULTRA_TH_HIGH (8 * 594)
+#define FLD_ULTRA_TH_LOW GENMASK(15, 0)
+#define FLD_ULTRA_TH_HIGH GENMASK(31, 16)
+#define DISP_REG_MERGE_CFG_41 0x0b4
+/* 8 us, 594M pixel/sec */
+#define PREULTRA_TH_LOW (8 * 594)
+/* 9 us, 594M pixel/sec */
+#define PREULTRA_TH_HIGH (9 * 594)
+#define FLD_PREULTRA_TH_LOW GENMASK(15, 0)
+#define FLD_PREULTRA_TH_HIGH GENMASK(31, 16)
+
+struct mtk_disp_merge {
+ void __iomem *regs;
+ struct clk *clk;
+ struct clk *async_clk;
+ struct cmdq_client_reg cmdq_reg;
+ bool fifo_en;
+};
+
+void mtk_merge_start(struct device *dev)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ writel(MERGE_EN, priv->regs + DISP_REG_MERGE_CTRL);
+}
+
+void mtk_merge_stop(struct device *dev)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ writel(0x0, priv->regs + DISP_REG_MERGE_CTRL);
+}
+
+static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ mtk_ddp_write(cmdq_pkt, ULTRA_EN | PREULTRA_EN,
+ &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_36);
+
+ mtk_ddp_write_mask(cmdq_pkt, BUFFER_MODE,
+ &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_37,
+ FLD_BUFFER_MODE);
+
+ mtk_ddp_write_mask(cmdq_pkt, ULTRA_TH_LOW | ULTRA_TH_HIGH << 16,
+ &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_40,
+ FLD_ULTRA_TH_LOW | FLD_ULTRA_TH_HIGH);
+
+ mtk_ddp_write_mask(cmdq_pkt, PREULTRA_TH_LOW | PREULTRA_TH_HIGH << 16,
+ &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_41,
+ FLD_PREULTRA_TH_LOW | FLD_PREULTRA_TH_HIGH);
+}
+
+void mtk_merge_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+ unsigned int mode = CFG_10_10_1PI_2PO_BUF_MODE;
+
+ if (!h || !w) {
+ dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, w, h);
+ return;
+ }
+
+ if (priv->fifo_en) {
+ mtk_merge_fifo_setting(priv, cmdq_pkt);
+ mode = CFG_10_10_2PI_2PO_BUF_MODE;
+ }
+
+ mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_0);
+ mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_4);
+ mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_24);
+ mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_25);
+ mtk_ddp_write_mask(cmdq_pkt, SWAP_MODE, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_10, FLD_SWAP_MODE);
+ mtk_ddp_write_mask(cmdq_pkt, mode, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_12, FLD_CFG_MERGE_MODE);
+}
+
+int mtk_merge_clk_enable(struct device *dev)
+{
+ int ret = 0;
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ ret = clk_prepare_enable(priv->clk);
+ if (ret) {
+ dev_err(dev, "merge clk prepare enable failed\n");
+ return ret;
+ }
+
+ ret = clk_prepare_enable(priv->async_clk);
+ if (ret) {
+ /* should clean up the state of priv->clk */
+ clk_disable_unprepare(priv->clk);
+
+ dev_err(dev, "async clk prepare enable failed\n");
+ return ret;
+ }
+
+ return ret;
+}
+
+void mtk_merge_clk_disable(struct device *dev)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ clk_disable_unprepare(priv->async_clk);
+ clk_disable_unprepare(priv->clk);
+}
+
+static int mtk_disp_merge_bind(struct device *dev, struct device *master,
+ void *data)
+{
+ return 0;
+}
+
+static void mtk_disp_merge_unbind(struct device *dev, struct device *master,
+ void *data)
+{
+}
+
+static const struct component_ops mtk_disp_merge_component_ops = {
+ .bind = mtk_disp_merge_bind,
+ .unbind = mtk_disp_merge_unbind,
+};
+
+static int mtk_disp_merge_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+ struct mtk_disp_merge *priv;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ priv->regs = devm_ioremap_resource(dev, res);
+ if (IS_ERR(priv->regs)) {
+ dev_err(dev, "failed to ioremap merge\n");
+ return PTR_ERR(priv->regs);
+ }
+
+ priv->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(priv->clk)) {
+ dev_err(dev, "failed to get merge clk\n");
+ return PTR_ERR(priv->clk);
+ }
+
+ priv->async_clk = devm_clk_get_optional(dev, "merge_async");
+ if (IS_ERR(priv->async_clk)) {
+ dev_err(dev, "failed to get merge async clock\n");
+ return PTR_ERR(priv->async_clk);
+ }
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
+ if (ret)
+ dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+
+ priv->fifo_en = of_property_read_bool(dev->of_node,
+ "mediatek,merge-fifo-en");
+
+ platform_set_drvdata(pdev, priv);
+
+ ret = component_add(dev, &mtk_disp_merge_component_ops);
+ if (ret != 0)
+ dev_err(dev, "Failed to add component: %d\n", ret);
+
+ return ret;
+}
+
+static int mtk_disp_merge_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &mtk_disp_merge_component_ops);
+
+ return 0;
+}
+
+static const struct of_device_id mtk_disp_merge_driver_dt_match[] = {
+ { .compatible = "mediatek,mt8195-disp-merge", },
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, mtk_disp_merge_driver_dt_match);
+
+struct platform_driver mtk_disp_merge_driver = {
+ .probe = mtk_disp_merge_probe,
+ .remove = mtk_disp_merge_remove,
+ .driver = {
+ .name = "mediatek-disp-merge",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_disp_merge_driver_dt_match,
+ },
+};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index b3d26a05741f..95722de4986b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -328,6 +328,14 @@ static const struct mtk_ddp_comp_funcs ddp_gamma = {
.stop = mtk_gamma_stop,
};
+static const struct mtk_ddp_comp_funcs ddp_merge = {
+ .clk_enable = mtk_merge_clk_enable,
+ .clk_disable = mtk_merge_clk_disable,
+ .start = mtk_merge_start,
+ .stop = mtk_merge_stop,
+ .config = mtk_merge_config,
+};
+
static const struct mtk_ddp_comp_funcs ddp_od = {
.clk_enable = mtk_ddp_clk_enable,
.clk_disable = mtk_ddp_clk_disable,
@@ -385,6 +393,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_DITHER] = "dither",
[MTK_DISP_DSC] = "dsc",
[MTK_DISP_GAMMA] = "gamma",
+ [MTK_DISP_MERGE] = "merge",
[MTK_DISP_MUTEX] = "mutex",
[MTK_DISP_OD] = "od",
[MTK_DISP_OVL] = "ovl",
@@ -421,6 +430,12 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
[DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi },
[DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
+ [DDP_COMPONENT_MERGE0] = { MTK_DISP_MERGE, 0, &ddp_merge },
+ [DDP_COMPONENT_MERGE1] = { MTK_DISP_MERGE, 1, &ddp_merge },
+ [DDP_COMPONENT_MERGE2] = { MTK_DISP_MERGE, 2, &ddp_merge },
+ [DDP_COMPONENT_MERGE3] = { MTK_DISP_MERGE, 3, &ddp_merge },
+ [DDP_COMPONENT_MERGE4] = { MTK_DISP_MERGE, 4, &ddp_merge },
+ [DDP_COMPONENT_MERGE5] = { MTK_DISP_MERGE, 5, &ddp_merge },
[DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od },
[DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od },
[DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl },
@@ -523,6 +538,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
type == MTK_DISP_CCORR ||
type == MTK_DISP_COLOR ||
type == MTK_DISP_GAMMA ||
+ type == MTK_DISP_MERGE ||
type == MTK_DISP_OVL ||
type == MTK_DISP_OVL_2L ||
type == MTK_DISP_PWM ||
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 763725fe72b3..09ac9496547d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -25,6 +25,7 @@ enum mtk_ddp_comp_type {
MTK_DISP_DITHER,
MTK_DISP_DSC,
MTK_DISP_GAMMA,
+ MTK_DISP_MERGE,
MTK_DISP_MUTEX,
MTK_DISP_OD,
MTK_DISP_OVL,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 6a0a167320f0..230b8aee12b2 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -597,7 +597,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
private->comp_node[comp_id] = of_node_get(node);
/*
- * Currently only the AAL, CCORR, COLOR, GAMMA, OVL, RDMA, DSI, and DPI
+ * Currently only the AAL, CCORR, COLOR, GAMMA, MERGE, OVL, RDMA, DSI, and DPI
* blocks have separate component platform drivers and initialize their own
* DDP component structure. The others are initialized here.
*/
@@ -605,6 +605,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
comp_type == MTK_DISP_CCORR ||
comp_type == MTK_DISP_COLOR ||
comp_type == MTK_DISP_GAMMA ||
+ comp_type == MTK_DISP_MERGE ||
comp_type == MTK_DISP_OVL ||
comp_type == MTK_DISP_OVL_2L ||
comp_type == MTK_DISP_RDMA ||
@@ -703,6 +704,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
&mtk_disp_ccorr_driver,
&mtk_disp_color_driver,
&mtk_disp_gamma_driver,
+ &mtk_disp_merge_driver,
&mtk_disp_ovl_driver,
&mtk_disp_rdma_driver,
&mtk_dpi_driver,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 3e7d1e6fbe01..a58cebd01d35 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -50,6 +50,7 @@ extern struct platform_driver mtk_disp_aal_driver;
extern struct platform_driver mtk_disp_ccorr_driver;
extern struct platform_driver mtk_disp_color_driver;
extern struct platform_driver mtk_disp_gamma_driver;
+extern struct platform_driver mtk_disp_merge_driver;
extern struct platform_driver mtk_disp_ovl_driver;
extern struct platform_driver mtk_disp_rdma_driver;
extern struct platform_driver mtk_dpi_driver;
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [RESEND v17 7/7] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
2022-04-07 3:04 ` jason-jh.lin
@ 2022-04-07 3:04 ` jason-jh.lin
-1 siblings, 0 replies; 49+ messages in thread
From: jason-jh.lin @ 2022-04-07 3:04 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: David Airlie, singo.chang, Alexandre Torgue, postmaster,
Fabien Parent, John 'Warthog9' Hawley, linux-stm32,
roy-cw.yeh, Project_Global_Chrome_Upstream_Group, CK Hu,
Philipp Zabel, devicetree, Daniel Vetter, nancy.lin,
linux-mediatek, hsinyi, linux-arm-kernel, jason-jh . lin,
linux-kernel, moudy.ho, Maxime Coquelin
1. Add driver data of mt8195 vdosys0 to mediatek-drm and the sub driver.
2. Add get driver data by clock name function to get the corresponding
driver data for mt8195 vdosys0.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 80 ++++++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 2 +
3 files changed, 88 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 662e91d9d45f..8ce60371536e 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -364,6 +364,10 @@ static const struct mtk_disp_rdma_data mt8192_rdma_driver_data = {
.fifo_size = 5 * SZ_1K,
};
+static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = {
+ .fifo_size = 1920,
+};
+
static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
{ .compatible = "mediatek,mt2701-disp-rdma",
.data = &mt2701_rdma_driver_data},
@@ -373,6 +377,8 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
.data = &mt8183_rdma_driver_data},
{ .compatible = "mediatek,mt8192-disp-rdma",
.data = &mt8192_rdma_driver_data},
+ { .compatible = "mediatek,mt8195-disp-rdma",
+ .data = &mt8195_rdma_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 230b8aee12b2..cd3a5b215087 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -4,6 +4,8 @@
* Author: YT SHEN <yt.shen@mediatek.com>
*/
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
#include <linux/component.h>
#include <linux/iommu.h>
#include <linux/module.h>
@@ -177,6 +179,19 @@ static const enum mtk_ddp_comp_id mt8192_mtk_ddp_ext[] = {
DDP_COMPONENT_DPI0,
};
+static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
+ DDP_COMPONENT_OVL0,
+ DDP_COMPONENT_RDMA0,
+ DDP_COMPONENT_COLOR0,
+ DDP_COMPONENT_CCORR,
+ DDP_COMPONENT_AAL0,
+ DDP_COMPONENT_GAMMA,
+ DDP_COMPONENT_DITHER0,
+ DDP_COMPONENT_DSC0,
+ DDP_COMPONENT_MERGE0,
+ DDP_COMPONENT_DP_INTF0,
+};
+
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.main_path = mt2701_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
@@ -228,6 +243,13 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
.ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext),
};
+static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
+ .clk_name = "cfg_vdo0",
+ .clk_platform = "clk-mt8195",
+ .main_path = mt8195_mtk_ddp_main,
+ .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
+};
+
static int mtk_drm_kms_init(struct drm_device *drm)
{
struct mtk_drm_private *private = drm->dev_private;
@@ -445,12 +467,16 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_DITHER },
{ .compatible = "mediatek,mt8183-disp-dither",
.data = (void *)MTK_DISP_DITHER },
+ { .compatible = "mediatek,mt8195-disp-dsc",
+ .data = (void *)MTK_DISP_DSC },
{ .compatible = "mediatek,mt8167-disp-gamma",
.data = (void *)MTK_DISP_GAMMA, },
{ .compatible = "mediatek,mt8173-disp-gamma",
.data = (void *)MTK_DISP_GAMMA, },
{ .compatible = "mediatek,mt8183-disp-gamma",
.data = (void *)MTK_DISP_GAMMA, },
+ { .compatible = "mediatek,mt8195-disp-merge",
+ .data = (void *)MTK_DISP_MERGE },
{ .compatible = "mediatek,mt2701-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt2712-disp-mutex",
@@ -463,6 +489,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt8192-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
+ { .compatible = "mediatek,mt8195-disp-mutex",
+ .data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt8173-disp-od",
.data = (void *)MTK_DISP_OD },
{ .compatible = "mediatek,mt2701-disp-ovl",
@@ -497,6 +525,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_RDMA },
{ .compatible = "mediatek,mt8192-disp-rdma",
.data = (void *)MTK_DISP_RDMA },
+ { .compatible = "mediatek,mt8195-disp-rdma",
+ .data = (void *)MTK_DISP_RDMA },
{ .compatible = "mediatek,mt8173-disp-ufoe",
.data = (void *)MTK_DISP_UFOE },
{ .compatible = "mediatek,mt8173-disp-wdma",
@@ -533,10 +563,56 @@ static const struct of_device_id mtk_drm_of_ids[] = {
.data = &mt8183_mmsys_driver_data},
{ .compatible = "mediatek,mt8192-mmsys",
.data = &mt8192_mmsys_driver_data},
+ { .compatible = "mediatek,mt8195-mmsys"},
{ }
};
MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
+static const struct of_device_id mtk_clk_platform_labels[] = {
+ { .compatible = "mediatek,mt8195-mmsys",
+ .data = (void *)"clk-mt8195"},
+};
+
+static int mtk_drm_get_match_data_by_clk_name(const struct mtk_mmsys_driver_data **data,
+ struct device *dev)
+{
+ int i;
+ struct platform_device *pdev = of_find_device_by_node(dev->parent->of_node);
+ struct clk *clk;
+ const char *clk_name;
+ const struct of_device_id *of_id = of_match_node(mtk_clk_platform_labels,
+ dev->parent->of_node);
+ const struct mtk_mmsys_driver_data *drvdata[] = {
+ &mt8195_vdosys0_driver_data,
+ };
+
+ if (!of_id || !of_id->data) {
+ dev_err(dev, "Can't find match clk platform labels\n");
+ return -EINVAL;
+ }
+
+ clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(clk)) {
+ dev_err(&pdev->dev, "failed to get parent clk\n");
+ return PTR_ERR(clk);
+ }
+
+ clk_name = __clk_get_name(clk);
+ if (!clk_name) {
+ dev_err(dev, "invalid mmsys clk name\n");
+ return -EINVAL;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(drvdata); i++)
+ if (strncmp(drvdata[i]->clk_name, clk_name, strlen(clk_name)) == 0 &&
+ strncmp(drvdata[i]->clk_platform, of_id->data, strlen(of_id->data)) == 0) {
+ *data = drvdata[i];
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
static int mtk_drm_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -563,6 +639,10 @@ static int mtk_drm_probe(struct platform_device *pdev)
return -ENODEV;
private->data = of_id->data;
+ if (!private->data && mtk_drm_get_match_data_by_clk_name(&private->data, dev) < 0) {
+ dev_err(dev, "Couldn't get match driver data\n");
+ return -EINVAL;
+ }
/* Iterate over sibling DISP function blocks */
for_each_child_of_node(phandle->parent, node) {
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index a58cebd01d35..78cbf1ae3bd5 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -21,6 +21,8 @@ struct drm_property;
struct regmap;
struct mtk_mmsys_driver_data {
+ const char *clk_name;
+ const char *clk_platform;
const enum mtk_ddp_comp_id *main_path;
unsigned int main_len;
const enum mtk_ddp_comp_id *ext_path;
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [RESEND v17 7/7] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
@ 2022-04-07 3:04 ` jason-jh.lin
0 siblings, 0 replies; 49+ messages in thread
From: jason-jh.lin @ 2022-04-07 3:04 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: Philipp Zabel, Maxime Coquelin, David Airlie, Daniel Vetter,
Alexandre Torgue, John 'Warthog9' Hawley, postmaster,
jason-jh . lin, hsinyi, fshao, moudy.ho, roy-cw.yeh, CK Hu,
Fabien Parent, nancy.lin, singo.chang, devicetree, linux-stm32,
linux-arm-kernel, linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group
1. Add driver data of mt8195 vdosys0 to mediatek-drm and the sub driver.
2. Add get driver data by clock name function to get the corresponding
driver data for mt8195 vdosys0.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 80 ++++++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 2 +
3 files changed, 88 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 662e91d9d45f..8ce60371536e 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -364,6 +364,10 @@ static const struct mtk_disp_rdma_data mt8192_rdma_driver_data = {
.fifo_size = 5 * SZ_1K,
};
+static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = {
+ .fifo_size = 1920,
+};
+
static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
{ .compatible = "mediatek,mt2701-disp-rdma",
.data = &mt2701_rdma_driver_data},
@@ -373,6 +377,8 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
.data = &mt8183_rdma_driver_data},
{ .compatible = "mediatek,mt8192-disp-rdma",
.data = &mt8192_rdma_driver_data},
+ { .compatible = "mediatek,mt8195-disp-rdma",
+ .data = &mt8195_rdma_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 230b8aee12b2..cd3a5b215087 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -4,6 +4,8 @@
* Author: YT SHEN <yt.shen@mediatek.com>
*/
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
#include <linux/component.h>
#include <linux/iommu.h>
#include <linux/module.h>
@@ -177,6 +179,19 @@ static const enum mtk_ddp_comp_id mt8192_mtk_ddp_ext[] = {
DDP_COMPONENT_DPI0,
};
+static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
+ DDP_COMPONENT_OVL0,
+ DDP_COMPONENT_RDMA0,
+ DDP_COMPONENT_COLOR0,
+ DDP_COMPONENT_CCORR,
+ DDP_COMPONENT_AAL0,
+ DDP_COMPONENT_GAMMA,
+ DDP_COMPONENT_DITHER0,
+ DDP_COMPONENT_DSC0,
+ DDP_COMPONENT_MERGE0,
+ DDP_COMPONENT_DP_INTF0,
+};
+
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.main_path = mt2701_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
@@ -228,6 +243,13 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
.ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext),
};
+static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
+ .clk_name = "cfg_vdo0",
+ .clk_platform = "clk-mt8195",
+ .main_path = mt8195_mtk_ddp_main,
+ .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
+};
+
static int mtk_drm_kms_init(struct drm_device *drm)
{
struct mtk_drm_private *private = drm->dev_private;
@@ -445,12 +467,16 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_DITHER },
{ .compatible = "mediatek,mt8183-disp-dither",
.data = (void *)MTK_DISP_DITHER },
+ { .compatible = "mediatek,mt8195-disp-dsc",
+ .data = (void *)MTK_DISP_DSC },
{ .compatible = "mediatek,mt8167-disp-gamma",
.data = (void *)MTK_DISP_GAMMA, },
{ .compatible = "mediatek,mt8173-disp-gamma",
.data = (void *)MTK_DISP_GAMMA, },
{ .compatible = "mediatek,mt8183-disp-gamma",
.data = (void *)MTK_DISP_GAMMA, },
+ { .compatible = "mediatek,mt8195-disp-merge",
+ .data = (void *)MTK_DISP_MERGE },
{ .compatible = "mediatek,mt2701-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt2712-disp-mutex",
@@ -463,6 +489,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt8192-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
+ { .compatible = "mediatek,mt8195-disp-mutex",
+ .data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt8173-disp-od",
.data = (void *)MTK_DISP_OD },
{ .compatible = "mediatek,mt2701-disp-ovl",
@@ -497,6 +525,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_RDMA },
{ .compatible = "mediatek,mt8192-disp-rdma",
.data = (void *)MTK_DISP_RDMA },
+ { .compatible = "mediatek,mt8195-disp-rdma",
+ .data = (void *)MTK_DISP_RDMA },
{ .compatible = "mediatek,mt8173-disp-ufoe",
.data = (void *)MTK_DISP_UFOE },
{ .compatible = "mediatek,mt8173-disp-wdma",
@@ -533,10 +563,56 @@ static const struct of_device_id mtk_drm_of_ids[] = {
.data = &mt8183_mmsys_driver_data},
{ .compatible = "mediatek,mt8192-mmsys",
.data = &mt8192_mmsys_driver_data},
+ { .compatible = "mediatek,mt8195-mmsys"},
{ }
};
MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
+static const struct of_device_id mtk_clk_platform_labels[] = {
+ { .compatible = "mediatek,mt8195-mmsys",
+ .data = (void *)"clk-mt8195"},
+};
+
+static int mtk_drm_get_match_data_by_clk_name(const struct mtk_mmsys_driver_data **data,
+ struct device *dev)
+{
+ int i;
+ struct platform_device *pdev = of_find_device_by_node(dev->parent->of_node);
+ struct clk *clk;
+ const char *clk_name;
+ const struct of_device_id *of_id = of_match_node(mtk_clk_platform_labels,
+ dev->parent->of_node);
+ const struct mtk_mmsys_driver_data *drvdata[] = {
+ &mt8195_vdosys0_driver_data,
+ };
+
+ if (!of_id || !of_id->data) {
+ dev_err(dev, "Can't find match clk platform labels\n");
+ return -EINVAL;
+ }
+
+ clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(clk)) {
+ dev_err(&pdev->dev, "failed to get parent clk\n");
+ return PTR_ERR(clk);
+ }
+
+ clk_name = __clk_get_name(clk);
+ if (!clk_name) {
+ dev_err(dev, "invalid mmsys clk name\n");
+ return -EINVAL;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(drvdata); i++)
+ if (strncmp(drvdata[i]->clk_name, clk_name, strlen(clk_name)) == 0 &&
+ strncmp(drvdata[i]->clk_platform, of_id->data, strlen(of_id->data)) == 0) {
+ *data = drvdata[i];
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
static int mtk_drm_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -563,6 +639,10 @@ static int mtk_drm_probe(struct platform_device *pdev)
return -ENODEV;
private->data = of_id->data;
+ if (!private->data && mtk_drm_get_match_data_by_clk_name(&private->data, dev) < 0) {
+ dev_err(dev, "Couldn't get match driver data\n");
+ return -EINVAL;
+ }
/* Iterate over sibling DISP function blocks */
for_each_child_of_node(phandle->parent, node) {
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index a58cebd01d35..78cbf1ae3bd5 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -21,6 +21,8 @@ struct drm_property;
struct regmap;
struct mtk_mmsys_driver_data {
+ const char *clk_name;
+ const char *clk_platform;
const enum mtk_ddp_comp_id *main_path;
unsigned int main_len;
const enum mtk_ddp_comp_id *ext_path;
--
2.18.0
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 49+ messages in thread
* Re: [RESEND v17 2/7] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
2022-04-07 3:04 ` jason-jh.lin
@ 2022-04-07 5:12 ` CK Hu
-1 siblings, 0 replies; 49+ messages in thread
From: CK Hu @ 2022-04-07 5:12 UTC (permalink / raw)
To: jason-jh.lin, Rob Herring, Matthias Brugger, Chun-Kuang Hu,
AngeloGioacchino Del Regno
Cc: devicetree, Maxime Coquelin, David Airlie, linux-kernel,
singo.chang, hsinyi, Alexandre Torgue, postmaster,
Project_Global_Chrome_Upstream_Group, Fabien Parent, moudy.ho,
linux-mediatek, roy-cw.yeh, Daniel Vetter,
John 'Warthog9' Hawley, Philipp Zabel, nancy.lin,
linux-stm32, linux-arm-kernel
Hi, Jason:
On Thu, 2022-04-07 at 11:04 +0800, jason-jh.lin wrote:
> In the SoC before, such as mt8173, it has 2 pipelines binding to one
> mmsys with the same clock driver and the same power domain.
>
> In mt8195, there are 4 pipelines binding to 4 different mmsys, such
> as
> vdosys0, vdosys1, vppsys0 and vppsys1.
> Each mmsys uses different clock drivers and different power domain.
>
> Since each mmsys has its own clock, they could be identified
> by the different name of their clock.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 4
> ++++
> 1 file changed, 4 insertions(+)
>
> diff --git
> a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> index 6c2c3edcd443..f71c8dd07bf9 100644
> ---
> a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +++
> b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> @@ -31,6 +31,7 @@ properties:
> - mediatek,mt8183-mmsys
> - mediatek,mt8186-mmsys
> - mediatek,mt8192-mmsys
> + - mediatek,mt8195-mmsys
> - mediatek,mt8365-mmsys
> - const: syscon
> - items:
> @@ -65,6 +66,9 @@ properties:
> $ref: /schemas/types.yaml#/definitions/phandle-array
> maxItems: 1
>
> + clocks:
> + maxItems: 1
> +
> "#clock-cells":
> const: 1
>
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^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [RESEND v17 2/7] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
@ 2022-04-07 5:12 ` CK Hu
0 siblings, 0 replies; 49+ messages in thread
From: CK Hu @ 2022-04-07 5:12 UTC (permalink / raw)
To: jason-jh.lin, Rob Herring, Matthias Brugger, Chun-Kuang Hu,
AngeloGioacchino Del Regno
Cc: Philipp Zabel, Maxime Coquelin, David Airlie, Daniel Vetter,
Alexandre Torgue, John 'Warthog9' Hawley, postmaster,
hsinyi, fshao, moudy.ho, roy-cw.yeh, Fabien Parent, nancy.lin,
singo.chang, devicetree, linux-stm32, linux-arm-kernel,
linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group
Hi, Jason:
On Thu, 2022-04-07 at 11:04 +0800, jason-jh.lin wrote:
> In the SoC before, such as mt8173, it has 2 pipelines binding to one
> mmsys with the same clock driver and the same power domain.
>
> In mt8195, there are 4 pipelines binding to 4 different mmsys, such
> as
> vdosys0, vdosys1, vppsys0 and vppsys1.
> Each mmsys uses different clock drivers and different power domain.
>
> Since each mmsys has its own clock, they could be identified
> by the different name of their clock.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 4
> ++++
> 1 file changed, 4 insertions(+)
>
> diff --git
> a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> index 6c2c3edcd443..f71c8dd07bf9 100644
> ---
> a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +++
> b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> @@ -31,6 +31,7 @@ properties:
> - mediatek,mt8183-mmsys
> - mediatek,mt8186-mmsys
> - mediatek,mt8192-mmsys
> + - mediatek,mt8195-mmsys
> - mediatek,mt8365-mmsys
> - const: syscon
> - items:
> @@ -65,6 +66,9 @@ properties:
> $ref: /schemas/types.yaml#/definitions/phandle-array
> maxItems: 1
>
> + clocks:
> + maxItems: 1
> +
> "#clock-cells":
> const: 1
>
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [RESEND v17 3/7] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
2022-04-07 3:04 ` jason-jh.lin
@ 2022-04-07 5:45 ` CK Hu
-1 siblings, 0 replies; 49+ messages in thread
From: CK Hu @ 2022-04-07 5:45 UTC (permalink / raw)
To: jason-jh.lin, Rob Herring, Matthias Brugger, Chun-Kuang Hu,
AngeloGioacchino Del Regno
Cc: David Airlie, singo.chang, Alexandre Torgue, postmaster,
Fabien Parent, John 'Warthog9' Hawley, linux-stm32,
roy-cw.yeh, Project_Global_Chrome_Upstream_Group, Philipp Zabel,
devicetree, Daniel Vetter, nancy.lin, linux-mediatek, hsinyi,
linux-arm-kernel, linux-kernel, moudy.ho, Maxime Coquelin
Hi, Jason:
On Thu, 2022-04-07 at 11:04 +0800, jason-jh.lin wrote:
> 1. Add mt8195 mmsys compatible for vdosys0.
> 2. Add mt8195 routing table settings and fix build fail.
> 3. Add clock name, clock driver name and routing table into the
> driver data
> of mt8195 vdosys0.
> 4. Add get match data by clock name function and clock platform
> labels
> to identify which mmsys node is corresponding to vdosys0.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 6 +-
> drivers/soc/mediatek/mt8167-mmsys.h | 2 +-
> drivers/soc/mediatek/mt8183-mmsys.h | 2 +-
> drivers/soc/mediatek/mt8186-mmsys.h | 4 +-
> drivers/soc/mediatek/mt8192-mmsys.h | 4 +-
> drivers/soc/mediatek/mt8195-mmsys.h | 370
> ++++++++++++++++++++
> drivers/soc/mediatek/mt8365-mmsys.h | 4 +-
> drivers/soc/mediatek/mtk-mmsys.c | 62 ++++
> drivers/soc/mediatek/mtk-mmsys.h | 1 +
> drivers/soc/mediatek/mtk-mutex.c | 8 +-
> include/linux/soc/mediatek/mtk-mmsys.h | 13 +-
> 12 files changed, 461 insertions(+), 17 deletions(-)
> create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
>
[snip]
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> b/drivers/soc/mediatek/mtk-mmsys.c
> index 4fc4c2c9ea20..b2fa239c5f5f 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -4,6 +4,8 @@
> * Author: James Liao <jamesjj.liao@mediatek.com>
> */
>
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> #include <linux/delay.h>
> #include <linux/device.h>
> #include <linux/io.h>
> @@ -17,6 +19,7 @@
> #include "mt8183-mmsys.h"
> #include "mt8186-mmsys.h"
> #include "mt8192-mmsys.h"
> +#include "mt8195-mmsys.h"
> #include "mt8365-mmsys.h"
>
> static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data =
> {
> @@ -72,12 +75,24 @@ static const struct mtk_mmsys_driver_data
> mt8192_mmsys_driver_data = {
> .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
> };
>
> +static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data
> = {
> + .clk_name = "cfg_vdo0",
> + .clk_driver = "clk-mt8195-vdo0",
> + .routes = mmsys_mt8195_routing_table,
> + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> +};
> +
> static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data =
> {
> .clk_driver = "clk-mt8365-mm",
> .routes = mt8365_mmsys_routing_table,
> .num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
> };
>
> +static const struct of_device_id mtk_clk_platform_labels[] = {
> + { .compatible = "mediatek,mt8195-mmsys",
> + .data = (void *)"clk-mt8195"},
> +};
> +
> struct mtk_mmsys {
> void __iomem *regs;
> const struct mtk_mmsys_driver_data *data;
> @@ -85,6 +100,45 @@ struct mtk_mmsys {
> struct reset_controller_dev rcdev;
> };
>
> +static int mtk_mmsys_get_match_data_by_clk_name(const struct
> mtk_mmsys_driver_data **data,
> + struct device *dev)
> +{
> + int i;
> + struct clk *clk;
> + const char *clk_name;
> + const struct of_device_id *of_id =
> of_match_node(mtk_clk_platform_labels,
> + dev->of_node);
> + const struct mtk_mmsys_driver_data *drvdata[] = {
> + &mt8195_vdosys0_driver_data,
> + };
> +
> + if (!of_id || !of_id->data) {
> + dev_err(dev, "Can't find match clk platform labels\n");
> + return -EINVAL;
> + }
> +
> + clk = devm_clk_get(dev, NULL);
> + if (IS_ERR(clk)) {
> + dev_err(dev, "failed to get mmsys clk\n");
> + return PTR_ERR(clk);
> + }
> +
> + clk_name = __clk_get_name(clk);
> + if (!clk_name) {
> + dev_err(dev, "invalid mmsys clk name\n");
> + return -EINVAL;
> + }
> +
> + for (i = 0; i < ARRAY_SIZE(drvdata); i++)
> + if (strncmp(drvdata[i]->clk_name, clk_name,
> strlen(clk_name)) == 0 &&
> + strncmp(drvdata[i]->clk_driver, of_id->data,
> strlen(of_id->data)) == 0) {
I think clk_name is enough to identify the mmsys, why do you need
clk_driver?
> + *data = drvdata[i];
> + return 0;
> + }
> +
> + return -EINVAL;
> +}
> +
> void mtk_mmsys_ddp_connect(struct device *dev,
> enum mtk_ddp_comp_id cur,
> enum mtk_ddp_comp_id next)
> @@ -206,6 +260,11 @@ static int mtk_mmsys_probe(struct
> platform_device *pdev)
> }
>
> mmsys->data = of_device_get_match_data(&pdev->dev);
> + if (!mmsys->data &&
> mtk_mmsys_get_match_data_by_clk_name(&mmsys->data, dev) < 0) {
> + dev_err(dev, "Couldn't get match driver data\n");
> + return -EINVAL;
> + }
> +
> platform_set_drvdata(pdev, mmsys);
>
> clks = platform_device_register_data(&pdev->dev, mmsys->data-
> >clk_driver,
> @@ -260,6 +319,9 @@ static const struct of_device_id
> of_match_mtk_mmsys[] = {
> .compatible = "mediatek,mt8192-mmsys",
> .data = &mt8192_mmsys_driver_data,
> },
> + {
> + .compatible = "mediatek,mt8195-mmsys",
> + },
> {
> .compatible = "mediatek,mt8365-mmsys",
> .data = &mt8365_mmsys_driver_data,
>
[snip]
> b/include/linux/soc/mediatek/mtk-mmsys.h
> index 4bba275e235a..fb719fd1281c 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -16,14 +16,25 @@ enum mtk_ddp_comp_id {
> DDP_COMPONENT_CCORR,
> DDP_COMPONENT_COLOR0,
> DDP_COMPONENT_COLOR1,
> - DDP_COMPONENT_DITHER,
> + DDP_COMPONENT_DITHER0,
I would like soc and drm modification to go through different tree, so
this setting would not modify drm driver in this patch.
DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
Then modify drm driver after this patch.
Regards,
CK
> + DDP_COMPONENT_DITHER1,
> + DDP_COMPONENT_DP_INTF0,
> + DDP_COMPONENT_DP_INTF1,
> DDP_COMPONENT_DPI0,
> DDP_COMPONENT_DPI1,
> + DDP_COMPONENT_DSC0,
> + DDP_COMPONENT_DSC1,
> DDP_COMPONENT_DSI0,
> DDP_COMPONENT_DSI1,
> DDP_COMPONENT_DSI2,
> DDP_COMPONENT_DSI3,
> DDP_COMPONENT_GAMMA,
> + DDP_COMPONENT_MERGE0,
> + DDP_COMPONENT_MERGE1,
> + DDP_COMPONENT_MERGE2,
> + DDP_COMPONENT_MERGE3,
> + DDP_COMPONENT_MERGE4,
> + DDP_COMPONENT_MERGE5,
> DDP_COMPONENT_OD0,
> DDP_COMPONENT_OD1,
> DDP_COMPONENT_OVL0,
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^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [RESEND v17 3/7] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
@ 2022-04-07 5:45 ` CK Hu
0 siblings, 0 replies; 49+ messages in thread
From: CK Hu @ 2022-04-07 5:45 UTC (permalink / raw)
To: jason-jh.lin, Rob Herring, Matthias Brugger, Chun-Kuang Hu,
AngeloGioacchino Del Regno
Cc: David Airlie, singo.chang, Alexandre Torgue, postmaster,
Fabien Parent, John 'Warthog9' Hawley, linux-stm32,
roy-cw.yeh, Project_Global_Chrome_Upstream_Group, Philipp Zabel,
devicetree, Daniel Vetter, nancy.lin, linux-mediatek, hsinyi,
linux-arm-kernel, linux-kernel, moudy.ho, Maxime Coquelin
Hi, Jason:
On Thu, 2022-04-07 at 11:04 +0800, jason-jh.lin wrote:
> 1. Add mt8195 mmsys compatible for vdosys0.
> 2. Add mt8195 routing table settings and fix build fail.
> 3. Add clock name, clock driver name and routing table into the
> driver data
> of mt8195 vdosys0.
> 4. Add get match data by clock name function and clock platform
> labels
> to identify which mmsys node is corresponding to vdosys0.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 6 +-
> drivers/soc/mediatek/mt8167-mmsys.h | 2 +-
> drivers/soc/mediatek/mt8183-mmsys.h | 2 +-
> drivers/soc/mediatek/mt8186-mmsys.h | 4 +-
> drivers/soc/mediatek/mt8192-mmsys.h | 4 +-
> drivers/soc/mediatek/mt8195-mmsys.h | 370
> ++++++++++++++++++++
> drivers/soc/mediatek/mt8365-mmsys.h | 4 +-
> drivers/soc/mediatek/mtk-mmsys.c | 62 ++++
> drivers/soc/mediatek/mtk-mmsys.h | 1 +
> drivers/soc/mediatek/mtk-mutex.c | 8 +-
> include/linux/soc/mediatek/mtk-mmsys.h | 13 +-
> 12 files changed, 461 insertions(+), 17 deletions(-)
> create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
>
[snip]
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> b/drivers/soc/mediatek/mtk-mmsys.c
> index 4fc4c2c9ea20..b2fa239c5f5f 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -4,6 +4,8 @@
> * Author: James Liao <jamesjj.liao@mediatek.com>
> */
>
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> #include <linux/delay.h>
> #include <linux/device.h>
> #include <linux/io.h>
> @@ -17,6 +19,7 @@
> #include "mt8183-mmsys.h"
> #include "mt8186-mmsys.h"
> #include "mt8192-mmsys.h"
> +#include "mt8195-mmsys.h"
> #include "mt8365-mmsys.h"
>
> static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data =
> {
> @@ -72,12 +75,24 @@ static const struct mtk_mmsys_driver_data
> mt8192_mmsys_driver_data = {
> .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
> };
>
> +static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data
> = {
> + .clk_name = "cfg_vdo0",
> + .clk_driver = "clk-mt8195-vdo0",
> + .routes = mmsys_mt8195_routing_table,
> + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> +};
> +
> static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data =
> {
> .clk_driver = "clk-mt8365-mm",
> .routes = mt8365_mmsys_routing_table,
> .num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
> };
>
> +static const struct of_device_id mtk_clk_platform_labels[] = {
> + { .compatible = "mediatek,mt8195-mmsys",
> + .data = (void *)"clk-mt8195"},
> +};
> +
> struct mtk_mmsys {
> void __iomem *regs;
> const struct mtk_mmsys_driver_data *data;
> @@ -85,6 +100,45 @@ struct mtk_mmsys {
> struct reset_controller_dev rcdev;
> };
>
> +static int mtk_mmsys_get_match_data_by_clk_name(const struct
> mtk_mmsys_driver_data **data,
> + struct device *dev)
> +{
> + int i;
> + struct clk *clk;
> + const char *clk_name;
> + const struct of_device_id *of_id =
> of_match_node(mtk_clk_platform_labels,
> + dev->of_node);
> + const struct mtk_mmsys_driver_data *drvdata[] = {
> + &mt8195_vdosys0_driver_data,
> + };
> +
> + if (!of_id || !of_id->data) {
> + dev_err(dev, "Can't find match clk platform labels\n");
> + return -EINVAL;
> + }
> +
> + clk = devm_clk_get(dev, NULL);
> + if (IS_ERR(clk)) {
> + dev_err(dev, "failed to get mmsys clk\n");
> + return PTR_ERR(clk);
> + }
> +
> + clk_name = __clk_get_name(clk);
> + if (!clk_name) {
> + dev_err(dev, "invalid mmsys clk name\n");
> + return -EINVAL;
> + }
> +
> + for (i = 0; i < ARRAY_SIZE(drvdata); i++)
> + if (strncmp(drvdata[i]->clk_name, clk_name,
> strlen(clk_name)) == 0 &&
> + strncmp(drvdata[i]->clk_driver, of_id->data,
> strlen(of_id->data)) == 0) {
I think clk_name is enough to identify the mmsys, why do you need
clk_driver?
> + *data = drvdata[i];
> + return 0;
> + }
> +
> + return -EINVAL;
> +}
> +
> void mtk_mmsys_ddp_connect(struct device *dev,
> enum mtk_ddp_comp_id cur,
> enum mtk_ddp_comp_id next)
> @@ -206,6 +260,11 @@ static int mtk_mmsys_probe(struct
> platform_device *pdev)
> }
>
> mmsys->data = of_device_get_match_data(&pdev->dev);
> + if (!mmsys->data &&
> mtk_mmsys_get_match_data_by_clk_name(&mmsys->data, dev) < 0) {
> + dev_err(dev, "Couldn't get match driver data\n");
> + return -EINVAL;
> + }
> +
> platform_set_drvdata(pdev, mmsys);
>
> clks = platform_device_register_data(&pdev->dev, mmsys->data-
> >clk_driver,
> @@ -260,6 +319,9 @@ static const struct of_device_id
> of_match_mtk_mmsys[] = {
> .compatible = "mediatek,mt8192-mmsys",
> .data = &mt8192_mmsys_driver_data,
> },
> + {
> + .compatible = "mediatek,mt8195-mmsys",
> + },
> {
> .compatible = "mediatek,mt8365-mmsys",
> .data = &mt8365_mmsys_driver_data,
>
[snip]
> b/include/linux/soc/mediatek/mtk-mmsys.h
> index 4bba275e235a..fb719fd1281c 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -16,14 +16,25 @@ enum mtk_ddp_comp_id {
> DDP_COMPONENT_CCORR,
> DDP_COMPONENT_COLOR0,
> DDP_COMPONENT_COLOR1,
> - DDP_COMPONENT_DITHER,
> + DDP_COMPONENT_DITHER0,
I would like soc and drm modification to go through different tree, so
this setting would not modify drm driver in this patch.
DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
Then modify drm driver after this patch.
Regards,
CK
> + DDP_COMPONENT_DITHER1,
> + DDP_COMPONENT_DP_INTF0,
> + DDP_COMPONENT_DP_INTF1,
> DDP_COMPONENT_DPI0,
> DDP_COMPONENT_DPI1,
> + DDP_COMPONENT_DSC0,
> + DDP_COMPONENT_DSC1,
> DDP_COMPONENT_DSI0,
> DDP_COMPONENT_DSI1,
> DDP_COMPONENT_DSI2,
> DDP_COMPONENT_DSI3,
> DDP_COMPONENT_GAMMA,
> + DDP_COMPONENT_MERGE0,
> + DDP_COMPONENT_MERGE1,
> + DDP_COMPONENT_MERGE2,
> + DDP_COMPONENT_MERGE3,
> + DDP_COMPONENT_MERGE4,
> + DDP_COMPONENT_MERGE5,
> DDP_COMPONENT_OD0,
> DDP_COMPONENT_OD1,
> DDP_COMPONENT_OVL0,
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [RESEND v17 3/7] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
2022-04-07 3:04 ` jason-jh.lin
@ 2022-04-07 5:58 ` CK Hu
-1 siblings, 0 replies; 49+ messages in thread
From: CK Hu @ 2022-04-07 5:58 UTC (permalink / raw)
To: jason-jh.lin, Rob Herring, Matthias Brugger, Chun-Kuang Hu,
AngeloGioacchino Del Regno
Cc: David Airlie, singo.chang, Alexandre Torgue, postmaster,
Fabien Parent, John 'Warthog9' Hawley, linux-stm32,
roy-cw.yeh, Project_Global_Chrome_Upstream_Group, Philipp Zabel,
devicetree, Daniel Vetter, nancy.lin, linux-mediatek, hsinyi,
linux-arm-kernel, linux-kernel, moudy.ho, Maxime Coquelin
Hi, Jason:
On Thu, 2022-04-07 at 11:04 +0800, jason-jh.lin wrote:
> 1. Add mt8195 mmsys compatible for vdosys0.
> 2. Add mt8195 routing table settings and fix build fail.
> 3. Add clock name, clock driver name and routing table into the
> driver data
> of mt8195 vdosys0.
> 4. Add get match data by clock name function and clock platform
> labels
> to identify which mmsys node is corresponding to vdosys0.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
>
[snip]
>
> +static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data
> = {
> + .clk_name = "cfg_vdo0",
> + .clk_driver = "clk-mt8195-vdo0",
> + .routes = mmsys_mt8195_routing_table,
> + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> +};
> +
>
[snip]
>
> +static int mtk_mmsys_get_match_data_by_clk_name(const struct
> mtk_mmsys_driver_data **data,
> + struct device *dev)
> +{
> + int i;
> + struct clk *clk;
> + const char *clk_name;
> + const struct of_device_id *of_id =
> of_match_node(mtk_clk_platform_labels,
> + dev->of_node);
> + const struct mtk_mmsys_driver_data *drvdata[] = {
> + &mt8195_vdosys0_driver_data,
> + };
> +
> + if (!of_id || !of_id->data) {
> + dev_err(dev, "Can't find match clk platform labels\n");
> + return -EINVAL;
> + }
> +
> + clk = devm_clk_get(dev, NULL);
> + if (IS_ERR(clk)) {
> + dev_err(dev, "failed to get mmsys clk\n");
> + return PTR_ERR(clk);
> + }
> +
> + clk_name = __clk_get_name(clk);
> + if (!clk_name) {
> + dev_err(dev, "invalid mmsys clk name\n");
> + return -EINVAL;
> + }
> +
> + for (i = 0; i < ARRAY_SIZE(drvdata); i++)
> + if (strncmp(drvdata[i]->clk_name, clk_name,
> strlen(clk_name)) == 0 &&
Why not
strcmp(drvdata[i]->clk_name, clk_name) == 0
Regards,
CK
> + strncmp(drvdata[i]->clk_driver, of_id->data,
> strlen(of_id->data)) == 0) {
> + *data = drvdata[i];
> + return 0;
> + }
> +
> + return -EINVAL;
> +}
> +
>
_______________________________________________
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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [RESEND v17 3/7] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
@ 2022-04-07 5:58 ` CK Hu
0 siblings, 0 replies; 49+ messages in thread
From: CK Hu @ 2022-04-07 5:58 UTC (permalink / raw)
To: jason-jh.lin, Rob Herring, Matthias Brugger, Chun-Kuang Hu,
AngeloGioacchino Del Regno
Cc: David Airlie, singo.chang, Alexandre Torgue, postmaster,
Fabien Parent, John 'Warthog9' Hawley, linux-stm32,
roy-cw.yeh, Project_Global_Chrome_Upstream_Group, Philipp Zabel,
devicetree, Daniel Vetter, nancy.lin, linux-mediatek, hsinyi,
linux-arm-kernel, linux-kernel, moudy.ho, Maxime Coquelin
Hi, Jason:
On Thu, 2022-04-07 at 11:04 +0800, jason-jh.lin wrote:
> 1. Add mt8195 mmsys compatible for vdosys0.
> 2. Add mt8195 routing table settings and fix build fail.
> 3. Add clock name, clock driver name and routing table into the
> driver data
> of mt8195 vdosys0.
> 4. Add get match data by clock name function and clock platform
> labels
> to identify which mmsys node is corresponding to vdosys0.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
>
[snip]
>
> +static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data
> = {
> + .clk_name = "cfg_vdo0",
> + .clk_driver = "clk-mt8195-vdo0",
> + .routes = mmsys_mt8195_routing_table,
> + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> +};
> +
>
[snip]
>
> +static int mtk_mmsys_get_match_data_by_clk_name(const struct
> mtk_mmsys_driver_data **data,
> + struct device *dev)
> +{
> + int i;
> + struct clk *clk;
> + const char *clk_name;
> + const struct of_device_id *of_id =
> of_match_node(mtk_clk_platform_labels,
> + dev->of_node);
> + const struct mtk_mmsys_driver_data *drvdata[] = {
> + &mt8195_vdosys0_driver_data,
> + };
> +
> + if (!of_id || !of_id->data) {
> + dev_err(dev, "Can't find match clk platform labels\n");
> + return -EINVAL;
> + }
> +
> + clk = devm_clk_get(dev, NULL);
> + if (IS_ERR(clk)) {
> + dev_err(dev, "failed to get mmsys clk\n");
> + return PTR_ERR(clk);
> + }
> +
> + clk_name = __clk_get_name(clk);
> + if (!clk_name) {
> + dev_err(dev, "invalid mmsys clk name\n");
> + return -EINVAL;
> + }
> +
> + for (i = 0; i < ARRAY_SIZE(drvdata); i++)
> + if (strncmp(drvdata[i]->clk_name, clk_name,
> strlen(clk_name)) == 0 &&
Why not
strcmp(drvdata[i]->clk_name, clk_name) == 0
Regards,
CK
> + strncmp(drvdata[i]->clk_driver, of_id->data,
> strlen(of_id->data)) == 0) {
> + *data = drvdata[i];
> + return 0;
> + }
> +
> + return -EINVAL;
> +}
> +
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [RESEND v17 3/7] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
2022-04-07 5:45 ` CK Hu
(?)
@ 2022-04-07 6:27 ` Jason-JH Lin
-1 siblings, 0 replies; 49+ messages in thread
From: Jason-JH Lin @ 2022-04-07 6:27 UTC (permalink / raw)
To: CK Hu, Rob Herring, Matthias Brugger, Chun-Kuang Hu,
AngeloGioacchino Del Regno
Cc: David Airlie, singo.chang, Alexandre Torgue, postmaster,
Fabien Parent, John 'Warthog9' Hawley, linux-stm32,
roy-cw.yeh, Project_Global_Chrome_Upstream_Group, Philipp Zabel,
devicetree, Daniel Vetter, nancy.lin, linux-mediatek, hsinyi,
linux-arm-kernel, linux-kernel, moudy.ho, Maxime Coquelin
Hi CK,
Thanks for the reviews.
On Thu, 2022-04-07 at 13:45 +0800, CK Hu wrote:
> Hi, Jason:
>
> On Thu, 2022-04-07 at 11:04 +0800, jason-jh.lin wrote:
> > 1. Add mt8195 mmsys compatible for vdosys0.
> > 2. Add mt8195 routing table settings and fix build fail.
> > 3. Add clock name, clock driver name and routing table into the
> > driver data
> > of mt8195 vdosys0.
> > 4. Add get match data by clock name function and clock platform
> > labels
> > to identify which mmsys node is corresponding to vdosys0.
> >
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
> > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 6 +-
> > drivers/soc/mediatek/mt8167-mmsys.h | 2 +-
> > drivers/soc/mediatek/mt8183-mmsys.h | 2 +-
> > drivers/soc/mediatek/mt8186-mmsys.h | 4 +-
> > drivers/soc/mediatek/mt8192-mmsys.h | 4 +-
> > drivers/soc/mediatek/mt8195-mmsys.h | 370
> > ++++++++++++++++++++
> > drivers/soc/mediatek/mt8365-mmsys.h | 4 +-
> > drivers/soc/mediatek/mtk-mmsys.c | 62 ++++
> > drivers/soc/mediatek/mtk-mmsys.h | 1 +
> > drivers/soc/mediatek/mtk-mutex.c | 8 +-
> > include/linux/soc/mediatek/mtk-mmsys.h | 13 +-
> > 12 files changed, 461 insertions(+), 17 deletions(-)
> > create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
> >
>
> [snip]
>
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > b/drivers/soc/mediatek/mtk-mmsys.c
> > index 4fc4c2c9ea20..b2fa239c5f5f 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > @@ -4,6 +4,8 @@
> > * Author: James Liao <jamesjj.liao@mediatek.com>
> > */
> >
> > +#include <linux/clk.h>
> > +#include <linux/clk-provider.h>
> > #include <linux/delay.h>
> > #include <linux/device.h>
> > #include <linux/io.h>
> > @@ -17,6 +19,7 @@
> > #include "mt8183-mmsys.h"
> > #include "mt8186-mmsys.h"
> > #include "mt8192-mmsys.h"
> > +#include "mt8195-mmsys.h"
> > #include "mt8365-mmsys.h"
> >
> > static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data
> > =
> > {
> > @@ -72,12 +75,24 @@ static const struct mtk_mmsys_driver_data
> > mt8192_mmsys_driver_data = {
> > .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
> > };
> >
> > +static const struct mtk_mmsys_driver_data
> > mt8195_vdosys0_driver_data
> > = {
> > + .clk_name = "cfg_vdo0",
> > + .clk_driver = "clk-mt8195-vdo0",
> > + .routes = mmsys_mt8195_routing_table,
> > + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > +};
> > +
> > static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data
> > =
> > {
> > .clk_driver = "clk-mt8365-mm",
> > .routes = mt8365_mmsys_routing_table,
> > .num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
> > };
> >
> > +static const struct of_device_id mtk_clk_platform_labels[] = {
> > + { .compatible = "mediatek,mt8195-mmsys",
> > + .data = (void *)"clk-mt8195"},
> > +};
> > +
> > struct mtk_mmsys {
> > void __iomem *regs;
> > const struct mtk_mmsys_driver_data *data;
> > @@ -85,6 +100,45 @@ struct mtk_mmsys {
> > struct reset_controller_dev rcdev;
> > };
> >
> > +static int mtk_mmsys_get_match_data_by_clk_name(const struct
> > mtk_mmsys_driver_data **data,
> > + struct device *dev)
> > +{
> > + int i;
> > + struct clk *clk;
> > + const char *clk_name;
> > + const struct of_device_id *of_id =
> > of_match_node(mtk_clk_platform_labels,
> > + dev->of_node);
> > + const struct mtk_mmsys_driver_data *drvdata[] = {
> > + &mt8195_vdosys0_driver_data,
> > + };
> > +
> > + if (!of_id || !of_id->data) {
> > + dev_err(dev, "Can't find match clk platform labels\n");
> > + return -EINVAL;
> > + }
> > +
> > + clk = devm_clk_get(dev, NULL);
> > + if (IS_ERR(clk)) {
> > + dev_err(dev, "failed to get mmsys clk\n");
> > + return PTR_ERR(clk);
> > + }
> > +
> > + clk_name = __clk_get_name(clk);
> > + if (!clk_name) {
> > + dev_err(dev, "invalid mmsys clk name\n");
> > + return -EINVAL;
> > + }
> > +
> > + for (i = 0; i < ARRAY_SIZE(drvdata); i++)
> > + if (strncmp(drvdata[i]->clk_name, clk_name,
> > strlen(clk_name)) == 0 &&
> > + strncmp(drvdata[i]->clk_driver, of_id->data,
> > strlen(of_id->data)) == 0) {
>
> I think clk_name is enough to identify the mmsys, why do you need
> clk_driver?
I think there might be another chip that needs to get driver data by
clk_name .
So I use "clk-mt8195" in clk_driver to identify the corresponding
platform whose clk_name of mmsys is also "cfg_vod0".
> > + *data = drvdata[i];
> > + return 0;
> > + }
> > +
> > + return -EINVAL;
> > +}
> > +
> > void mtk_mmsys_ddp_connect(struct device *dev,
> > enum mtk_ddp_comp_id cur,
> > enum mtk_ddp_comp_id next)
> > @@ -206,6 +260,11 @@ static int mtk_mmsys_probe(struct
> > platform_device *pdev)
> > }
> >
> > mmsys->data = of_device_get_match_data(&pdev->dev);
> > + if (!mmsys->data &&
> > mtk_mmsys_get_match_data_by_clk_name(&mmsys->data, dev) < 0) {
> > + dev_err(dev, "Couldn't get match driver data\n");
> > + return -EINVAL;
> > + }
> > +
> > platform_set_drvdata(pdev, mmsys);
> >
> > clks = platform_device_register_data(&pdev->dev, mmsys->data-
> > > clk_driver,
> >
> > @@ -260,6 +319,9 @@ static const struct of_device_id
> > of_match_mtk_mmsys[] = {
> > .compatible = "mediatek,mt8192-mmsys",
> > .data = &mt8192_mmsys_driver_data,
> > },
> > + {
> > + .compatible = "mediatek,mt8195-mmsys",
> > + },
> > {
> > .compatible = "mediatek,mt8365-mmsys",
> > .data = &mt8365_mmsys_driver_data,
> >
>
> [snip]
>
> > b/include/linux/soc/mediatek/mtk-mmsys.h
> > index 4bba275e235a..fb719fd1281c 100644
> > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > @@ -16,14 +16,25 @@ enum mtk_ddp_comp_id {
> > DDP_COMPONENT_CCORR,
> > DDP_COMPONENT_COLOR0,
> > DDP_COMPONENT_COLOR1,
> > - DDP_COMPONENT_DITHER,
> > + DDP_COMPONENT_DITHER0,
>
> I would like soc and drm modification to go through different tree,
> so
> this setting would not modify drm driver in this patch.
>
> DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
>
> Then modify drm driver after this patch.
>
> Regards,
> CK
OK, I will use this modification at the next version.
Thanks!
Regards,
Jason-JH.Lin
>
> > + DDP_COMPONENT_DITHER1,
> > + DDP_COMPONENT_DP_INTF0,
> > + DDP_COMPONENT_DP_INTF1,
> > DDP_COMPONENT_DPI0,
> > DDP_COMPONENT_DPI1,
> > + DDP_COMPONENT_DSC0,
> > + DDP_COMPONENT_DSC1,
> > DDP_COMPONENT_DSI0,
> > DDP_COMPONENT_DSI1,
> > DDP_COMPONENT_DSI2,
> > DDP_COMPONENT_DSI3,
> > DDP_COMPONENT_GAMMA,
> > + DDP_COMPONENT_MERGE0,
> > + DDP_COMPONENT_MERGE1,
> > + DDP_COMPONENT_MERGE2,
> > + DDP_COMPONENT_MERGE3,
> > + DDP_COMPONENT_MERGE4,
> > + DDP_COMPONENT_MERGE5,
> > DDP_COMPONENT_OD0,
> > DDP_COMPONENT_OD1,
> > DDP_COMPONENT_OVL0,
>
>
--
Jason-JH Lin <jason-jh.lin@mediatek.com>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [RESEND v17 3/7] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
@ 2022-04-07 6:27 ` Jason-JH Lin
0 siblings, 0 replies; 49+ messages in thread
From: Jason-JH Lin @ 2022-04-07 6:27 UTC (permalink / raw)
To: CK Hu, Rob Herring, Matthias Brugger, Chun-Kuang Hu,
AngeloGioacchino Del Regno
Cc: David Airlie, singo.chang, Alexandre Torgue, postmaster,
Fabien Parent, John 'Warthog9' Hawley, linux-stm32,
roy-cw.yeh, Project_Global_Chrome_Upstream_Group, Philipp Zabel,
devicetree, Daniel Vetter, nancy.lin, linux-mediatek, hsinyi,
linux-arm-kernel, linux-kernel, moudy.ho, Maxime Coquelin
Hi CK,
Thanks for the reviews.
On Thu, 2022-04-07 at 13:45 +0800, CK Hu wrote:
> Hi, Jason:
>
> On Thu, 2022-04-07 at 11:04 +0800, jason-jh.lin wrote:
> > 1. Add mt8195 mmsys compatible for vdosys0.
> > 2. Add mt8195 routing table settings and fix build fail.
> > 3. Add clock name, clock driver name and routing table into the
> > driver data
> > of mt8195 vdosys0.
> > 4. Add get match data by clock name function and clock platform
> > labels
> > to identify which mmsys node is corresponding to vdosys0.
> >
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
> > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 6 +-
> > drivers/soc/mediatek/mt8167-mmsys.h | 2 +-
> > drivers/soc/mediatek/mt8183-mmsys.h | 2 +-
> > drivers/soc/mediatek/mt8186-mmsys.h | 4 +-
> > drivers/soc/mediatek/mt8192-mmsys.h | 4 +-
> > drivers/soc/mediatek/mt8195-mmsys.h | 370
> > ++++++++++++++++++++
> > drivers/soc/mediatek/mt8365-mmsys.h | 4 +-
> > drivers/soc/mediatek/mtk-mmsys.c | 62 ++++
> > drivers/soc/mediatek/mtk-mmsys.h | 1 +
> > drivers/soc/mediatek/mtk-mutex.c | 8 +-
> > include/linux/soc/mediatek/mtk-mmsys.h | 13 +-
> > 12 files changed, 461 insertions(+), 17 deletions(-)
> > create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
> >
>
> [snip]
>
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > b/drivers/soc/mediatek/mtk-mmsys.c
> > index 4fc4c2c9ea20..b2fa239c5f5f 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > @@ -4,6 +4,8 @@
> > * Author: James Liao <jamesjj.liao@mediatek.com>
> > */
> >
> > +#include <linux/clk.h>
> > +#include <linux/clk-provider.h>
> > #include <linux/delay.h>
> > #include <linux/device.h>
> > #include <linux/io.h>
> > @@ -17,6 +19,7 @@
> > #include "mt8183-mmsys.h"
> > #include "mt8186-mmsys.h"
> > #include "mt8192-mmsys.h"
> > +#include "mt8195-mmsys.h"
> > #include "mt8365-mmsys.h"
> >
> > static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data
> > =
> > {
> > @@ -72,12 +75,24 @@ static const struct mtk_mmsys_driver_data
> > mt8192_mmsys_driver_data = {
> > .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
> > };
> >
> > +static const struct mtk_mmsys_driver_data
> > mt8195_vdosys0_driver_data
> > = {
> > + .clk_name = "cfg_vdo0",
> > + .clk_driver = "clk-mt8195-vdo0",
> > + .routes = mmsys_mt8195_routing_table,
> > + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > +};
> > +
> > static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data
> > =
> > {
> > .clk_driver = "clk-mt8365-mm",
> > .routes = mt8365_mmsys_routing_table,
> > .num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
> > };
> >
> > +static const struct of_device_id mtk_clk_platform_labels[] = {
> > + { .compatible = "mediatek,mt8195-mmsys",
> > + .data = (void *)"clk-mt8195"},
> > +};
> > +
> > struct mtk_mmsys {
> > void __iomem *regs;
> > const struct mtk_mmsys_driver_data *data;
> > @@ -85,6 +100,45 @@ struct mtk_mmsys {
> > struct reset_controller_dev rcdev;
> > };
> >
> > +static int mtk_mmsys_get_match_data_by_clk_name(const struct
> > mtk_mmsys_driver_data **data,
> > + struct device *dev)
> > +{
> > + int i;
> > + struct clk *clk;
> > + const char *clk_name;
> > + const struct of_device_id *of_id =
> > of_match_node(mtk_clk_platform_labels,
> > + dev->of_node);
> > + const struct mtk_mmsys_driver_data *drvdata[] = {
> > + &mt8195_vdosys0_driver_data,
> > + };
> > +
> > + if (!of_id || !of_id->data) {
> > + dev_err(dev, "Can't find match clk platform labels\n");
> > + return -EINVAL;
> > + }
> > +
> > + clk = devm_clk_get(dev, NULL);
> > + if (IS_ERR(clk)) {
> > + dev_err(dev, "failed to get mmsys clk\n");
> > + return PTR_ERR(clk);
> > + }
> > +
> > + clk_name = __clk_get_name(clk);
> > + if (!clk_name) {
> > + dev_err(dev, "invalid mmsys clk name\n");
> > + return -EINVAL;
> > + }
> > +
> > + for (i = 0; i < ARRAY_SIZE(drvdata); i++)
> > + if (strncmp(drvdata[i]->clk_name, clk_name,
> > strlen(clk_name)) == 0 &&
> > + strncmp(drvdata[i]->clk_driver, of_id->data,
> > strlen(of_id->data)) == 0) {
>
> I think clk_name is enough to identify the mmsys, why do you need
> clk_driver?
I think there might be another chip that needs to get driver data by
clk_name .
So I use "clk-mt8195" in clk_driver to identify the corresponding
platform whose clk_name of mmsys is also "cfg_vod0".
> > + *data = drvdata[i];
> > + return 0;
> > + }
> > +
> > + return -EINVAL;
> > +}
> > +
> > void mtk_mmsys_ddp_connect(struct device *dev,
> > enum mtk_ddp_comp_id cur,
> > enum mtk_ddp_comp_id next)
> > @@ -206,6 +260,11 @@ static int mtk_mmsys_probe(struct
> > platform_device *pdev)
> > }
> >
> > mmsys->data = of_device_get_match_data(&pdev->dev);
> > + if (!mmsys->data &&
> > mtk_mmsys_get_match_data_by_clk_name(&mmsys->data, dev) < 0) {
> > + dev_err(dev, "Couldn't get match driver data\n");
> > + return -EINVAL;
> > + }
> > +
> > platform_set_drvdata(pdev, mmsys);
> >
> > clks = platform_device_register_data(&pdev->dev, mmsys->data-
> > > clk_driver,
> >
> > @@ -260,6 +319,9 @@ static const struct of_device_id
> > of_match_mtk_mmsys[] = {
> > .compatible = "mediatek,mt8192-mmsys",
> > .data = &mt8192_mmsys_driver_data,
> > },
> > + {
> > + .compatible = "mediatek,mt8195-mmsys",
> > + },
> > {
> > .compatible = "mediatek,mt8365-mmsys",
> > .data = &mt8365_mmsys_driver_data,
> >
>
> [snip]
>
> > b/include/linux/soc/mediatek/mtk-mmsys.h
> > index 4bba275e235a..fb719fd1281c 100644
> > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > @@ -16,14 +16,25 @@ enum mtk_ddp_comp_id {
> > DDP_COMPONENT_CCORR,
> > DDP_COMPONENT_COLOR0,
> > DDP_COMPONENT_COLOR1,
> > - DDP_COMPONENT_DITHER,
> > + DDP_COMPONENT_DITHER0,
>
> I would like soc and drm modification to go through different tree,
> so
> this setting would not modify drm driver in this patch.
>
> DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
>
> Then modify drm driver after this patch.
>
> Regards,
> CK
OK, I will use this modification at the next version.
Thanks!
Regards,
Jason-JH.Lin
>
> > + DDP_COMPONENT_DITHER1,
> > + DDP_COMPONENT_DP_INTF0,
> > + DDP_COMPONENT_DP_INTF1,
> > DDP_COMPONENT_DPI0,
> > DDP_COMPONENT_DPI1,
> > + DDP_COMPONENT_DSC0,
> > + DDP_COMPONENT_DSC1,
> > DDP_COMPONENT_DSI0,
> > DDP_COMPONENT_DSI1,
> > DDP_COMPONENT_DSI2,
> > DDP_COMPONENT_DSI3,
> > DDP_COMPONENT_GAMMA,
> > + DDP_COMPONENT_MERGE0,
> > + DDP_COMPONENT_MERGE1,
> > + DDP_COMPONENT_MERGE2,
> > + DDP_COMPONENT_MERGE3,
> > + DDP_COMPONENT_MERGE4,
> > + DDP_COMPONENT_MERGE5,
> > DDP_COMPONENT_OD0,
> > DDP_COMPONENT_OD1,
> > DDP_COMPONENT_OVL0,
>
>
--
Jason-JH Lin <jason-jh.lin@mediatek.com>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [RESEND v17 3/7] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
@ 2022-04-07 6:27 ` Jason-JH Lin
0 siblings, 0 replies; 49+ messages in thread
From: Jason-JH Lin @ 2022-04-07 6:27 UTC (permalink / raw)
To: CK Hu, Rob Herring, Matthias Brugger, Chun-Kuang Hu,
AngeloGioacchino Del Regno
Cc: David Airlie, singo.chang, Alexandre Torgue, postmaster,
Fabien Parent, John 'Warthog9' Hawley, linux-stm32,
roy-cw.yeh, Project_Global_Chrome_Upstream_Group, Philipp Zabel,
devicetree, Daniel Vetter, nancy.lin, linux-mediatek, hsinyi,
linux-arm-kernel, linux-kernel, moudy.ho, Maxime Coquelin
Hi CK,
Thanks for the reviews.
On Thu, 2022-04-07 at 13:45 +0800, CK Hu wrote:
> Hi, Jason:
>
> On Thu, 2022-04-07 at 11:04 +0800, jason-jh.lin wrote:
> > 1. Add mt8195 mmsys compatible for vdosys0.
> > 2. Add mt8195 routing table settings and fix build fail.
> > 3. Add clock name, clock driver name and routing table into the
> > driver data
> > of mt8195 vdosys0.
> > 4. Add get match data by clock name function and clock platform
> > labels
> > to identify which mmsys node is corresponding to vdosys0.
> >
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
> > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 6 +-
> > drivers/soc/mediatek/mt8167-mmsys.h | 2 +-
> > drivers/soc/mediatek/mt8183-mmsys.h | 2 +-
> > drivers/soc/mediatek/mt8186-mmsys.h | 4 +-
> > drivers/soc/mediatek/mt8192-mmsys.h | 4 +-
> > drivers/soc/mediatek/mt8195-mmsys.h | 370
> > ++++++++++++++++++++
> > drivers/soc/mediatek/mt8365-mmsys.h | 4 +-
> > drivers/soc/mediatek/mtk-mmsys.c | 62 ++++
> > drivers/soc/mediatek/mtk-mmsys.h | 1 +
> > drivers/soc/mediatek/mtk-mutex.c | 8 +-
> > include/linux/soc/mediatek/mtk-mmsys.h | 13 +-
> > 12 files changed, 461 insertions(+), 17 deletions(-)
> > create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
> >
>
> [snip]
>
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > b/drivers/soc/mediatek/mtk-mmsys.c
> > index 4fc4c2c9ea20..b2fa239c5f5f 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > @@ -4,6 +4,8 @@
> > * Author: James Liao <jamesjj.liao@mediatek.com>
> > */
> >
> > +#include <linux/clk.h>
> > +#include <linux/clk-provider.h>
> > #include <linux/delay.h>
> > #include <linux/device.h>
> > #include <linux/io.h>
> > @@ -17,6 +19,7 @@
> > #include "mt8183-mmsys.h"
> > #include "mt8186-mmsys.h"
> > #include "mt8192-mmsys.h"
> > +#include "mt8195-mmsys.h"
> > #include "mt8365-mmsys.h"
> >
> > static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data
> > =
> > {
> > @@ -72,12 +75,24 @@ static const struct mtk_mmsys_driver_data
> > mt8192_mmsys_driver_data = {
> > .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
> > };
> >
> > +static const struct mtk_mmsys_driver_data
> > mt8195_vdosys0_driver_data
> > = {
> > + .clk_name = "cfg_vdo0",
> > + .clk_driver = "clk-mt8195-vdo0",
> > + .routes = mmsys_mt8195_routing_table,
> > + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > +};
> > +
> > static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data
> > =
> > {
> > .clk_driver = "clk-mt8365-mm",
> > .routes = mt8365_mmsys_routing_table,
> > .num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
> > };
> >
> > +static const struct of_device_id mtk_clk_platform_labels[] = {
> > + { .compatible = "mediatek,mt8195-mmsys",
> > + .data = (void *)"clk-mt8195"},
> > +};
> > +
> > struct mtk_mmsys {
> > void __iomem *regs;
> > const struct mtk_mmsys_driver_data *data;
> > @@ -85,6 +100,45 @@ struct mtk_mmsys {
> > struct reset_controller_dev rcdev;
> > };
> >
> > +static int mtk_mmsys_get_match_data_by_clk_name(const struct
> > mtk_mmsys_driver_data **data,
> > + struct device *dev)
> > +{
> > + int i;
> > + struct clk *clk;
> > + const char *clk_name;
> > + const struct of_device_id *of_id =
> > of_match_node(mtk_clk_platform_labels,
> > + dev->of_node);
> > + const struct mtk_mmsys_driver_data *drvdata[] = {
> > + &mt8195_vdosys0_driver_data,
> > + };
> > +
> > + if (!of_id || !of_id->data) {
> > + dev_err(dev, "Can't find match clk platform labels\n");
> > + return -EINVAL;
> > + }
> > +
> > + clk = devm_clk_get(dev, NULL);
> > + if (IS_ERR(clk)) {
> > + dev_err(dev, "failed to get mmsys clk\n");
> > + return PTR_ERR(clk);
> > + }
> > +
> > + clk_name = __clk_get_name(clk);
> > + if (!clk_name) {
> > + dev_err(dev, "invalid mmsys clk name\n");
> > + return -EINVAL;
> > + }
> > +
> > + for (i = 0; i < ARRAY_SIZE(drvdata); i++)
> > + if (strncmp(drvdata[i]->clk_name, clk_name,
> > strlen(clk_name)) == 0 &&
> > + strncmp(drvdata[i]->clk_driver, of_id->data,
> > strlen(of_id->data)) == 0) {
>
> I think clk_name is enough to identify the mmsys, why do you need
> clk_driver?
I think there might be another chip that needs to get driver data by
clk_name .
So I use "clk-mt8195" in clk_driver to identify the corresponding
platform whose clk_name of mmsys is also "cfg_vod0".
> > + *data = drvdata[i];
> > + return 0;
> > + }
> > +
> > + return -EINVAL;
> > +}
> > +
> > void mtk_mmsys_ddp_connect(struct device *dev,
> > enum mtk_ddp_comp_id cur,
> > enum mtk_ddp_comp_id next)
> > @@ -206,6 +260,11 @@ static int mtk_mmsys_probe(struct
> > platform_device *pdev)
> > }
> >
> > mmsys->data = of_device_get_match_data(&pdev->dev);
> > + if (!mmsys->data &&
> > mtk_mmsys_get_match_data_by_clk_name(&mmsys->data, dev) < 0) {
> > + dev_err(dev, "Couldn't get match driver data\n");
> > + return -EINVAL;
> > + }
> > +
> > platform_set_drvdata(pdev, mmsys);
> >
> > clks = platform_device_register_data(&pdev->dev, mmsys->data-
> > > clk_driver,
> >
> > @@ -260,6 +319,9 @@ static const struct of_device_id
> > of_match_mtk_mmsys[] = {
> > .compatible = "mediatek,mt8192-mmsys",
> > .data = &mt8192_mmsys_driver_data,
> > },
> > + {
> > + .compatible = "mediatek,mt8195-mmsys",
> > + },
> > {
> > .compatible = "mediatek,mt8365-mmsys",
> > .data = &mt8365_mmsys_driver_data,
> >
>
> [snip]
>
> > b/include/linux/soc/mediatek/mtk-mmsys.h
> > index 4bba275e235a..fb719fd1281c 100644
> > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > @@ -16,14 +16,25 @@ enum mtk_ddp_comp_id {
> > DDP_COMPONENT_CCORR,
> > DDP_COMPONENT_COLOR0,
> > DDP_COMPONENT_COLOR1,
> > - DDP_COMPONENT_DITHER,
> > + DDP_COMPONENT_DITHER0,
>
> I would like soc and drm modification to go through different tree,
> so
> this setting would not modify drm driver in this patch.
>
> DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
>
> Then modify drm driver after this patch.
>
> Regards,
> CK
OK, I will use this modification at the next version.
Thanks!
Regards,
Jason-JH.Lin
>
> > + DDP_COMPONENT_DITHER1,
> > + DDP_COMPONENT_DP_INTF0,
> > + DDP_COMPONENT_DP_INTF1,
> > DDP_COMPONENT_DPI0,
> > DDP_COMPONENT_DPI1,
> > + DDP_COMPONENT_DSC0,
> > + DDP_COMPONENT_DSC1,
> > DDP_COMPONENT_DSI0,
> > DDP_COMPONENT_DSI1,
> > DDP_COMPONENT_DSI2,
> > DDP_COMPONENT_DSI3,
> > DDP_COMPONENT_GAMMA,
> > + DDP_COMPONENT_MERGE0,
> > + DDP_COMPONENT_MERGE1,
> > + DDP_COMPONENT_MERGE2,
> > + DDP_COMPONENT_MERGE3,
> > + DDP_COMPONENT_MERGE4,
> > + DDP_COMPONENT_MERGE5,
> > DDP_COMPONENT_OD0,
> > DDP_COMPONENT_OD1,
> > DDP_COMPONENT_OVL0,
>
>
--
Jason-JH Lin <jason-jh.lin@mediatek.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [RESEND v17 2/7] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
2022-04-07 3:04 ` jason-jh.lin
(?)
@ 2022-04-07 8:30 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 49+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-04-07 8:30 UTC (permalink / raw)
To: jason-jh.lin, Rob Herring, Matthias Brugger, Chun-Kuang Hu
Cc: Philipp Zabel, Maxime Coquelin, David Airlie, Daniel Vetter,
Alexandre Torgue, John 'Warthog9' Hawley, postmaster,
hsinyi, fshao, moudy.ho, roy-cw.yeh, CK Hu, Fabien Parent,
nancy.lin, singo.chang, devicetree, linux-stm32,
linux-arm-kernel, linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group
Il 07/04/22 05:04, jason-jh.lin ha scritto:
> In the SoC before, such as mt8173, it has 2 pipelines binding to one
> mmsys with the same clock driver and the same power domain.
>
> In mt8195, there are 4 pipelines binding to 4 different mmsys, such as
> vdosys0, vdosys1, vppsys0 and vppsys1.
> Each mmsys uses different clock drivers and different power domain.
>
> Since each mmsys has its own clock, they could be identified
> by the different name of their clock.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [RESEND v17 2/7] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
@ 2022-04-07 8:30 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 49+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-04-07 8:30 UTC (permalink / raw)
To: jason-jh.lin, Rob Herring, Matthias Brugger, Chun-Kuang Hu
Cc: devicetree, Maxime Coquelin, David Airlie, linux-kernel,
singo.chang, hsinyi, Alexandre Torgue, postmaster,
Project_Global_Chrome_Upstream_Group, Fabien Parent, moudy.ho,
linux-mediatek, roy-cw.yeh, Daniel Vetter,
John 'Warthog9' Hawley, CK Hu, Philipp Zabel, nancy.lin,
linux-stm32, linux-arm-kernel
Il 07/04/22 05:04, jason-jh.lin ha scritto:
> In the SoC before, such as mt8173, it has 2 pipelines binding to one
> mmsys with the same clock driver and the same power domain.
>
> In mt8195, there are 4 pipelines binding to 4 different mmsys, such as
> vdosys0, vdosys1, vppsys0 and vppsys1.
> Each mmsys uses different clock drivers and different power domain.
>
> Since each mmsys has its own clock, they could be identified
> by the different name of their clock.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [RESEND v17 2/7] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
@ 2022-04-07 8:30 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 49+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-04-07 8:30 UTC (permalink / raw)
To: jason-jh.lin, Rob Herring, Matthias Brugger, Chun-Kuang Hu
Cc: Philipp Zabel, Maxime Coquelin, David Airlie, Daniel Vetter,
Alexandre Torgue, John 'Warthog9' Hawley, postmaster,
hsinyi, fshao, moudy.ho, roy-cw.yeh, CK Hu, Fabien Parent,
nancy.lin, singo.chang, devicetree, linux-stm32,
linux-arm-kernel, linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group
Il 07/04/22 05:04, jason-jh.lin ha scritto:
> In the SoC before, such as mt8173, it has 2 pipelines binding to one
> mmsys with the same clock driver and the same power domain.
>
> In mt8195, there are 4 pipelines binding to 4 different mmsys, such as
> vdosys0, vdosys1, vppsys0 and vppsys1.
> Each mmsys uses different clock drivers and different power domain.
>
> Since each mmsys has its own clock, they could be identified
> by the different name of their clock.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [RESEND v17 3/7] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
2022-04-07 3:04 ` jason-jh.lin
(?)
@ 2022-04-07 9:11 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 49+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-04-07 9:11 UTC (permalink / raw)
To: jason-jh.lin, Rob Herring, Matthias Brugger, Chun-Kuang Hu
Cc: Philipp Zabel, Maxime Coquelin, David Airlie, Daniel Vetter,
Alexandre Torgue, John 'Warthog9' Hawley, postmaster,
hsinyi, fshao, moudy.ho, roy-cw.yeh, CK Hu, Fabien Parent,
nancy.lin, singo.chang, devicetree, linux-stm32,
linux-arm-kernel, linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group
Il 07/04/22 05:04, jason-jh.lin ha scritto:
> 1. Add mt8195 mmsys compatible for vdosys0.
> 2. Add mt8195 routing table settings and fix build fail.
> 3. Add clock name, clock driver name and routing table into the driver data
> of mt8195 vdosys0.
> 4. Add get match data by clock name function and clock platform labels
> to identify which mmsys node is corresponding to vdosys0.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 6 +-
> drivers/soc/mediatek/mt8167-mmsys.h | 2 +-
> drivers/soc/mediatek/mt8183-mmsys.h | 2 +-
> drivers/soc/mediatek/mt8186-mmsys.h | 4 +-
> drivers/soc/mediatek/mt8192-mmsys.h | 4 +-
> drivers/soc/mediatek/mt8195-mmsys.h | 370 ++++++++++++++++++++
> drivers/soc/mediatek/mt8365-mmsys.h | 4 +-
> drivers/soc/mediatek/mtk-mmsys.c | 62 ++++
> drivers/soc/mediatek/mtk-mmsys.h | 1 +
> drivers/soc/mediatek/mtk-mutex.c | 8 +-
> include/linux/soc/mediatek/mtk-mmsys.h | 13 +-
> 12 files changed, 461 insertions(+), 17 deletions(-)
> create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
>
..snip..
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index 4fc4c2c9ea20..b2fa239c5f5f 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -4,6 +4,8 @@
> * Author: James Liao <jamesjj.liao@mediatek.com>
> */
>
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> #include <linux/delay.h>
> #include <linux/device.h>
> #include <linux/io.h>
> @@ -17,6 +19,7 @@
> #include "mt8183-mmsys.h"
> #include "mt8186-mmsys.h"
> #include "mt8192-mmsys.h"
> +#include "mt8195-mmsys.h"
> #include "mt8365-mmsys.h"
>
> static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
> @@ -72,12 +75,24 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
> .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
> };
>
> +static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
> + .clk_name = "cfg_vdo0",
> + .clk_driver = "clk-mt8195-vdo0",
> + .routes = mmsys_mt8195_routing_table,
> + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> +};
> +
> static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
> .clk_driver = "clk-mt8365-mm",
> .routes = mt8365_mmsys_routing_table,
> .num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
> };
>
> +static const struct of_device_id mtk_clk_platform_labels[] = {
> + { .compatible = "mediatek,mt8195-mmsys",
> + .data = (void *)"clk-mt8195"},
I have a hunch that MT8195 won't be the first and last SoC having multiple
mmsys channels. I would tend to think that there will be more....
....so, to make it clean from the beginning, I think that you should, at
this point, assign a struct to that .data pointer, instead of declaring a
drvdata struct into mtk_mmsys_get_match_data_by_clk_name().
Besides, I think that this kind of usage for __clk_get_name() may be an API
abuse... but I'm not sure about that... in any case:
- if it's not an abuse, then you should simply pass mt8195_vdosys0_driver_data,
or an array of pointers to mtk_mmsys_driver_data;
- if this is an abuse, you can do the same checks by looking at the iostart
(mmio base address) of the vdosys{0,1} node(s).
Honestly, though, I'm not even sure that you need this different of_device_id
array here... since you could simply wrap the mtk_mmsys_driver_data in the
of_match_mtk_mmsys that you have below... here's another idea:
struct mtk_mmsys_match_data {
const struct mtk_mmsys_driver_data *drv_data[];
unsigned short num_drv_data;
};
...so that:
static int some_function_handling_multi_mmsys(struct mtk_mmsys *mmsys,
struct mtk_mmsys_match_data *match)
{
int i;
i = [ logic to find the right match->drv_data entry here ]
return i;
}
static int mtk_mmsys_probe()
{
.... variables, something else ....
if (match_data->num_drv_data > 1) {
/* This SoC has multiple mmsys channels */
ret = some_function_handling_multi_mmsys(mmsys);
if (ret < 0)
return ret;
mmsys->data = match_data->drv_data[ret];
} else {
dev_dbg(dev, "Using single mmsys channel\n");
mmsys->data = match_data->drv_data[0];
}
...everything else that mtk_mmsys_probe does ...
}
What I'm trying to communicate with this is that the currently chosen solution
looks a bit fragile and needs to be made robust.
In comparison, even if it's not technically right to have two different compatibles
for the same hardware (and shall not be done), the former solution, even if wrong,
was more robust than this one, imo.
Regards,
Angelo
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [RESEND v17 3/7] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
@ 2022-04-07 9:11 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 49+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-04-07 9:11 UTC (permalink / raw)
To: jason-jh.lin, Rob Herring, Matthias Brugger, Chun-Kuang Hu
Cc: devicetree, Maxime Coquelin, David Airlie, linux-kernel,
singo.chang, hsinyi, Alexandre Torgue, postmaster,
Project_Global_Chrome_Upstream_Group, Fabien Parent, moudy.ho,
linux-mediatek, roy-cw.yeh, Daniel Vetter,
John 'Warthog9' Hawley, CK Hu, Philipp Zabel, nancy.lin,
linux-stm32, linux-arm-kernel
Il 07/04/22 05:04, jason-jh.lin ha scritto:
> 1. Add mt8195 mmsys compatible for vdosys0.
> 2. Add mt8195 routing table settings and fix build fail.
> 3. Add clock name, clock driver name and routing table into the driver data
> of mt8195 vdosys0.
> 4. Add get match data by clock name function and clock platform labels
> to identify which mmsys node is corresponding to vdosys0.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 6 +-
> drivers/soc/mediatek/mt8167-mmsys.h | 2 +-
> drivers/soc/mediatek/mt8183-mmsys.h | 2 +-
> drivers/soc/mediatek/mt8186-mmsys.h | 4 +-
> drivers/soc/mediatek/mt8192-mmsys.h | 4 +-
> drivers/soc/mediatek/mt8195-mmsys.h | 370 ++++++++++++++++++++
> drivers/soc/mediatek/mt8365-mmsys.h | 4 +-
> drivers/soc/mediatek/mtk-mmsys.c | 62 ++++
> drivers/soc/mediatek/mtk-mmsys.h | 1 +
> drivers/soc/mediatek/mtk-mutex.c | 8 +-
> include/linux/soc/mediatek/mtk-mmsys.h | 13 +-
> 12 files changed, 461 insertions(+), 17 deletions(-)
> create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
>
..snip..
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index 4fc4c2c9ea20..b2fa239c5f5f 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -4,6 +4,8 @@
> * Author: James Liao <jamesjj.liao@mediatek.com>
> */
>
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> #include <linux/delay.h>
> #include <linux/device.h>
> #include <linux/io.h>
> @@ -17,6 +19,7 @@
> #include "mt8183-mmsys.h"
> #include "mt8186-mmsys.h"
> #include "mt8192-mmsys.h"
> +#include "mt8195-mmsys.h"
> #include "mt8365-mmsys.h"
>
> static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
> @@ -72,12 +75,24 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
> .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
> };
>
> +static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
> + .clk_name = "cfg_vdo0",
> + .clk_driver = "clk-mt8195-vdo0",
> + .routes = mmsys_mt8195_routing_table,
> + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> +};
> +
> static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
> .clk_driver = "clk-mt8365-mm",
> .routes = mt8365_mmsys_routing_table,
> .num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
> };
>
> +static const struct of_device_id mtk_clk_platform_labels[] = {
> + { .compatible = "mediatek,mt8195-mmsys",
> + .data = (void *)"clk-mt8195"},
I have a hunch that MT8195 won't be the first and last SoC having multiple
mmsys channels. I would tend to think that there will be more....
....so, to make it clean from the beginning, I think that you should, at
this point, assign a struct to that .data pointer, instead of declaring a
drvdata struct into mtk_mmsys_get_match_data_by_clk_name().
Besides, I think that this kind of usage for __clk_get_name() may be an API
abuse... but I'm not sure about that... in any case:
- if it's not an abuse, then you should simply pass mt8195_vdosys0_driver_data,
or an array of pointers to mtk_mmsys_driver_data;
- if this is an abuse, you can do the same checks by looking at the iostart
(mmio base address) of the vdosys{0,1} node(s).
Honestly, though, I'm not even sure that you need this different of_device_id
array here... since you could simply wrap the mtk_mmsys_driver_data in the
of_match_mtk_mmsys that you have below... here's another idea:
struct mtk_mmsys_match_data {
const struct mtk_mmsys_driver_data *drv_data[];
unsigned short num_drv_data;
};
...so that:
static int some_function_handling_multi_mmsys(struct mtk_mmsys *mmsys,
struct mtk_mmsys_match_data *match)
{
int i;
i = [ logic to find the right match->drv_data entry here ]
return i;
}
static int mtk_mmsys_probe()
{
.... variables, something else ....
if (match_data->num_drv_data > 1) {
/* This SoC has multiple mmsys channels */
ret = some_function_handling_multi_mmsys(mmsys);
if (ret < 0)
return ret;
mmsys->data = match_data->drv_data[ret];
} else {
dev_dbg(dev, "Using single mmsys channel\n");
mmsys->data = match_data->drv_data[0];
}
...everything else that mtk_mmsys_probe does ...
}
What I'm trying to communicate with this is that the currently chosen solution
looks a bit fragile and needs to be made robust.
In comparison, even if it's not technically right to have two different compatibles
for the same hardware (and shall not be done), the former solution, even if wrong,
was more robust than this one, imo.
Regards,
Angelo
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [RESEND v17 3/7] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
@ 2022-04-07 9:11 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 49+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-04-07 9:11 UTC (permalink / raw)
To: jason-jh.lin, Rob Herring, Matthias Brugger, Chun-Kuang Hu
Cc: Philipp Zabel, Maxime Coquelin, David Airlie, Daniel Vetter,
Alexandre Torgue, John 'Warthog9' Hawley, postmaster,
hsinyi, fshao, moudy.ho, roy-cw.yeh, CK Hu, Fabien Parent,
nancy.lin, singo.chang, devicetree, linux-stm32,
linux-arm-kernel, linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group
Il 07/04/22 05:04, jason-jh.lin ha scritto:
> 1. Add mt8195 mmsys compatible for vdosys0.
> 2. Add mt8195 routing table settings and fix build fail.
> 3. Add clock name, clock driver name and routing table into the driver data
> of mt8195 vdosys0.
> 4. Add get match data by clock name function and clock platform labels
> to identify which mmsys node is corresponding to vdosys0.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 6 +-
> drivers/soc/mediatek/mt8167-mmsys.h | 2 +-
> drivers/soc/mediatek/mt8183-mmsys.h | 2 +-
> drivers/soc/mediatek/mt8186-mmsys.h | 4 +-
> drivers/soc/mediatek/mt8192-mmsys.h | 4 +-
> drivers/soc/mediatek/mt8195-mmsys.h | 370 ++++++++++++++++++++
> drivers/soc/mediatek/mt8365-mmsys.h | 4 +-
> drivers/soc/mediatek/mtk-mmsys.c | 62 ++++
> drivers/soc/mediatek/mtk-mmsys.h | 1 +
> drivers/soc/mediatek/mtk-mutex.c | 8 +-
> include/linux/soc/mediatek/mtk-mmsys.h | 13 +-
> 12 files changed, 461 insertions(+), 17 deletions(-)
> create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
>
..snip..
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index 4fc4c2c9ea20..b2fa239c5f5f 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -4,6 +4,8 @@
> * Author: James Liao <jamesjj.liao@mediatek.com>
> */
>
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> #include <linux/delay.h>
> #include <linux/device.h>
> #include <linux/io.h>
> @@ -17,6 +19,7 @@
> #include "mt8183-mmsys.h"
> #include "mt8186-mmsys.h"
> #include "mt8192-mmsys.h"
> +#include "mt8195-mmsys.h"
> #include "mt8365-mmsys.h"
>
> static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
> @@ -72,12 +75,24 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
> .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
> };
>
> +static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
> + .clk_name = "cfg_vdo0",
> + .clk_driver = "clk-mt8195-vdo0",
> + .routes = mmsys_mt8195_routing_table,
> + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> +};
> +
> static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
> .clk_driver = "clk-mt8365-mm",
> .routes = mt8365_mmsys_routing_table,
> .num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
> };
>
> +static const struct of_device_id mtk_clk_platform_labels[] = {
> + { .compatible = "mediatek,mt8195-mmsys",
> + .data = (void *)"clk-mt8195"},
I have a hunch that MT8195 won't be the first and last SoC having multiple
mmsys channels. I would tend to think that there will be more....
....so, to make it clean from the beginning, I think that you should, at
this point, assign a struct to that .data pointer, instead of declaring a
drvdata struct into mtk_mmsys_get_match_data_by_clk_name().
Besides, I think that this kind of usage for __clk_get_name() may be an API
abuse... but I'm not sure about that... in any case:
- if it's not an abuse, then you should simply pass mt8195_vdosys0_driver_data,
or an array of pointers to mtk_mmsys_driver_data;
- if this is an abuse, you can do the same checks by looking at the iostart
(mmio base address) of the vdosys{0,1} node(s).
Honestly, though, I'm not even sure that you need this different of_device_id
array here... since you could simply wrap the mtk_mmsys_driver_data in the
of_match_mtk_mmsys that you have below... here's another idea:
struct mtk_mmsys_match_data {
const struct mtk_mmsys_driver_data *drv_data[];
unsigned short num_drv_data;
};
...so that:
static int some_function_handling_multi_mmsys(struct mtk_mmsys *mmsys,
struct mtk_mmsys_match_data *match)
{
int i;
i = [ logic to find the right match->drv_data entry here ]
return i;
}
static int mtk_mmsys_probe()
{
.... variables, something else ....
if (match_data->num_drv_data > 1) {
/* This SoC has multiple mmsys channels */
ret = some_function_handling_multi_mmsys(mmsys);
if (ret < 0)
return ret;
mmsys->data = match_data->drv_data[ret];
} else {
dev_dbg(dev, "Using single mmsys channel\n");
mmsys->data = match_data->drv_data[0];
}
...everything else that mtk_mmsys_probe does ...
}
What I'm trying to communicate with this is that the currently chosen solution
looks a bit fragile and needs to be made robust.
In comparison, even if it's not technically right to have two different compatibles
for the same hardware (and shall not be done), the former solution, even if wrong,
was more robust than this one, imo.
Regards,
Angelo
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [RESEND v17 3/7] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
2022-04-07 6:27 ` Jason-JH Lin
(?)
@ 2022-04-08 1:28 ` CK Hu
-1 siblings, 0 replies; 49+ messages in thread
From: CK Hu @ 2022-04-08 1:28 UTC (permalink / raw)
To: Jason-JH Lin, Rob Herring, Matthias Brugger, Chun-Kuang Hu,
AngeloGioacchino Del Regno
Cc: David Airlie, singo.chang, Alexandre Torgue, postmaster,
Fabien Parent, John 'Warthog9' Hawley, linux-stm32,
roy-cw.yeh, Project_Global_Chrome_Upstream_Group, Philipp Zabel,
devicetree, Daniel Vetter, nancy.lin, linux-mediatek, hsinyi,
linux-arm-kernel, linux-kernel, moudy.ho, Maxime Coquelin
Hi, Jason:
On Thu, 2022-04-07 at 14:27 +0800, Jason-JH Lin wrote:
> Hi CK,
>
> Thanks for the reviews.
>
> On Thu, 2022-04-07 at 13:45 +0800, CK Hu wrote:
> > Hi, Jason:
> >
> > On Thu, 2022-04-07 at 11:04 +0800, jason-jh.lin wrote:
> > > 1. Add mt8195 mmsys compatible for vdosys0.
> > > 2. Add mt8195 routing table settings and fix build fail.
> > > 3. Add clock name, clock driver name and routing table into the
> > > driver data
> > > of mt8195 vdosys0.
> > > 4. Add get match data by clock name function and clock platform
> > > labels
> > > to identify which mmsys node is corresponding to vdosys0.
> > >
> > > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > > ---
> > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 6 +-
> > > drivers/soc/mediatek/mt8167-mmsys.h | 2 +-
> > > drivers/soc/mediatek/mt8183-mmsys.h | 2 +-
> > > drivers/soc/mediatek/mt8186-mmsys.h | 4 +-
> > > drivers/soc/mediatek/mt8192-mmsys.h | 4 +-
> > > drivers/soc/mediatek/mt8195-mmsys.h | 370
> > > ++++++++++++++++++++
> > > drivers/soc/mediatek/mt8365-mmsys.h | 4 +-
> > > drivers/soc/mediatek/mtk-mmsys.c | 62 ++++
> > > drivers/soc/mediatek/mtk-mmsys.h | 1 +
> > > drivers/soc/mediatek/mtk-mutex.c | 8 +-
> > > include/linux/soc/mediatek/mtk-mmsys.h | 13 +-
> > > 12 files changed, 461 insertions(+), 17 deletions(-)
> > > create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
> > >
> >
> > [snip]
> >
> > > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > > b/drivers/soc/mediatek/mtk-mmsys.c
> > > index 4fc4c2c9ea20..b2fa239c5f5f 100644
> > > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > > @@ -4,6 +4,8 @@
> > > * Author: James Liao <jamesjj.liao@mediatek.com>
> > > */
> > >
> > > +#include <linux/clk.h>
> > > +#include <linux/clk-provider.h>
> > > #include <linux/delay.h>
> > > #include <linux/device.h>
> > > #include <linux/io.h>
> > > @@ -17,6 +19,7 @@
> > > #include "mt8183-mmsys.h"
> > > #include "mt8186-mmsys.h"
> > > #include "mt8192-mmsys.h"
> > > +#include "mt8195-mmsys.h"
> > > #include "mt8365-mmsys.h"
> > >
> > > static const struct mtk_mmsys_driver_data
> > > mt2701_mmsys_driver_data
> > > =
> > > {
> > > @@ -72,12 +75,24 @@ static const struct mtk_mmsys_driver_data
> > > mt8192_mmsys_driver_data = {
> > > .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
> > > };
> > >
> > > +static const struct mtk_mmsys_driver_data
> > > mt8195_vdosys0_driver_data
> > > = {
> > > + .clk_name = "cfg_vdo0",
> > > + .clk_driver = "clk-mt8195-vdo0",
> > > + .routes = mmsys_mt8195_routing_table,
> > > + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > > +};
> > > +
> > > static const struct mtk_mmsys_driver_data
> > > mt8365_mmsys_driver_data
> > > =
> > > {
> > > .clk_driver = "clk-mt8365-mm",
> > > .routes = mt8365_mmsys_routing_table,
> > > .num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
> > > };
> > >
> > > +static const struct of_device_id mtk_clk_platform_labels[] = {
> > > + { .compatible = "mediatek,mt8195-mmsys",
> > > + .data = (void *)"clk-mt8195"},
> > > +};
> > > +
> > > struct mtk_mmsys {
> > > void __iomem *regs;
> > > const struct mtk_mmsys_driver_data *data;
> > > @@ -85,6 +100,45 @@ struct mtk_mmsys {
> > > struct reset_controller_dev rcdev;
> > > };
> > >
> > > +static int mtk_mmsys_get_match_data_by_clk_name(const struct
> > > mtk_mmsys_driver_data **data,
> > > + struct device *dev)
> > > +{
> > > + int i;
> > > + struct clk *clk;
> > > + const char *clk_name;
> > > + const struct of_device_id *of_id =
> > > of_match_node(mtk_clk_platform_labels,
> > > + dev->of_node);
> > > + const struct mtk_mmsys_driver_data *drvdata[] = {
> > > + &mt8195_vdosys0_driver_data,
> > > + };
> > > +
> > > + if (!of_id || !of_id->data) {
> > > + dev_err(dev, "Can't find match clk platform labels\n");
> > > + return -EINVAL;
> > > + }
> > > +
> > > + clk = devm_clk_get(dev, NULL);
> > > + if (IS_ERR(clk)) {
> > > + dev_err(dev, "failed to get mmsys clk\n");
> > > + return PTR_ERR(clk);
> > > + }
> > > +
> > > + clk_name = __clk_get_name(clk);
> > > + if (!clk_name) {
> > > + dev_err(dev, "invalid mmsys clk name\n");
> > > + return -EINVAL;
> > > + }
> > > +
> > > + for (i = 0; i < ARRAY_SIZE(drvdata); i++)
> > > + if (strncmp(drvdata[i]->clk_name, clk_name,
> > > strlen(clk_name)) == 0 &&
> > > + strncmp(drvdata[i]->clk_driver, of_id->data,
> > > strlen(of_id->data)) == 0) {
> >
> > I think clk_name is enough to identify the mmsys, why do you need
> > clk_driver?
>
> I think there might be another chip that needs to get driver data by
> clk_name .
> So I use "clk-mt8195" in clk_driver to identify the corresponding
> platform whose clk_name of mmsys is also "cfg_vod0".
We usually don't care the future because the future may not happen. If
it's sure that would happen, I think clk_driver is not a good choice.
For now, the clk_driver name is different for each SoC, but it could be
the same for each SoC because only one clock driver would be compiled.
I think "compatible" would be different for each SoC.
Regards,
CK
>
> > > + *data = drvdata[i];
> > > + return 0;
> > > + }
> > > +
> > > + return -EINVAL;
> > > +}
> > > +
> > > void mtk_mmsys_ddp_connect(struct device *dev,
> > > enum mtk_ddp_comp_id cur,
> > > enum mtk_ddp_comp_id next)
> > > @@ -206,6 +260,11 @@ static int mtk_mmsys_probe(struct
> > > platform_device *pdev)
> > > }
> > >
> > > mmsys->data = of_device_get_match_data(&pdev->dev);
> > > + if (!mmsys->data &&
> > > mtk_mmsys_get_match_data_by_clk_name(&mmsys->data, dev) < 0) {
> > > + dev_err(dev, "Couldn't get match driver data\n");
> > > + return -EINVAL;
> > > + }
> > > +
> > > platform_set_drvdata(pdev, mmsys);
> > >
> > > clks = platform_device_register_data(&pdev->dev, mmsys->data-
> > > > clk_driver,
> > >
> > > @@ -260,6 +319,9 @@ static const struct of_device_id
> > > of_match_mtk_mmsys[] = {
> > > .compatible = "mediatek,mt8192-mmsys",
> > > .data = &mt8192_mmsys_driver_data,
> > > },
> > > + {
> > > + .compatible = "mediatek,mt8195-mmsys",
> > > + },
> > > {
> > > .compatible = "mediatek,mt8365-mmsys",
> > > .data = &mt8365_mmsys_driver_data,
> > >
> >
> > [snip]
> >
> > > b/include/linux/soc/mediatek/mtk-mmsys.h
> > > index 4bba275e235a..fb719fd1281c 100644
> > > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > > @@ -16,14 +16,25 @@ enum mtk_ddp_comp_id {
> > > DDP_COMPONENT_CCORR,
> > > DDP_COMPONENT_COLOR0,
> > > DDP_COMPONENT_COLOR1,
> > > - DDP_COMPONENT_DITHER,
> > > + DDP_COMPONENT_DITHER0,
> >
> > I would like soc and drm modification to go through different tree,
> > so
> > this setting would not modify drm driver in this patch.
> >
> > DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
> >
> > Then modify drm driver after this patch.
> >
> > Regards,
> > CK
>
> OK, I will use this modification at the next version.
> Thanks!
>
> Regards,
> Jason-JH.Lin
>
> >
> > > + DDP_COMPONENT_DITHER1,
> > > + DDP_COMPONENT_DP_INTF0,
> > > + DDP_COMPONENT_DP_INTF1,
> > > DDP_COMPONENT_DPI0,
> > > DDP_COMPONENT_DPI1,
> > > + DDP_COMPONENT_DSC0,
> > > + DDP_COMPONENT_DSC1,
> > > DDP_COMPONENT_DSI0,
> > > DDP_COMPONENT_DSI1,
> > > DDP_COMPONENT_DSI2,
> > > DDP_COMPONENT_DSI3,
> > > DDP_COMPONENT_GAMMA,
> > > + DDP_COMPONENT_MERGE0,
> > > + DDP_COMPONENT_MERGE1,
> > > + DDP_COMPONENT_MERGE2,
> > > + DDP_COMPONENT_MERGE3,
> > > + DDP_COMPONENT_MERGE4,
> > > + DDP_COMPONENT_MERGE5,
> > > DDP_COMPONENT_OD0,
> > > DDP_COMPONENT_OD1,
> > > DDP_COMPONENT_OVL0,
> >
> >
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [RESEND v17 3/7] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
@ 2022-04-08 1:28 ` CK Hu
0 siblings, 0 replies; 49+ messages in thread
From: CK Hu @ 2022-04-08 1:28 UTC (permalink / raw)
To: Jason-JH Lin, Rob Herring, Matthias Brugger, Chun-Kuang Hu,
AngeloGioacchino Del Regno
Cc: David Airlie, singo.chang, Alexandre Torgue, postmaster,
Fabien Parent, John 'Warthog9' Hawley, linux-stm32,
roy-cw.yeh, Project_Global_Chrome_Upstream_Group, Philipp Zabel,
devicetree, Daniel Vetter, nancy.lin, linux-mediatek, hsinyi,
linux-arm-kernel, linux-kernel, moudy.ho, Maxime Coquelin
Hi, Jason:
On Thu, 2022-04-07 at 14:27 +0800, Jason-JH Lin wrote:
> Hi CK,
>
> Thanks for the reviews.
>
> On Thu, 2022-04-07 at 13:45 +0800, CK Hu wrote:
> > Hi, Jason:
> >
> > On Thu, 2022-04-07 at 11:04 +0800, jason-jh.lin wrote:
> > > 1. Add mt8195 mmsys compatible for vdosys0.
> > > 2. Add mt8195 routing table settings and fix build fail.
> > > 3. Add clock name, clock driver name and routing table into the
> > > driver data
> > > of mt8195 vdosys0.
> > > 4. Add get match data by clock name function and clock platform
> > > labels
> > > to identify which mmsys node is corresponding to vdosys0.
> > >
> > > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > > ---
> > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 6 +-
> > > drivers/soc/mediatek/mt8167-mmsys.h | 2 +-
> > > drivers/soc/mediatek/mt8183-mmsys.h | 2 +-
> > > drivers/soc/mediatek/mt8186-mmsys.h | 4 +-
> > > drivers/soc/mediatek/mt8192-mmsys.h | 4 +-
> > > drivers/soc/mediatek/mt8195-mmsys.h | 370
> > > ++++++++++++++++++++
> > > drivers/soc/mediatek/mt8365-mmsys.h | 4 +-
> > > drivers/soc/mediatek/mtk-mmsys.c | 62 ++++
> > > drivers/soc/mediatek/mtk-mmsys.h | 1 +
> > > drivers/soc/mediatek/mtk-mutex.c | 8 +-
> > > include/linux/soc/mediatek/mtk-mmsys.h | 13 +-
> > > 12 files changed, 461 insertions(+), 17 deletions(-)
> > > create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
> > >
> >
> > [snip]
> >
> > > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > > b/drivers/soc/mediatek/mtk-mmsys.c
> > > index 4fc4c2c9ea20..b2fa239c5f5f 100644
> > > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > > @@ -4,6 +4,8 @@
> > > * Author: James Liao <jamesjj.liao@mediatek.com>
> > > */
> > >
> > > +#include <linux/clk.h>
> > > +#include <linux/clk-provider.h>
> > > #include <linux/delay.h>
> > > #include <linux/device.h>
> > > #include <linux/io.h>
> > > @@ -17,6 +19,7 @@
> > > #include "mt8183-mmsys.h"
> > > #include "mt8186-mmsys.h"
> > > #include "mt8192-mmsys.h"
> > > +#include "mt8195-mmsys.h"
> > > #include "mt8365-mmsys.h"
> > >
> > > static const struct mtk_mmsys_driver_data
> > > mt2701_mmsys_driver_data
> > > =
> > > {
> > > @@ -72,12 +75,24 @@ static const struct mtk_mmsys_driver_data
> > > mt8192_mmsys_driver_data = {
> > > .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
> > > };
> > >
> > > +static const struct mtk_mmsys_driver_data
> > > mt8195_vdosys0_driver_data
> > > = {
> > > + .clk_name = "cfg_vdo0",
> > > + .clk_driver = "clk-mt8195-vdo0",
> > > + .routes = mmsys_mt8195_routing_table,
> > > + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > > +};
> > > +
> > > static const struct mtk_mmsys_driver_data
> > > mt8365_mmsys_driver_data
> > > =
> > > {
> > > .clk_driver = "clk-mt8365-mm",
> > > .routes = mt8365_mmsys_routing_table,
> > > .num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
> > > };
> > >
> > > +static const struct of_device_id mtk_clk_platform_labels[] = {
> > > + { .compatible = "mediatek,mt8195-mmsys",
> > > + .data = (void *)"clk-mt8195"},
> > > +};
> > > +
> > > struct mtk_mmsys {
> > > void __iomem *regs;
> > > const struct mtk_mmsys_driver_data *data;
> > > @@ -85,6 +100,45 @@ struct mtk_mmsys {
> > > struct reset_controller_dev rcdev;
> > > };
> > >
> > > +static int mtk_mmsys_get_match_data_by_clk_name(const struct
> > > mtk_mmsys_driver_data **data,
> > > + struct device *dev)
> > > +{
> > > + int i;
> > > + struct clk *clk;
> > > + const char *clk_name;
> > > + const struct of_device_id *of_id =
> > > of_match_node(mtk_clk_platform_labels,
> > > + dev->of_node);
> > > + const struct mtk_mmsys_driver_data *drvdata[] = {
> > > + &mt8195_vdosys0_driver_data,
> > > + };
> > > +
> > > + if (!of_id || !of_id->data) {
> > > + dev_err(dev, "Can't find match clk platform labels\n");
> > > + return -EINVAL;
> > > + }
> > > +
> > > + clk = devm_clk_get(dev, NULL);
> > > + if (IS_ERR(clk)) {
> > > + dev_err(dev, "failed to get mmsys clk\n");
> > > + return PTR_ERR(clk);
> > > + }
> > > +
> > > + clk_name = __clk_get_name(clk);
> > > + if (!clk_name) {
> > > + dev_err(dev, "invalid mmsys clk name\n");
> > > + return -EINVAL;
> > > + }
> > > +
> > > + for (i = 0; i < ARRAY_SIZE(drvdata); i++)
> > > + if (strncmp(drvdata[i]->clk_name, clk_name,
> > > strlen(clk_name)) == 0 &&
> > > + strncmp(drvdata[i]->clk_driver, of_id->data,
> > > strlen(of_id->data)) == 0) {
> >
> > I think clk_name is enough to identify the mmsys, why do you need
> > clk_driver?
>
> I think there might be another chip that needs to get driver data by
> clk_name .
> So I use "clk-mt8195" in clk_driver to identify the corresponding
> platform whose clk_name of mmsys is also "cfg_vod0".
We usually don't care the future because the future may not happen. If
it's sure that would happen, I think clk_driver is not a good choice.
For now, the clk_driver name is different for each SoC, but it could be
the same for each SoC because only one clock driver would be compiled.
I think "compatible" would be different for each SoC.
Regards,
CK
>
> > > + *data = drvdata[i];
> > > + return 0;
> > > + }
> > > +
> > > + return -EINVAL;
> > > +}
> > > +
> > > void mtk_mmsys_ddp_connect(struct device *dev,
> > > enum mtk_ddp_comp_id cur,
> > > enum mtk_ddp_comp_id next)
> > > @@ -206,6 +260,11 @@ static int mtk_mmsys_probe(struct
> > > platform_device *pdev)
> > > }
> > >
> > > mmsys->data = of_device_get_match_data(&pdev->dev);
> > > + if (!mmsys->data &&
> > > mtk_mmsys_get_match_data_by_clk_name(&mmsys->data, dev) < 0) {
> > > + dev_err(dev, "Couldn't get match driver data\n");
> > > + return -EINVAL;
> > > + }
> > > +
> > > platform_set_drvdata(pdev, mmsys);
> > >
> > > clks = platform_device_register_data(&pdev->dev, mmsys->data-
> > > > clk_driver,
> > >
> > > @@ -260,6 +319,9 @@ static const struct of_device_id
> > > of_match_mtk_mmsys[] = {
> > > .compatible = "mediatek,mt8192-mmsys",
> > > .data = &mt8192_mmsys_driver_data,
> > > },
> > > + {
> > > + .compatible = "mediatek,mt8195-mmsys",
> > > + },
> > > {
> > > .compatible = "mediatek,mt8365-mmsys",
> > > .data = &mt8365_mmsys_driver_data,
> > >
> >
> > [snip]
> >
> > > b/include/linux/soc/mediatek/mtk-mmsys.h
> > > index 4bba275e235a..fb719fd1281c 100644
> > > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > > @@ -16,14 +16,25 @@ enum mtk_ddp_comp_id {
> > > DDP_COMPONENT_CCORR,
> > > DDP_COMPONENT_COLOR0,
> > > DDP_COMPONENT_COLOR1,
> > > - DDP_COMPONENT_DITHER,
> > > + DDP_COMPONENT_DITHER0,
> >
> > I would like soc and drm modification to go through different tree,
> > so
> > this setting would not modify drm driver in this patch.
> >
> > DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
> >
> > Then modify drm driver after this patch.
> >
> > Regards,
> > CK
>
> OK, I will use this modification at the next version.
> Thanks!
>
> Regards,
> Jason-JH.Lin
>
> >
> > > + DDP_COMPONENT_DITHER1,
> > > + DDP_COMPONENT_DP_INTF0,
> > > + DDP_COMPONENT_DP_INTF1,
> > > DDP_COMPONENT_DPI0,
> > > DDP_COMPONENT_DPI1,
> > > + DDP_COMPONENT_DSC0,
> > > + DDP_COMPONENT_DSC1,
> > > DDP_COMPONENT_DSI0,
> > > DDP_COMPONENT_DSI1,
> > > DDP_COMPONENT_DSI2,
> > > DDP_COMPONENT_DSI3,
> > > DDP_COMPONENT_GAMMA,
> > > + DDP_COMPONENT_MERGE0,
> > > + DDP_COMPONENT_MERGE1,
> > > + DDP_COMPONENT_MERGE2,
> > > + DDP_COMPONENT_MERGE3,
> > > + DDP_COMPONENT_MERGE4,
> > > + DDP_COMPONENT_MERGE5,
> > > DDP_COMPONENT_OD0,
> > > DDP_COMPONENT_OD1,
> > > DDP_COMPONENT_OVL0,
> >
> >
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [RESEND v17 3/7] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
@ 2022-04-08 1:28 ` CK Hu
0 siblings, 0 replies; 49+ messages in thread
From: CK Hu @ 2022-04-08 1:28 UTC (permalink / raw)
To: Jason-JH Lin, Rob Herring, Matthias Brugger, Chun-Kuang Hu,
AngeloGioacchino Del Regno
Cc: David Airlie, singo.chang, Alexandre Torgue, postmaster,
Fabien Parent, John 'Warthog9' Hawley, linux-stm32,
roy-cw.yeh, Project_Global_Chrome_Upstream_Group, Philipp Zabel,
devicetree, Daniel Vetter, nancy.lin, linux-mediatek, hsinyi,
linux-arm-kernel, linux-kernel, moudy.ho, Maxime Coquelin
Hi, Jason:
On Thu, 2022-04-07 at 14:27 +0800, Jason-JH Lin wrote:
> Hi CK,
>
> Thanks for the reviews.
>
> On Thu, 2022-04-07 at 13:45 +0800, CK Hu wrote:
> > Hi, Jason:
> >
> > On Thu, 2022-04-07 at 11:04 +0800, jason-jh.lin wrote:
> > > 1. Add mt8195 mmsys compatible for vdosys0.
> > > 2. Add mt8195 routing table settings and fix build fail.
> > > 3. Add clock name, clock driver name and routing table into the
> > > driver data
> > > of mt8195 vdosys0.
> > > 4. Add get match data by clock name function and clock platform
> > > labels
> > > to identify which mmsys node is corresponding to vdosys0.
> > >
> > > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > > ---
> > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 6 +-
> > > drivers/soc/mediatek/mt8167-mmsys.h | 2 +-
> > > drivers/soc/mediatek/mt8183-mmsys.h | 2 +-
> > > drivers/soc/mediatek/mt8186-mmsys.h | 4 +-
> > > drivers/soc/mediatek/mt8192-mmsys.h | 4 +-
> > > drivers/soc/mediatek/mt8195-mmsys.h | 370
> > > ++++++++++++++++++++
> > > drivers/soc/mediatek/mt8365-mmsys.h | 4 +-
> > > drivers/soc/mediatek/mtk-mmsys.c | 62 ++++
> > > drivers/soc/mediatek/mtk-mmsys.h | 1 +
> > > drivers/soc/mediatek/mtk-mutex.c | 8 +-
> > > include/linux/soc/mediatek/mtk-mmsys.h | 13 +-
> > > 12 files changed, 461 insertions(+), 17 deletions(-)
> > > create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
> > >
> >
> > [snip]
> >
> > > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > > b/drivers/soc/mediatek/mtk-mmsys.c
> > > index 4fc4c2c9ea20..b2fa239c5f5f 100644
> > > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > > @@ -4,6 +4,8 @@
> > > * Author: James Liao <jamesjj.liao@mediatek.com>
> > > */
> > >
> > > +#include <linux/clk.h>
> > > +#include <linux/clk-provider.h>
> > > #include <linux/delay.h>
> > > #include <linux/device.h>
> > > #include <linux/io.h>
> > > @@ -17,6 +19,7 @@
> > > #include "mt8183-mmsys.h"
> > > #include "mt8186-mmsys.h"
> > > #include "mt8192-mmsys.h"
> > > +#include "mt8195-mmsys.h"
> > > #include "mt8365-mmsys.h"
> > >
> > > static const struct mtk_mmsys_driver_data
> > > mt2701_mmsys_driver_data
> > > =
> > > {
> > > @@ -72,12 +75,24 @@ static const struct mtk_mmsys_driver_data
> > > mt8192_mmsys_driver_data = {
> > > .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
> > > };
> > >
> > > +static const struct mtk_mmsys_driver_data
> > > mt8195_vdosys0_driver_data
> > > = {
> > > + .clk_name = "cfg_vdo0",
> > > + .clk_driver = "clk-mt8195-vdo0",
> > > + .routes = mmsys_mt8195_routing_table,
> > > + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > > +};
> > > +
> > > static const struct mtk_mmsys_driver_data
> > > mt8365_mmsys_driver_data
> > > =
> > > {
> > > .clk_driver = "clk-mt8365-mm",
> > > .routes = mt8365_mmsys_routing_table,
> > > .num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
> > > };
> > >
> > > +static const struct of_device_id mtk_clk_platform_labels[] = {
> > > + { .compatible = "mediatek,mt8195-mmsys",
> > > + .data = (void *)"clk-mt8195"},
> > > +};
> > > +
> > > struct mtk_mmsys {
> > > void __iomem *regs;
> > > const struct mtk_mmsys_driver_data *data;
> > > @@ -85,6 +100,45 @@ struct mtk_mmsys {
> > > struct reset_controller_dev rcdev;
> > > };
> > >
> > > +static int mtk_mmsys_get_match_data_by_clk_name(const struct
> > > mtk_mmsys_driver_data **data,
> > > + struct device *dev)
> > > +{
> > > + int i;
> > > + struct clk *clk;
> > > + const char *clk_name;
> > > + const struct of_device_id *of_id =
> > > of_match_node(mtk_clk_platform_labels,
> > > + dev->of_node);
> > > + const struct mtk_mmsys_driver_data *drvdata[] = {
> > > + &mt8195_vdosys0_driver_data,
> > > + };
> > > +
> > > + if (!of_id || !of_id->data) {
> > > + dev_err(dev, "Can't find match clk platform labels\n");
> > > + return -EINVAL;
> > > + }
> > > +
> > > + clk = devm_clk_get(dev, NULL);
> > > + if (IS_ERR(clk)) {
> > > + dev_err(dev, "failed to get mmsys clk\n");
> > > + return PTR_ERR(clk);
> > > + }
> > > +
> > > + clk_name = __clk_get_name(clk);
> > > + if (!clk_name) {
> > > + dev_err(dev, "invalid mmsys clk name\n");
> > > + return -EINVAL;
> > > + }
> > > +
> > > + for (i = 0; i < ARRAY_SIZE(drvdata); i++)
> > > + if (strncmp(drvdata[i]->clk_name, clk_name,
> > > strlen(clk_name)) == 0 &&
> > > + strncmp(drvdata[i]->clk_driver, of_id->data,
> > > strlen(of_id->data)) == 0) {
> >
> > I think clk_name is enough to identify the mmsys, why do you need
> > clk_driver?
>
> I think there might be another chip that needs to get driver data by
> clk_name .
> So I use "clk-mt8195" in clk_driver to identify the corresponding
> platform whose clk_name of mmsys is also "cfg_vod0".
We usually don't care the future because the future may not happen. If
it's sure that would happen, I think clk_driver is not a good choice.
For now, the clk_driver name is different for each SoC, but it could be
the same for each SoC because only one clock driver would be compiled.
I think "compatible" would be different for each SoC.
Regards,
CK
>
> > > + *data = drvdata[i];
> > > + return 0;
> > > + }
> > > +
> > > + return -EINVAL;
> > > +}
> > > +
> > > void mtk_mmsys_ddp_connect(struct device *dev,
> > > enum mtk_ddp_comp_id cur,
> > > enum mtk_ddp_comp_id next)
> > > @@ -206,6 +260,11 @@ static int mtk_mmsys_probe(struct
> > > platform_device *pdev)
> > > }
> > >
> > > mmsys->data = of_device_get_match_data(&pdev->dev);
> > > + if (!mmsys->data &&
> > > mtk_mmsys_get_match_data_by_clk_name(&mmsys->data, dev) < 0) {
> > > + dev_err(dev, "Couldn't get match driver data\n");
> > > + return -EINVAL;
> > > + }
> > > +
> > > platform_set_drvdata(pdev, mmsys);
> > >
> > > clks = platform_device_register_data(&pdev->dev, mmsys->data-
> > > > clk_driver,
> > >
> > > @@ -260,6 +319,9 @@ static const struct of_device_id
> > > of_match_mtk_mmsys[] = {
> > > .compatible = "mediatek,mt8192-mmsys",
> > > .data = &mt8192_mmsys_driver_data,
> > > },
> > > + {
> > > + .compatible = "mediatek,mt8195-mmsys",
> > > + },
> > > {
> > > .compatible = "mediatek,mt8365-mmsys",
> > > .data = &mt8365_mmsys_driver_data,
> > >
> >
> > [snip]
> >
> > > b/include/linux/soc/mediatek/mtk-mmsys.h
> > > index 4bba275e235a..fb719fd1281c 100644
> > > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > > @@ -16,14 +16,25 @@ enum mtk_ddp_comp_id {
> > > DDP_COMPONENT_CCORR,
> > > DDP_COMPONENT_COLOR0,
> > > DDP_COMPONENT_COLOR1,
> > > - DDP_COMPONENT_DITHER,
> > > + DDP_COMPONENT_DITHER0,
> >
> > I would like soc and drm modification to go through different tree,
> > so
> > this setting would not modify drm driver in this patch.
> >
> > DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
> >
> > Then modify drm driver after this patch.
> >
> > Regards,
> > CK
>
> OK, I will use this modification at the next version.
> Thanks!
>
> Regards,
> Jason-JH.Lin
>
> >
> > > + DDP_COMPONENT_DITHER1,
> > > + DDP_COMPONENT_DP_INTF0,
> > > + DDP_COMPONENT_DP_INTF1,
> > > DDP_COMPONENT_DPI0,
> > > DDP_COMPONENT_DPI1,
> > > + DDP_COMPONENT_DSC0,
> > > + DDP_COMPONENT_DSC1,
> > > DDP_COMPONENT_DSI0,
> > > DDP_COMPONENT_DSI1,
> > > DDP_COMPONENT_DSI2,
> > > DDP_COMPONENT_DSI3,
> > > DDP_COMPONENT_GAMMA,
> > > + DDP_COMPONENT_MERGE0,
> > > + DDP_COMPONENT_MERGE1,
> > > + DDP_COMPONENT_MERGE2,
> > > + DDP_COMPONENT_MERGE3,
> > > + DDP_COMPONENT_MERGE4,
> > > + DDP_COMPONENT_MERGE5,
> > > DDP_COMPONENT_OD0,
> > > DDP_COMPONENT_OD1,
> > > DDP_COMPONENT_OVL0,
> >
> >
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^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [RESEND v17 3/7] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
2022-04-07 5:58 ` CK Hu
(?)
@ 2022-04-08 1:42 ` Jason-JH Lin
-1 siblings, 0 replies; 49+ messages in thread
From: Jason-JH Lin @ 2022-04-08 1:42 UTC (permalink / raw)
To: CK Hu, Rob Herring, Matthias Brugger, Chun-Kuang Hu,
AngeloGioacchino Del Regno
Cc: David Airlie, singo.chang, Alexandre Torgue, postmaster,
Fabien Parent, John 'Warthog9' Hawley, linux-stm32,
roy-cw.yeh, Project_Global_Chrome_Upstream_Group, Philipp Zabel,
devicetree, Daniel Vetter, nancy.lin, linux-mediatek, hsinyi,
linux-arm-kernel, linux-kernel, moudy.ho, Maxime Coquelin
Hi CK,
Thanks for the reviews.
On Thu, 2022-04-07 at 13:58 +0800, CK Hu wrote:
> Hi, Jason:
>
> On Thu, 2022-04-07 at 11:04 +0800, jason-jh.lin wrote:
> > 1. Add mt8195 mmsys compatible for vdosys0.
> > 2. Add mt8195 routing table settings and fix build fail.
> > 3. Add clock name, clock driver name and routing table into the
> > driver data
> > of mt8195 vdosys0.
> > 4. Add get match data by clock name function and clock platform
> > labels
> > to identify which mmsys node is corresponding to vdosys0.
> >
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> >
>
> [snip]
>
> >
> > +static const struct mtk_mmsys_driver_data
> > mt8195_vdosys0_driver_data
> > = {
> > + .clk_name = "cfg_vdo0",
> > + .clk_driver = "clk-mt8195-vdo0",
> > + .routes = mmsys_mt8195_routing_table,
> > + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > +};
> > +
> >
>
> [snip]
>
> >
> > +static int mtk_mmsys_get_match_data_by_clk_name(const struct
> > mtk_mmsys_driver_data **data,
> > + struct device *dev)
> > +{
> > + int i;
> > + struct clk *clk;
> > + const char *clk_name;
> > + const struct of_device_id *of_id =
> > of_match_node(mtk_clk_platform_labels,
> > + dev->of_node);
> > + const struct mtk_mmsys_driver_data *drvdata[] = {
> > + &mt8195_vdosys0_driver_data,
> > + };
> > +
> > + if (!of_id || !of_id->data) {
> > + dev_err(dev, "Can't find match clk platform labels\n");
> > + return -EINVAL;
> > + }
> > +
> > + clk = devm_clk_get(dev, NULL);
> > + if (IS_ERR(clk)) {
> > + dev_err(dev, "failed to get mmsys clk\n");
> > + return PTR_ERR(clk);
> > + }
> > +
> > + clk_name = __clk_get_name(clk);
> > + if (!clk_name) {
> > + dev_err(dev, "invalid mmsys clk name\n");
> > + return -EINVAL;
> > + }
> > +
> > + for (i = 0; i < ARRAY_SIZE(drvdata); i++)
> > + if (strncmp(drvdata[i]->clk_name, clk_name,
> > strlen(clk_name)) == 0 &&
>
> Why not
>
> strcmp(drvdata[i]->clk_name, clk_name) == 0
>
> Regards,
> CK
>
I would like to block strings without '\0', but it doesn't seem
necessary. So I will change to strcmp at the next version.
Regards,
Jason-JH.Lin
> > + strncmp(drvdata[i]->clk_driver, of_id->data,
> > strlen(of_id->data)) == 0) {
> > + *data = drvdata[i];
> > + return 0;
> > + }
> > +
> > + return -EINVAL;
> > +}
> > +
> >
>
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
>
https://urldefense.com/v3/__http://lists.infradead.org/mailman/listinfo/linux-mediatek__;!!CTRNKA9wMg0ARbw!0MJsfiFOYUann5GooGDcIv4Lgm1FaCXDl8dDFCwiONgD0zJn0PQwJuV05-tZNZwVBxVS$
>
--
Jason-JH Lin <jason-jh.lin@mediatek.com>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [RESEND v17 3/7] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
@ 2022-04-08 1:42 ` Jason-JH Lin
0 siblings, 0 replies; 49+ messages in thread
From: Jason-JH Lin @ 2022-04-08 1:42 UTC (permalink / raw)
To: CK Hu, Rob Herring, Matthias Brugger, Chun-Kuang Hu,
AngeloGioacchino Del Regno
Cc: David Airlie, singo.chang, Alexandre Torgue, postmaster,
Fabien Parent, John 'Warthog9' Hawley, linux-stm32,
roy-cw.yeh, Project_Global_Chrome_Upstream_Group, Philipp Zabel,
devicetree, Daniel Vetter, nancy.lin, linux-mediatek, hsinyi,
linux-arm-kernel, linux-kernel, moudy.ho, Maxime Coquelin
Hi CK,
Thanks for the reviews.
On Thu, 2022-04-07 at 13:58 +0800, CK Hu wrote:
> Hi, Jason:
>
> On Thu, 2022-04-07 at 11:04 +0800, jason-jh.lin wrote:
> > 1. Add mt8195 mmsys compatible for vdosys0.
> > 2. Add mt8195 routing table settings and fix build fail.
> > 3. Add clock name, clock driver name and routing table into the
> > driver data
> > of mt8195 vdosys0.
> > 4. Add get match data by clock name function and clock platform
> > labels
> > to identify which mmsys node is corresponding to vdosys0.
> >
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> >
>
> [snip]
>
> >
> > +static const struct mtk_mmsys_driver_data
> > mt8195_vdosys0_driver_data
> > = {
> > + .clk_name = "cfg_vdo0",
> > + .clk_driver = "clk-mt8195-vdo0",
> > + .routes = mmsys_mt8195_routing_table,
> > + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > +};
> > +
> >
>
> [snip]
>
> >
> > +static int mtk_mmsys_get_match_data_by_clk_name(const struct
> > mtk_mmsys_driver_data **data,
> > + struct device *dev)
> > +{
> > + int i;
> > + struct clk *clk;
> > + const char *clk_name;
> > + const struct of_device_id *of_id =
> > of_match_node(mtk_clk_platform_labels,
> > + dev->of_node);
> > + const struct mtk_mmsys_driver_data *drvdata[] = {
> > + &mt8195_vdosys0_driver_data,
> > + };
> > +
> > + if (!of_id || !of_id->data) {
> > + dev_err(dev, "Can't find match clk platform labels\n");
> > + return -EINVAL;
> > + }
> > +
> > + clk = devm_clk_get(dev, NULL);
> > + if (IS_ERR(clk)) {
> > + dev_err(dev, "failed to get mmsys clk\n");
> > + return PTR_ERR(clk);
> > + }
> > +
> > + clk_name = __clk_get_name(clk);
> > + if (!clk_name) {
> > + dev_err(dev, "invalid mmsys clk name\n");
> > + return -EINVAL;
> > + }
> > +
> > + for (i = 0; i < ARRAY_SIZE(drvdata); i++)
> > + if (strncmp(drvdata[i]->clk_name, clk_name,
> > strlen(clk_name)) == 0 &&
>
> Why not
>
> strcmp(drvdata[i]->clk_name, clk_name) == 0
>
> Regards,
> CK
>
I would like to block strings without '\0', but it doesn't seem
necessary. So I will change to strcmp at the next version.
Regards,
Jason-JH.Lin
> > + strncmp(drvdata[i]->clk_driver, of_id->data,
> > strlen(of_id->data)) == 0) {
> > + *data = drvdata[i];
> > + return 0;
> > + }
> > +
> > + return -EINVAL;
> > +}
> > +
> >
>
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
>
https://urldefense.com/v3/__http://lists.infradead.org/mailman/listinfo/linux-mediatek__;!!CTRNKA9wMg0ARbw!0MJsfiFOYUann5GooGDcIv4Lgm1FaCXDl8dDFCwiONgD0zJn0PQwJuV05-tZNZwVBxVS$
>
--
Jason-JH Lin <jason-jh.lin@mediatek.com>
_______________________________________________
Linux-mediatek mailing list
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http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [RESEND v17 3/7] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
@ 2022-04-08 1:42 ` Jason-JH Lin
0 siblings, 0 replies; 49+ messages in thread
From: Jason-JH Lin @ 2022-04-08 1:42 UTC (permalink / raw)
To: CK Hu, Rob Herring, Matthias Brugger, Chun-Kuang Hu,
AngeloGioacchino Del Regno
Cc: David Airlie, singo.chang, Alexandre Torgue, postmaster,
Fabien Parent, John 'Warthog9' Hawley, linux-stm32,
roy-cw.yeh, Project_Global_Chrome_Upstream_Group, Philipp Zabel,
devicetree, Daniel Vetter, nancy.lin, linux-mediatek, hsinyi,
linux-arm-kernel, linux-kernel, moudy.ho, Maxime Coquelin
Hi CK,
Thanks for the reviews.
On Thu, 2022-04-07 at 13:58 +0800, CK Hu wrote:
> Hi, Jason:
>
> On Thu, 2022-04-07 at 11:04 +0800, jason-jh.lin wrote:
> > 1. Add mt8195 mmsys compatible for vdosys0.
> > 2. Add mt8195 routing table settings and fix build fail.
> > 3. Add clock name, clock driver name and routing table into the
> > driver data
> > of mt8195 vdosys0.
> > 4. Add get match data by clock name function and clock platform
> > labels
> > to identify which mmsys node is corresponding to vdosys0.
> >
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> >
>
> [snip]
>
> >
> > +static const struct mtk_mmsys_driver_data
> > mt8195_vdosys0_driver_data
> > = {
> > + .clk_name = "cfg_vdo0",
> > + .clk_driver = "clk-mt8195-vdo0",
> > + .routes = mmsys_mt8195_routing_table,
> > + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > +};
> > +
> >
>
> [snip]
>
> >
> > +static int mtk_mmsys_get_match_data_by_clk_name(const struct
> > mtk_mmsys_driver_data **data,
> > + struct device *dev)
> > +{
> > + int i;
> > + struct clk *clk;
> > + const char *clk_name;
> > + const struct of_device_id *of_id =
> > of_match_node(mtk_clk_platform_labels,
> > + dev->of_node);
> > + const struct mtk_mmsys_driver_data *drvdata[] = {
> > + &mt8195_vdosys0_driver_data,
> > + };
> > +
> > + if (!of_id || !of_id->data) {
> > + dev_err(dev, "Can't find match clk platform labels\n");
> > + return -EINVAL;
> > + }
> > +
> > + clk = devm_clk_get(dev, NULL);
> > + if (IS_ERR(clk)) {
> > + dev_err(dev, "failed to get mmsys clk\n");
> > + return PTR_ERR(clk);
> > + }
> > +
> > + clk_name = __clk_get_name(clk);
> > + if (!clk_name) {
> > + dev_err(dev, "invalid mmsys clk name\n");
> > + return -EINVAL;
> > + }
> > +
> > + for (i = 0; i < ARRAY_SIZE(drvdata); i++)
> > + if (strncmp(drvdata[i]->clk_name, clk_name,
> > strlen(clk_name)) == 0 &&
>
> Why not
>
> strcmp(drvdata[i]->clk_name, clk_name) == 0
>
> Regards,
> CK
>
I would like to block strings without '\0', but it doesn't seem
necessary. So I will change to strcmp at the next version.
Regards,
Jason-JH.Lin
> > + strncmp(drvdata[i]->clk_driver, of_id->data,
> > strlen(of_id->data)) == 0) {
> > + *data = drvdata[i];
> > + return 0;
> > + }
> > +
> > + return -EINVAL;
> > +}
> > +
> >
>
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
>
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>
--
Jason-JH Lin <jason-jh.lin@mediatek.com>
_______________________________________________
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^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [RESEND v17 3/7] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
2022-04-07 9:11 ` AngeloGioacchino Del Regno
(?)
@ 2022-04-08 2:42 ` Jason-JH Lin
-1 siblings, 0 replies; 49+ messages in thread
From: Jason-JH Lin @ 2022-04-08 2:42 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Rob Herring, Matthias Brugger, Chun-Kuang Hu
Cc: Philipp Zabel, Maxime Coquelin, David Airlie, Daniel Vetter,
Alexandre Torgue, John 'Warthog9' Hawley, postmaster,
hsinyi, fshao, moudy.ho, roy-cw.yeh, CK Hu, Fabien Parent,
nancy.lin, singo.chang, devicetree, linux-stm32,
linux-arm-kernel, linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group
Hi Angelo,
Thanks for the reviews.
On Thu, 2022-04-07 at 11:11 +0200, AngeloGioacchino Del Regno wrote:
> Il 07/04/22 05:04, jason-jh.lin ha scritto:
> > 1. Add mt8195 mmsys compatible for vdosys0.
> > 2. Add mt8195 routing table settings and fix build fail.
> > 3. Add clock name, clock driver name and routing table into the
> > driver data
> > of mt8195 vdosys0.
> > 4. Add get match data by clock name function and clock platform
> > labels
> > to identify which mmsys node is corresponding to vdosys0.
> >
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
> > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 6 +-
> > drivers/soc/mediatek/mt8167-mmsys.h | 2 +-
> > drivers/soc/mediatek/mt8183-mmsys.h | 2 +-
> > drivers/soc/mediatek/mt8186-mmsys.h | 4 +-
> > drivers/soc/mediatek/mt8192-mmsys.h | 4 +-
> > drivers/soc/mediatek/mt8195-mmsys.h | 370
> > ++++++++++++++++++++
> > drivers/soc/mediatek/mt8365-mmsys.h | 4 +-
> > drivers/soc/mediatek/mtk-mmsys.c | 62 ++++
> > drivers/soc/mediatek/mtk-mmsys.h | 1 +
> > drivers/soc/mediatek/mtk-mutex.c | 8 +-
> > include/linux/soc/mediatek/mtk-mmsys.h | 13 +-
> > 12 files changed, 461 insertions(+), 17 deletions(-)
> > create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
> >
>
> ..snip..
>
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > b/drivers/soc/mediatek/mtk-mmsys.c
> > index 4fc4c2c9ea20..b2fa239c5f5f 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > @@ -4,6 +4,8 @@
> > * Author: James Liao <jamesjj.liao@mediatek.com>
> > */
> >
> > +#include <linux/clk.h>
> > +#include <linux/clk-provider.h>
> > #include <linux/delay.h>
> > #include <linux/device.h>
> > #include <linux/io.h>
> > @@ -17,6 +19,7 @@
> > #include "mt8183-mmsys.h"
> > #include "mt8186-mmsys.h"
> > #include "mt8192-mmsys.h"
> > +#include "mt8195-mmsys.h"
> > #include "mt8365-mmsys.h"
> >
> > static const struct mtk_mmsys_driver_data
> > mt2701_mmsys_driver_data = {
> > @@ -72,12 +75,24 @@ static const struct mtk_mmsys_driver_data
> > mt8192_mmsys_driver_data = {
> > .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
> > };
> >
> > +static const struct mtk_mmsys_driver_data
> > mt8195_vdosys0_driver_data = {
> > + .clk_name = "cfg_vdo0",
> > + .clk_driver = "clk-mt8195-vdo0",
> > + .routes = mmsys_mt8195_routing_table,
> > + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt8365_mmsys_driver_data = {
> > .clk_driver = "clk-mt8365-mm",
> > .routes = mt8365_mmsys_routing_table,
> > .num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
> > };
> >
> > +static const struct of_device_id mtk_clk_platform_labels[] = {
> > + { .compatible = "mediatek,mt8195-mmsys",
> > + .data = (void *)"clk-mt8195"},
>
> I have a hunch that MT8195 won't be the first and last SoC having
> multiple
> mmsys channels. I would tend to think that there will be more....
>
Yes, there will be another SoC with multiple mmsys channels...
> ....so, to make it clean from the beginning, I think that you should,
> at
> this point, assign a struct to that .data pointer, instead of
> declaring a
> drvdata struct into mtk_mmsys_get_match_data_by_clk_name().
>
> Besides, I think that this kind of usage for __clk_get_name() may be
> an API
> abuse... but I'm not sure about that... in any case:
> - if it's not an abuse, then you should simply pass
> mt8195_vdosys0_driver_data,
> or an array of pointers to mtk_mmsys_driver_data;
> - if this is an abuse, you can do the same checks by looking at the
> iostart
> (mmio base address) of the vdosys{0,1} node(s).
Do you mean that I should change clk_name to iostart like this?
mt8195_vdosys0_driver_data = {
.iostart = 0x1c01a000, // instead of clk_name
.clk_driver = "clk-mt8195-vdo0",
.routes = mmsys_mt8195_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
};
Just to confirm that address information can be disclosed here.
If it is not appropriate to use address here, I'll keep using clk_name.
> Honestly, though, I'm not even sure that you need this different
> of_device_id
> array here... since you could simply wrap the mtk_mmsys_driver_data
> in the
> of_match_mtk_mmsys that you have below... here's another idea:
>
> struct mtk_mmsys_match_data {
> const struct mtk_mmsys_driver_data *drv_data[];
> unsigned short num_drv_data;
> };
>
> ...so that:
>
> static int some_function_handling_multi_mmsys(struct mtk_mmsys
> *mmsys,
> struct
> mtk_mmsys_match_data *match)
> {
> int i;
>
> i = [ logic to find the right match->drv_data entry here ]
>
> return i;
> }
>
> static int mtk_mmsys_probe()
> {
> .... variables, something else ....
>
> if (match_data->num_drv_data > 1) {
> /* This SoC has multiple mmsys channels */
> ret = some_function_handling_multi_mmsys(mmsys);
> if (ret < 0)
> return ret;
>
> mmsys->data = match_data->drv_data[ret];
> } else {
> dev_dbg(dev, "Using single mmsys channel\n");
> mmsys->data = match_data->drv_data[0];
> }
>
> ...everything else that mtk_mmsys_probe does ...
> }
I've tried this idea in my local environment and it looks good.
So I'll apply this at the next version. Thanks for your idea!
> What I'm trying to communicate with this is that the currently chosen
> solution
> looks a bit fragile and needs to be made robust.
> In comparison, even if it's not technically right to have two
> different compatibles
> for the same hardware (and shall not be done), the former solution,
> even if wrong,
> was more robust than this one, imo.
>
> Regards,
> Angelo
Because we don't have a property to identify the different mmsys
directly (not using multi-mmsys handle function).
Although it make the code more complicated and not robust, but I think
this time it should be implemented for other multi-mmsys SoC in the
feature.
Regards,
Jason-JH.Lin
-
Jason-JH Lin <jason-jh.lin@mediatek.com>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [RESEND v17 3/7] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
@ 2022-04-08 2:42 ` Jason-JH Lin
0 siblings, 0 replies; 49+ messages in thread
From: Jason-JH Lin @ 2022-04-08 2:42 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Rob Herring, Matthias Brugger, Chun-Kuang Hu
Cc: devicetree, Maxime Coquelin, David Airlie, linux-kernel,
singo.chang, hsinyi, Alexandre Torgue, postmaster,
Project_Global_Chrome_Upstream_Group, Fabien Parent, moudy.ho,
linux-mediatek, roy-cw.yeh, Daniel Vetter,
John 'Warthog9' Hawley, CK Hu, Philipp Zabel, nancy.lin,
linux-stm32, linux-arm-kernel
Hi Angelo,
Thanks for the reviews.
On Thu, 2022-04-07 at 11:11 +0200, AngeloGioacchino Del Regno wrote:
> Il 07/04/22 05:04, jason-jh.lin ha scritto:
> > 1. Add mt8195 mmsys compatible for vdosys0.
> > 2. Add mt8195 routing table settings and fix build fail.
> > 3. Add clock name, clock driver name and routing table into the
> > driver data
> > of mt8195 vdosys0.
> > 4. Add get match data by clock name function and clock platform
> > labels
> > to identify which mmsys node is corresponding to vdosys0.
> >
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
> > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 6 +-
> > drivers/soc/mediatek/mt8167-mmsys.h | 2 +-
> > drivers/soc/mediatek/mt8183-mmsys.h | 2 +-
> > drivers/soc/mediatek/mt8186-mmsys.h | 4 +-
> > drivers/soc/mediatek/mt8192-mmsys.h | 4 +-
> > drivers/soc/mediatek/mt8195-mmsys.h | 370
> > ++++++++++++++++++++
> > drivers/soc/mediatek/mt8365-mmsys.h | 4 +-
> > drivers/soc/mediatek/mtk-mmsys.c | 62 ++++
> > drivers/soc/mediatek/mtk-mmsys.h | 1 +
> > drivers/soc/mediatek/mtk-mutex.c | 8 +-
> > include/linux/soc/mediatek/mtk-mmsys.h | 13 +-
> > 12 files changed, 461 insertions(+), 17 deletions(-)
> > create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
> >
>
> ..snip..
>
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > b/drivers/soc/mediatek/mtk-mmsys.c
> > index 4fc4c2c9ea20..b2fa239c5f5f 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > @@ -4,6 +4,8 @@
> > * Author: James Liao <jamesjj.liao@mediatek.com>
> > */
> >
> > +#include <linux/clk.h>
> > +#include <linux/clk-provider.h>
> > #include <linux/delay.h>
> > #include <linux/device.h>
> > #include <linux/io.h>
> > @@ -17,6 +19,7 @@
> > #include "mt8183-mmsys.h"
> > #include "mt8186-mmsys.h"
> > #include "mt8192-mmsys.h"
> > +#include "mt8195-mmsys.h"
> > #include "mt8365-mmsys.h"
> >
> > static const struct mtk_mmsys_driver_data
> > mt2701_mmsys_driver_data = {
> > @@ -72,12 +75,24 @@ static const struct mtk_mmsys_driver_data
> > mt8192_mmsys_driver_data = {
> > .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
> > };
> >
> > +static const struct mtk_mmsys_driver_data
> > mt8195_vdosys0_driver_data = {
> > + .clk_name = "cfg_vdo0",
> > + .clk_driver = "clk-mt8195-vdo0",
> > + .routes = mmsys_mt8195_routing_table,
> > + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt8365_mmsys_driver_data = {
> > .clk_driver = "clk-mt8365-mm",
> > .routes = mt8365_mmsys_routing_table,
> > .num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
> > };
> >
> > +static const struct of_device_id mtk_clk_platform_labels[] = {
> > + { .compatible = "mediatek,mt8195-mmsys",
> > + .data = (void *)"clk-mt8195"},
>
> I have a hunch that MT8195 won't be the first and last SoC having
> multiple
> mmsys channels. I would tend to think that there will be more....
>
Yes, there will be another SoC with multiple mmsys channels...
> ....so, to make it clean from the beginning, I think that you should,
> at
> this point, assign a struct to that .data pointer, instead of
> declaring a
> drvdata struct into mtk_mmsys_get_match_data_by_clk_name().
>
> Besides, I think that this kind of usage for __clk_get_name() may be
> an API
> abuse... but I'm not sure about that... in any case:
> - if it's not an abuse, then you should simply pass
> mt8195_vdosys0_driver_data,
> or an array of pointers to mtk_mmsys_driver_data;
> - if this is an abuse, you can do the same checks by looking at the
> iostart
> (mmio base address) of the vdosys{0,1} node(s).
Do you mean that I should change clk_name to iostart like this?
mt8195_vdosys0_driver_data = {
.iostart = 0x1c01a000, // instead of clk_name
.clk_driver = "clk-mt8195-vdo0",
.routes = mmsys_mt8195_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
};
Just to confirm that address information can be disclosed here.
If it is not appropriate to use address here, I'll keep using clk_name.
> Honestly, though, I'm not even sure that you need this different
> of_device_id
> array here... since you could simply wrap the mtk_mmsys_driver_data
> in the
> of_match_mtk_mmsys that you have below... here's another idea:
>
> struct mtk_mmsys_match_data {
> const struct mtk_mmsys_driver_data *drv_data[];
> unsigned short num_drv_data;
> };
>
> ...so that:
>
> static int some_function_handling_multi_mmsys(struct mtk_mmsys
> *mmsys,
> struct
> mtk_mmsys_match_data *match)
> {
> int i;
>
> i = [ logic to find the right match->drv_data entry here ]
>
> return i;
> }
>
> static int mtk_mmsys_probe()
> {
> .... variables, something else ....
>
> if (match_data->num_drv_data > 1) {
> /* This SoC has multiple mmsys channels */
> ret = some_function_handling_multi_mmsys(mmsys);
> if (ret < 0)
> return ret;
>
> mmsys->data = match_data->drv_data[ret];
> } else {
> dev_dbg(dev, "Using single mmsys channel\n");
> mmsys->data = match_data->drv_data[0];
> }
>
> ...everything else that mtk_mmsys_probe does ...
> }
I've tried this idea in my local environment and it looks good.
So I'll apply this at the next version. Thanks for your idea!
> What I'm trying to communicate with this is that the currently chosen
> solution
> looks a bit fragile and needs to be made robust.
> In comparison, even if it's not technically right to have two
> different compatibles
> for the same hardware (and shall not be done), the former solution,
> even if wrong,
> was more robust than this one, imo.
>
> Regards,
> Angelo
Because we don't have a property to identify the different mmsys
directly (not using multi-mmsys handle function).
Although it make the code more complicated and not robust, but I think
this time it should be implemented for other multi-mmsys SoC in the
feature.
Regards,
Jason-JH.Lin
-
Jason-JH Lin <jason-jh.lin@mediatek.com>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [RESEND v17 3/7] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
@ 2022-04-08 2:42 ` Jason-JH Lin
0 siblings, 0 replies; 49+ messages in thread
From: Jason-JH Lin @ 2022-04-08 2:42 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Rob Herring, Matthias Brugger, Chun-Kuang Hu
Cc: Philipp Zabel, Maxime Coquelin, David Airlie, Daniel Vetter,
Alexandre Torgue, John 'Warthog9' Hawley, postmaster,
hsinyi, fshao, moudy.ho, roy-cw.yeh, CK Hu, Fabien Parent,
nancy.lin, singo.chang, devicetree, linux-stm32,
linux-arm-kernel, linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group
Hi Angelo,
Thanks for the reviews.
On Thu, 2022-04-07 at 11:11 +0200, AngeloGioacchino Del Regno wrote:
> Il 07/04/22 05:04, jason-jh.lin ha scritto:
> > 1. Add mt8195 mmsys compatible for vdosys0.
> > 2. Add mt8195 routing table settings and fix build fail.
> > 3. Add clock name, clock driver name and routing table into the
> > driver data
> > of mt8195 vdosys0.
> > 4. Add get match data by clock name function and clock platform
> > labels
> > to identify which mmsys node is corresponding to vdosys0.
> >
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
> > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 6 +-
> > drivers/soc/mediatek/mt8167-mmsys.h | 2 +-
> > drivers/soc/mediatek/mt8183-mmsys.h | 2 +-
> > drivers/soc/mediatek/mt8186-mmsys.h | 4 +-
> > drivers/soc/mediatek/mt8192-mmsys.h | 4 +-
> > drivers/soc/mediatek/mt8195-mmsys.h | 370
> > ++++++++++++++++++++
> > drivers/soc/mediatek/mt8365-mmsys.h | 4 +-
> > drivers/soc/mediatek/mtk-mmsys.c | 62 ++++
> > drivers/soc/mediatek/mtk-mmsys.h | 1 +
> > drivers/soc/mediatek/mtk-mutex.c | 8 +-
> > include/linux/soc/mediatek/mtk-mmsys.h | 13 +-
> > 12 files changed, 461 insertions(+), 17 deletions(-)
> > create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
> >
>
> ..snip..
>
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > b/drivers/soc/mediatek/mtk-mmsys.c
> > index 4fc4c2c9ea20..b2fa239c5f5f 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > @@ -4,6 +4,8 @@
> > * Author: James Liao <jamesjj.liao@mediatek.com>
> > */
> >
> > +#include <linux/clk.h>
> > +#include <linux/clk-provider.h>
> > #include <linux/delay.h>
> > #include <linux/device.h>
> > #include <linux/io.h>
> > @@ -17,6 +19,7 @@
> > #include "mt8183-mmsys.h"
> > #include "mt8186-mmsys.h"
> > #include "mt8192-mmsys.h"
> > +#include "mt8195-mmsys.h"
> > #include "mt8365-mmsys.h"
> >
> > static const struct mtk_mmsys_driver_data
> > mt2701_mmsys_driver_data = {
> > @@ -72,12 +75,24 @@ static const struct mtk_mmsys_driver_data
> > mt8192_mmsys_driver_data = {
> > .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
> > };
> >
> > +static const struct mtk_mmsys_driver_data
> > mt8195_vdosys0_driver_data = {
> > + .clk_name = "cfg_vdo0",
> > + .clk_driver = "clk-mt8195-vdo0",
> > + .routes = mmsys_mt8195_routing_table,
> > + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt8365_mmsys_driver_data = {
> > .clk_driver = "clk-mt8365-mm",
> > .routes = mt8365_mmsys_routing_table,
> > .num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
> > };
> >
> > +static const struct of_device_id mtk_clk_platform_labels[] = {
> > + { .compatible = "mediatek,mt8195-mmsys",
> > + .data = (void *)"clk-mt8195"},
>
> I have a hunch that MT8195 won't be the first and last SoC having
> multiple
> mmsys channels. I would tend to think that there will be more....
>
Yes, there will be another SoC with multiple mmsys channels...
> ....so, to make it clean from the beginning, I think that you should,
> at
> this point, assign a struct to that .data pointer, instead of
> declaring a
> drvdata struct into mtk_mmsys_get_match_data_by_clk_name().
>
> Besides, I think that this kind of usage for __clk_get_name() may be
> an API
> abuse... but I'm not sure about that... in any case:
> - if it's not an abuse, then you should simply pass
> mt8195_vdosys0_driver_data,
> or an array of pointers to mtk_mmsys_driver_data;
> - if this is an abuse, you can do the same checks by looking at the
> iostart
> (mmio base address) of the vdosys{0,1} node(s).
Do you mean that I should change clk_name to iostart like this?
mt8195_vdosys0_driver_data = {
.iostart = 0x1c01a000, // instead of clk_name
.clk_driver = "clk-mt8195-vdo0",
.routes = mmsys_mt8195_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
};
Just to confirm that address information can be disclosed here.
If it is not appropriate to use address here, I'll keep using clk_name.
> Honestly, though, I'm not even sure that you need this different
> of_device_id
> array here... since you could simply wrap the mtk_mmsys_driver_data
> in the
> of_match_mtk_mmsys that you have below... here's another idea:
>
> struct mtk_mmsys_match_data {
> const struct mtk_mmsys_driver_data *drv_data[];
> unsigned short num_drv_data;
> };
>
> ...so that:
>
> static int some_function_handling_multi_mmsys(struct mtk_mmsys
> *mmsys,
> struct
> mtk_mmsys_match_data *match)
> {
> int i;
>
> i = [ logic to find the right match->drv_data entry here ]
>
> return i;
> }
>
> static int mtk_mmsys_probe()
> {
> .... variables, something else ....
>
> if (match_data->num_drv_data > 1) {
> /* This SoC has multiple mmsys channels */
> ret = some_function_handling_multi_mmsys(mmsys);
> if (ret < 0)
> return ret;
>
> mmsys->data = match_data->drv_data[ret];
> } else {
> dev_dbg(dev, "Using single mmsys channel\n");
> mmsys->data = match_data->drv_data[0];
> }
>
> ...everything else that mtk_mmsys_probe does ...
> }
I've tried this idea in my local environment and it looks good.
So I'll apply this at the next version. Thanks for your idea!
> What I'm trying to communicate with this is that the currently chosen
> solution
> looks a bit fragile and needs to be made robust.
> In comparison, even if it's not technically right to have two
> different compatibles
> for the same hardware (and shall not be done), the former solution,
> even if wrong,
> was more robust than this one, imo.
>
> Regards,
> Angelo
Because we don't have a property to identify the different mmsys
directly (not using multi-mmsys handle function).
Although it make the code more complicated and not robust, but I think
this time it should be implemented for other multi-mmsys SoC in the
feature.
Regards,
Jason-JH.Lin
-
Jason-JH Lin <jason-jh.lin@mediatek.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [RESEND v17 3/7] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
2022-04-08 2:42 ` Jason-JH Lin
(?)
@ 2022-04-08 8:34 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 49+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-04-08 8:34 UTC (permalink / raw)
To: Jason-JH Lin, Rob Herring, Matthias Brugger, Chun-Kuang Hu
Cc: Philipp Zabel, Maxime Coquelin, David Airlie, Daniel Vetter,
Alexandre Torgue, John 'Warthog9' Hawley, postmaster,
hsinyi, fshao, moudy.ho, roy-cw.yeh, CK Hu, Fabien Parent,
nancy.lin, singo.chang, devicetree, linux-stm32,
linux-arm-kernel, linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group
Il 08/04/22 04:42, Jason-JH Lin ha scritto:
> Hi Angelo,
>
> Thanks for the reviews.
>
> On Thu, 2022-04-07 at 11:11 +0200, AngeloGioacchino Del Regno wrote:
>> Il 07/04/22 05:04, jason-jh.lin ha scritto:
>>> 1. Add mt8195 mmsys compatible for vdosys0.
>>> 2. Add mt8195 routing table settings and fix build fail.
>>> 3. Add clock name, clock driver name and routing table into the
>>> driver data
>>> of mt8195 vdosys0.
>>> 4. Add get match data by clock name function and clock platform
>>> labels
>>> to identify which mmsys node is corresponding to vdosys0.
>>>
>>> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
>>> ---
>>> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
>>> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 6 +-
>>> drivers/soc/mediatek/mt8167-mmsys.h | 2 +-
>>> drivers/soc/mediatek/mt8183-mmsys.h | 2 +-
>>> drivers/soc/mediatek/mt8186-mmsys.h | 4 +-
>>> drivers/soc/mediatek/mt8192-mmsys.h | 4 +-
>>> drivers/soc/mediatek/mt8195-mmsys.h | 370
>>> ++++++++++++++++++++
>>> drivers/soc/mediatek/mt8365-mmsys.h | 4 +-
>>> drivers/soc/mediatek/mtk-mmsys.c | 62 ++++
>>> drivers/soc/mediatek/mtk-mmsys.h | 1 +
>>> drivers/soc/mediatek/mtk-mutex.c | 8 +-
>>> include/linux/soc/mediatek/mtk-mmsys.h | 13 +-
>>> 12 files changed, 461 insertions(+), 17 deletions(-)
>>> create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
>>>
>>
>> ..snip..
>>
>>> diff --git a/drivers/soc/mediatek/mtk-mmsys.c
>>> b/drivers/soc/mediatek/mtk-mmsys.c
>>> index 4fc4c2c9ea20..b2fa239c5f5f 100644
>>> --- a/drivers/soc/mediatek/mtk-mmsys.c
>>> +++ b/drivers/soc/mediatek/mtk-mmsys.c
>>> @@ -4,6 +4,8 @@
>>> * Author: James Liao <jamesjj.liao@mediatek.com>
>>> */
>>>
>>> +#include <linux/clk.h>
>>> +#include <linux/clk-provider.h>
>>> #include <linux/delay.h>
>>> #include <linux/device.h>
>>> #include <linux/io.h>
>>> @@ -17,6 +19,7 @@
>>> #include "mt8183-mmsys.h"
>>> #include "mt8186-mmsys.h"
>>> #include "mt8192-mmsys.h"
>>> +#include "mt8195-mmsys.h"
>>> #include "mt8365-mmsys.h"
>>>
>>> static const struct mtk_mmsys_driver_data
>>> mt2701_mmsys_driver_data = {
>>> @@ -72,12 +75,24 @@ static const struct mtk_mmsys_driver_data
>>> mt8192_mmsys_driver_data = {
>>> .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
>>> };
>>>
>>> +static const struct mtk_mmsys_driver_data
>>> mt8195_vdosys0_driver_data = {
>>> + .clk_name = "cfg_vdo0",
>>> + .clk_driver = "clk-mt8195-vdo0",
>>> + .routes = mmsys_mt8195_routing_table,
>>> + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
>>> +};
>>> +
>>> static const struct mtk_mmsys_driver_data
>>> mt8365_mmsys_driver_data = {
>>> .clk_driver = "clk-mt8365-mm",
>>> .routes = mt8365_mmsys_routing_table,
>>> .num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
>>> };
>>>
>>> +static const struct of_device_id mtk_clk_platform_labels[] = {
>>> + { .compatible = "mediatek,mt8195-mmsys",
>>> + .data = (void *)"clk-mt8195"},
>>
>> I have a hunch that MT8195 won't be the first and last SoC having
>> multiple
>> mmsys channels. I would tend to think that there will be more....
>>
>
> Yes, there will be another SoC with multiple mmsys channels...
>
>> ....so, to make it clean from the beginning, I think that you should,
>> at
>> this point, assign a struct to that .data pointer, instead of
>> declaring a
>> drvdata struct into mtk_mmsys_get_match_data_by_clk_name().
>>
>> Besides, I think that this kind of usage for __clk_get_name() may be
>> an API
>> abuse... but I'm not sure about that... in any case:
>> - if it's not an abuse, then you should simply pass
>> mt8195_vdosys0_driver_data,
>> or an array of pointers to mtk_mmsys_driver_data;
>> - if this is an abuse, you can do the same checks by looking at the
>> iostart
>> (mmio base address) of the vdosys{0,1} node(s).
>
> Do you mean that I should change clk_name to iostart like this?
>
> mt8195_vdosys0_driver_data = {
> .iostart = 0x1c01a000, // instead of clk_name
> .clk_driver = "clk-mt8195-vdo0",
> .routes = mmsys_mt8195_routing_table,
> .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> };
>
> Just to confirm that address information can be disclosed here.
> If it is not appropriate to use address here, I'll keep using clk_name.
>
Yes Jason, even if that looks strange, it is an accepted behavior... at
least, on Qualcomm drivers, it was done exactly like that.
Besides, I'm sure that you will definitely agree with me that operations
on strings are way slower than checking "a number" :) :) :)
By the way, check that one out, that'll probably help you:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c?h=next-20220408#n789
>> Honestly, though, I'm not even sure that you need this different
>> of_device_id
>> array here... since you could simply wrap the mtk_mmsys_driver_data
>> in the
>> of_match_mtk_mmsys that you have below... here's another idea:
>>
>> struct mtk_mmsys_match_data {
>> const struct mtk_mmsys_driver_data *drv_data[];
>> unsigned short num_drv_data;
>> };
>>
>> ...so that:
>>
>> static int some_function_handling_multi_mmsys(struct mtk_mmsys
>> *mmsys,
>> struct
>> mtk_mmsys_match_data *match)
>> {
>> int i;
>>
>> i = [ logic to find the right match->drv_data entry here ]
>>
>> return i;
>> }
>>
>> static int mtk_mmsys_probe()
>> {
>> .... variables, something else ....
>>
>> if (match_data->num_drv_data > 1) {
>> /* This SoC has multiple mmsys channels */
>> ret = some_function_handling_multi_mmsys(mmsys);
>> if (ret < 0)
>> return ret;
>>
>> mmsys->data = match_data->drv_data[ret];
>> } else {
>> dev_dbg(dev, "Using single mmsys channel\n");
>> mmsys->data = match_data->drv_data[0];
>> }
>>
>> ...everything else that mtk_mmsys_probe does ...
>> }
>
> I've tried this idea in my local environment and it looks good.
> So I'll apply this at the next version. Thanks for your idea!
>
You're welcome! Looking forward to the next version!
>> What I'm trying to communicate with this is that the currently chosen
>> solution
>> looks a bit fragile and needs to be made robust.
>> In comparison, even if it's not technically right to have two
>> different compatibles
>> for the same hardware (and shall not be done), the former solution,
>> even if wrong,
>> was more robust than this one, imo.
>>
>> Regards,
>> Angelo
>
> Because we don't have a property to identify the different mmsys
> directly (not using multi-mmsys handle function).
>
> Although it make the code more complicated and not robust, but I think
> this time it should be implemented for other multi-mmsys SoC in the
> feature.
>
>
Yes, and I agree: please keep doing this future-proofing, it's a good thing,
as long as the code keeps being readable and robust!
Cheers,
Angelo
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [RESEND v17 3/7] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
@ 2022-04-08 8:34 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 49+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-04-08 8:34 UTC (permalink / raw)
To: Jason-JH Lin, Rob Herring, Matthias Brugger, Chun-Kuang Hu
Cc: devicetree, Maxime Coquelin, David Airlie, linux-kernel,
singo.chang, hsinyi, Alexandre Torgue, postmaster,
Project_Global_Chrome_Upstream_Group, Fabien Parent, moudy.ho,
linux-mediatek, roy-cw.yeh, Daniel Vetter,
John 'Warthog9' Hawley, CK Hu, Philipp Zabel, nancy.lin,
linux-stm32, linux-arm-kernel
Il 08/04/22 04:42, Jason-JH Lin ha scritto:
> Hi Angelo,
>
> Thanks for the reviews.
>
> On Thu, 2022-04-07 at 11:11 +0200, AngeloGioacchino Del Regno wrote:
>> Il 07/04/22 05:04, jason-jh.lin ha scritto:
>>> 1. Add mt8195 mmsys compatible for vdosys0.
>>> 2. Add mt8195 routing table settings and fix build fail.
>>> 3. Add clock name, clock driver name and routing table into the
>>> driver data
>>> of mt8195 vdosys0.
>>> 4. Add get match data by clock name function and clock platform
>>> labels
>>> to identify which mmsys node is corresponding to vdosys0.
>>>
>>> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
>>> ---
>>> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
>>> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 6 +-
>>> drivers/soc/mediatek/mt8167-mmsys.h | 2 +-
>>> drivers/soc/mediatek/mt8183-mmsys.h | 2 +-
>>> drivers/soc/mediatek/mt8186-mmsys.h | 4 +-
>>> drivers/soc/mediatek/mt8192-mmsys.h | 4 +-
>>> drivers/soc/mediatek/mt8195-mmsys.h | 370
>>> ++++++++++++++++++++
>>> drivers/soc/mediatek/mt8365-mmsys.h | 4 +-
>>> drivers/soc/mediatek/mtk-mmsys.c | 62 ++++
>>> drivers/soc/mediatek/mtk-mmsys.h | 1 +
>>> drivers/soc/mediatek/mtk-mutex.c | 8 +-
>>> include/linux/soc/mediatek/mtk-mmsys.h | 13 +-
>>> 12 files changed, 461 insertions(+), 17 deletions(-)
>>> create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
>>>
>>
>> ..snip..
>>
>>> diff --git a/drivers/soc/mediatek/mtk-mmsys.c
>>> b/drivers/soc/mediatek/mtk-mmsys.c
>>> index 4fc4c2c9ea20..b2fa239c5f5f 100644
>>> --- a/drivers/soc/mediatek/mtk-mmsys.c
>>> +++ b/drivers/soc/mediatek/mtk-mmsys.c
>>> @@ -4,6 +4,8 @@
>>> * Author: James Liao <jamesjj.liao@mediatek.com>
>>> */
>>>
>>> +#include <linux/clk.h>
>>> +#include <linux/clk-provider.h>
>>> #include <linux/delay.h>
>>> #include <linux/device.h>
>>> #include <linux/io.h>
>>> @@ -17,6 +19,7 @@
>>> #include "mt8183-mmsys.h"
>>> #include "mt8186-mmsys.h"
>>> #include "mt8192-mmsys.h"
>>> +#include "mt8195-mmsys.h"
>>> #include "mt8365-mmsys.h"
>>>
>>> static const struct mtk_mmsys_driver_data
>>> mt2701_mmsys_driver_data = {
>>> @@ -72,12 +75,24 @@ static const struct mtk_mmsys_driver_data
>>> mt8192_mmsys_driver_data = {
>>> .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
>>> };
>>>
>>> +static const struct mtk_mmsys_driver_data
>>> mt8195_vdosys0_driver_data = {
>>> + .clk_name = "cfg_vdo0",
>>> + .clk_driver = "clk-mt8195-vdo0",
>>> + .routes = mmsys_mt8195_routing_table,
>>> + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
>>> +};
>>> +
>>> static const struct mtk_mmsys_driver_data
>>> mt8365_mmsys_driver_data = {
>>> .clk_driver = "clk-mt8365-mm",
>>> .routes = mt8365_mmsys_routing_table,
>>> .num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
>>> };
>>>
>>> +static const struct of_device_id mtk_clk_platform_labels[] = {
>>> + { .compatible = "mediatek,mt8195-mmsys",
>>> + .data = (void *)"clk-mt8195"},
>>
>> I have a hunch that MT8195 won't be the first and last SoC having
>> multiple
>> mmsys channels. I would tend to think that there will be more....
>>
>
> Yes, there will be another SoC with multiple mmsys channels...
>
>> ....so, to make it clean from the beginning, I think that you should,
>> at
>> this point, assign a struct to that .data pointer, instead of
>> declaring a
>> drvdata struct into mtk_mmsys_get_match_data_by_clk_name().
>>
>> Besides, I think that this kind of usage for __clk_get_name() may be
>> an API
>> abuse... but I'm not sure about that... in any case:
>> - if it's not an abuse, then you should simply pass
>> mt8195_vdosys0_driver_data,
>> or an array of pointers to mtk_mmsys_driver_data;
>> - if this is an abuse, you can do the same checks by looking at the
>> iostart
>> (mmio base address) of the vdosys{0,1} node(s).
>
> Do you mean that I should change clk_name to iostart like this?
>
> mt8195_vdosys0_driver_data = {
> .iostart = 0x1c01a000, // instead of clk_name
> .clk_driver = "clk-mt8195-vdo0",
> .routes = mmsys_mt8195_routing_table,
> .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> };
>
> Just to confirm that address information can be disclosed here.
> If it is not appropriate to use address here, I'll keep using clk_name.
>
Yes Jason, even if that looks strange, it is an accepted behavior... at
least, on Qualcomm drivers, it was done exactly like that.
Besides, I'm sure that you will definitely agree with me that operations
on strings are way slower than checking "a number" :) :) :)
By the way, check that one out, that'll probably help you:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c?h=next-20220408#n789
>> Honestly, though, I'm not even sure that you need this different
>> of_device_id
>> array here... since you could simply wrap the mtk_mmsys_driver_data
>> in the
>> of_match_mtk_mmsys that you have below... here's another idea:
>>
>> struct mtk_mmsys_match_data {
>> const struct mtk_mmsys_driver_data *drv_data[];
>> unsigned short num_drv_data;
>> };
>>
>> ...so that:
>>
>> static int some_function_handling_multi_mmsys(struct mtk_mmsys
>> *mmsys,
>> struct
>> mtk_mmsys_match_data *match)
>> {
>> int i;
>>
>> i = [ logic to find the right match->drv_data entry here ]
>>
>> return i;
>> }
>>
>> static int mtk_mmsys_probe()
>> {
>> .... variables, something else ....
>>
>> if (match_data->num_drv_data > 1) {
>> /* This SoC has multiple mmsys channels */
>> ret = some_function_handling_multi_mmsys(mmsys);
>> if (ret < 0)
>> return ret;
>>
>> mmsys->data = match_data->drv_data[ret];
>> } else {
>> dev_dbg(dev, "Using single mmsys channel\n");
>> mmsys->data = match_data->drv_data[0];
>> }
>>
>> ...everything else that mtk_mmsys_probe does ...
>> }
>
> I've tried this idea in my local environment and it looks good.
> So I'll apply this at the next version. Thanks for your idea!
>
You're welcome! Looking forward to the next version!
>> What I'm trying to communicate with this is that the currently chosen
>> solution
>> looks a bit fragile and needs to be made robust.
>> In comparison, even if it's not technically right to have two
>> different compatibles
>> for the same hardware (and shall not be done), the former solution,
>> even if wrong,
>> was more robust than this one, imo.
>>
>> Regards,
>> Angelo
>
> Because we don't have a property to identify the different mmsys
> directly (not using multi-mmsys handle function).
>
> Although it make the code more complicated and not robust, but I think
> this time it should be implemented for other multi-mmsys SoC in the
> feature.
>
>
Yes, and I agree: please keep doing this future-proofing, it's a good thing,
as long as the code keeps being readable and robust!
Cheers,
Angelo
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [RESEND v17 3/7] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
@ 2022-04-08 8:34 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 49+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-04-08 8:34 UTC (permalink / raw)
To: Jason-JH Lin, Rob Herring, Matthias Brugger, Chun-Kuang Hu
Cc: Philipp Zabel, Maxime Coquelin, David Airlie, Daniel Vetter,
Alexandre Torgue, John 'Warthog9' Hawley, postmaster,
hsinyi, fshao, moudy.ho, roy-cw.yeh, CK Hu, Fabien Parent,
nancy.lin, singo.chang, devicetree, linux-stm32,
linux-arm-kernel, linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group
Il 08/04/22 04:42, Jason-JH Lin ha scritto:
> Hi Angelo,
>
> Thanks for the reviews.
>
> On Thu, 2022-04-07 at 11:11 +0200, AngeloGioacchino Del Regno wrote:
>> Il 07/04/22 05:04, jason-jh.lin ha scritto:
>>> 1. Add mt8195 mmsys compatible for vdosys0.
>>> 2. Add mt8195 routing table settings and fix build fail.
>>> 3. Add clock name, clock driver name and routing table into the
>>> driver data
>>> of mt8195 vdosys0.
>>> 4. Add get match data by clock name function and clock platform
>>> labels
>>> to identify which mmsys node is corresponding to vdosys0.
>>>
>>> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
>>> ---
>>> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
>>> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 6 +-
>>> drivers/soc/mediatek/mt8167-mmsys.h | 2 +-
>>> drivers/soc/mediatek/mt8183-mmsys.h | 2 +-
>>> drivers/soc/mediatek/mt8186-mmsys.h | 4 +-
>>> drivers/soc/mediatek/mt8192-mmsys.h | 4 +-
>>> drivers/soc/mediatek/mt8195-mmsys.h | 370
>>> ++++++++++++++++++++
>>> drivers/soc/mediatek/mt8365-mmsys.h | 4 +-
>>> drivers/soc/mediatek/mtk-mmsys.c | 62 ++++
>>> drivers/soc/mediatek/mtk-mmsys.h | 1 +
>>> drivers/soc/mediatek/mtk-mutex.c | 8 +-
>>> include/linux/soc/mediatek/mtk-mmsys.h | 13 +-
>>> 12 files changed, 461 insertions(+), 17 deletions(-)
>>> create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
>>>
>>
>> ..snip..
>>
>>> diff --git a/drivers/soc/mediatek/mtk-mmsys.c
>>> b/drivers/soc/mediatek/mtk-mmsys.c
>>> index 4fc4c2c9ea20..b2fa239c5f5f 100644
>>> --- a/drivers/soc/mediatek/mtk-mmsys.c
>>> +++ b/drivers/soc/mediatek/mtk-mmsys.c
>>> @@ -4,6 +4,8 @@
>>> * Author: James Liao <jamesjj.liao@mediatek.com>
>>> */
>>>
>>> +#include <linux/clk.h>
>>> +#include <linux/clk-provider.h>
>>> #include <linux/delay.h>
>>> #include <linux/device.h>
>>> #include <linux/io.h>
>>> @@ -17,6 +19,7 @@
>>> #include "mt8183-mmsys.h"
>>> #include "mt8186-mmsys.h"
>>> #include "mt8192-mmsys.h"
>>> +#include "mt8195-mmsys.h"
>>> #include "mt8365-mmsys.h"
>>>
>>> static const struct mtk_mmsys_driver_data
>>> mt2701_mmsys_driver_data = {
>>> @@ -72,12 +75,24 @@ static const struct mtk_mmsys_driver_data
>>> mt8192_mmsys_driver_data = {
>>> .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
>>> };
>>>
>>> +static const struct mtk_mmsys_driver_data
>>> mt8195_vdosys0_driver_data = {
>>> + .clk_name = "cfg_vdo0",
>>> + .clk_driver = "clk-mt8195-vdo0",
>>> + .routes = mmsys_mt8195_routing_table,
>>> + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
>>> +};
>>> +
>>> static const struct mtk_mmsys_driver_data
>>> mt8365_mmsys_driver_data = {
>>> .clk_driver = "clk-mt8365-mm",
>>> .routes = mt8365_mmsys_routing_table,
>>> .num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
>>> };
>>>
>>> +static const struct of_device_id mtk_clk_platform_labels[] = {
>>> + { .compatible = "mediatek,mt8195-mmsys",
>>> + .data = (void *)"clk-mt8195"},
>>
>> I have a hunch that MT8195 won't be the first and last SoC having
>> multiple
>> mmsys channels. I would tend to think that there will be more....
>>
>
> Yes, there will be another SoC with multiple mmsys channels...
>
>> ....so, to make it clean from the beginning, I think that you should,
>> at
>> this point, assign a struct to that .data pointer, instead of
>> declaring a
>> drvdata struct into mtk_mmsys_get_match_data_by_clk_name().
>>
>> Besides, I think that this kind of usage for __clk_get_name() may be
>> an API
>> abuse... but I'm not sure about that... in any case:
>> - if it's not an abuse, then you should simply pass
>> mt8195_vdosys0_driver_data,
>> or an array of pointers to mtk_mmsys_driver_data;
>> - if this is an abuse, you can do the same checks by looking at the
>> iostart
>> (mmio base address) of the vdosys{0,1} node(s).
>
> Do you mean that I should change clk_name to iostart like this?
>
> mt8195_vdosys0_driver_data = {
> .iostart = 0x1c01a000, // instead of clk_name
> .clk_driver = "clk-mt8195-vdo0",
> .routes = mmsys_mt8195_routing_table,
> .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> };
>
> Just to confirm that address information can be disclosed here.
> If it is not appropriate to use address here, I'll keep using clk_name.
>
Yes Jason, even if that looks strange, it is an accepted behavior... at
least, on Qualcomm drivers, it was done exactly like that.
Besides, I'm sure that you will definitely agree with me that operations
on strings are way slower than checking "a number" :) :) :)
By the way, check that one out, that'll probably help you:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c?h=next-20220408#n789
>> Honestly, though, I'm not even sure that you need this different
>> of_device_id
>> array here... since you could simply wrap the mtk_mmsys_driver_data
>> in the
>> of_match_mtk_mmsys that you have below... here's another idea:
>>
>> struct mtk_mmsys_match_data {
>> const struct mtk_mmsys_driver_data *drv_data[];
>> unsigned short num_drv_data;
>> };
>>
>> ...so that:
>>
>> static int some_function_handling_multi_mmsys(struct mtk_mmsys
>> *mmsys,
>> struct
>> mtk_mmsys_match_data *match)
>> {
>> int i;
>>
>> i = [ logic to find the right match->drv_data entry here ]
>>
>> return i;
>> }
>>
>> static int mtk_mmsys_probe()
>> {
>> .... variables, something else ....
>>
>> if (match_data->num_drv_data > 1) {
>> /* This SoC has multiple mmsys channels */
>> ret = some_function_handling_multi_mmsys(mmsys);
>> if (ret < 0)
>> return ret;
>>
>> mmsys->data = match_data->drv_data[ret];
>> } else {
>> dev_dbg(dev, "Using single mmsys channel\n");
>> mmsys->data = match_data->drv_data[0];
>> }
>>
>> ...everything else that mtk_mmsys_probe does ...
>> }
>
> I've tried this idea in my local environment and it looks good.
> So I'll apply this at the next version. Thanks for your idea!
>
You're welcome! Looking forward to the next version!
>> What I'm trying to communicate with this is that the currently chosen
>> solution
>> looks a bit fragile and needs to be made robust.
>> In comparison, even if it's not technically right to have two
>> different compatibles
>> for the same hardware (and shall not be done), the former solution,
>> even if wrong,
>> was more robust than this one, imo.
>>
>> Regards,
>> Angelo
>
> Because we don't have a property to identify the different mmsys
> directly (not using multi-mmsys handle function).
>
> Although it make the code more complicated and not robust, but I think
> this time it should be implemented for other multi-mmsys SoC in the
> feature.
>
>
Yes, and I agree: please keep doing this future-proofing, it's a good thing,
as long as the code keeps being readable and robust!
Cheers,
Angelo
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [RESEND v17 3/7] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
2022-04-08 1:28 ` CK Hu
(?)
@ 2022-04-08 8:49 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 49+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-04-08 8:49 UTC (permalink / raw)
To: CK Hu, Jason-JH Lin, Rob Herring, Matthias Brugger, Chun-Kuang Hu
Cc: David Airlie, singo.chang, Alexandre Torgue, postmaster,
Fabien Parent, John 'Warthog9' Hawley, linux-stm32,
roy-cw.yeh, Project_Global_Chrome_Upstream_Group, Philipp Zabel,
devicetree, Daniel Vetter, nancy.lin, linux-mediatek, hsinyi,
linux-arm-kernel, linux-kernel, moudy.ho, Maxime Coquelin
Il 08/04/22 03:28, CK Hu ha scritto:
> Hi, Jason:
>
> On Thu, 2022-04-07 at 14:27 +0800, Jason-JH Lin wrote:
>> Hi CK,
>>
>> Thanks for the reviews.
>>
>> On Thu, 2022-04-07 at 13:45 +0800, CK Hu wrote:
>>> Hi, Jason:
>>>
>>> On Thu, 2022-04-07 at 11:04 +0800, jason-jh.lin wrote:
>>>> 1. Add mt8195 mmsys compatible for vdosys0.
>>>> 2. Add mt8195 routing table settings and fix build fail.
>>>> 3. Add clock name, clock driver name and routing table into the
>>>> driver data
>>>> of mt8195 vdosys0.
>>>> 4. Add get match data by clock name function and clock platform
>>>> labels
>>>> to identify which mmsys node is corresponding to vdosys0.
>>>>
>>>> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
>>>> ---
>>>> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
>>>> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 6 +-
>>>> drivers/soc/mediatek/mt8167-mmsys.h | 2 +-
>>>> drivers/soc/mediatek/mt8183-mmsys.h | 2 +-
>>>> drivers/soc/mediatek/mt8186-mmsys.h | 4 +-
>>>> drivers/soc/mediatek/mt8192-mmsys.h | 4 +-
>>>> drivers/soc/mediatek/mt8195-mmsys.h | 370
>>>> ++++++++++++++++++++
>>>> drivers/soc/mediatek/mt8365-mmsys.h | 4 +-
>>>> drivers/soc/mediatek/mtk-mmsys.c | 62 ++++
>>>> drivers/soc/mediatek/mtk-mmsys.h | 1 +
>>>> drivers/soc/mediatek/mtk-mutex.c | 8 +-
>>>> include/linux/soc/mediatek/mtk-mmsys.h | 13 +-
>>>> 12 files changed, 461 insertions(+), 17 deletions(-)
>>>> create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
>>>>
>>>
>>> [snip]
>>>
>>>> diff --git a/drivers/soc/mediatek/mtk-mmsys.c
>>>> b/drivers/soc/mediatek/mtk-mmsys.c
>>>> index 4fc4c2c9ea20..b2fa239c5f5f 100644
>>>> --- a/drivers/soc/mediatek/mtk-mmsys.c
>>>> +++ b/drivers/soc/mediatek/mtk-mmsys.c
>>>> @@ -4,6 +4,8 @@
>>>> * Author: James Liao <jamesjj.liao@mediatek.com>
>>>> */
>>>>
..snip..
>>
>> I think there might be another chip that needs to get driver data by
>> clk_name .
>> So I use "clk-mt8195" in clk_driver to identify the corresponding
>> platform whose clk_name of mmsys is also "cfg_vod0".
>
> We usually don't care the future because the future may not happen. If
Hello CK,
I'm sorry, but I really have to disagree here.
Sure, the future may not happen, but from what I can see, MediaTek's commitment
on upstreaming their SoCs is continuative and they care about the future.
Let's also not forget that these drivers are not on a downstream tree, where
you don't care about the past or the future, but on upstream, where you:
- Definitely care about the past
- Should care about the future, if you want to avoid commit noise and
making big changes to your drivers everytime, which would slow down
your upstreaming due to reviewers having to put 3x efforts on each
iteration.
And let's also not forget that this being upstream means that these drivers
may (or may not) be extended even by passionate community developers, for
which, having such mechanisms there for other SoCs that MediaTek didn't try
to upstream yet can only be good - and when these are engineered with a
certain flexibility, while keeping the codebase solid, that can only be good.
Besides, if I've misunderstood your "don't care the future" statement,
pretend that I've never replied.
> it's sure that would happen, I think clk_driver is not a good choice.
> For now, the clk_driver name is different for each SoC, but it could be
> the same for each SoC because only one clock driver would be compiled.
> I think "compatible" would be different for each SoC.
>
...but I agree on that one (and I gave my own review and suggestions on
how to improve that situation).
Regards,
Angelo
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [RESEND v17 3/7] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
@ 2022-04-08 8:49 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 49+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-04-08 8:49 UTC (permalink / raw)
To: CK Hu, Jason-JH Lin, Rob Herring, Matthias Brugger, Chun-Kuang Hu
Cc: David Airlie, singo.chang, Alexandre Torgue, postmaster,
Fabien Parent, John 'Warthog9' Hawley, linux-stm32,
roy-cw.yeh, Project_Global_Chrome_Upstream_Group, Philipp Zabel,
devicetree, Daniel Vetter, nancy.lin, linux-mediatek, hsinyi,
linux-arm-kernel, linux-kernel, moudy.ho, Maxime Coquelin
Il 08/04/22 03:28, CK Hu ha scritto:
> Hi, Jason:
>
> On Thu, 2022-04-07 at 14:27 +0800, Jason-JH Lin wrote:
>> Hi CK,
>>
>> Thanks for the reviews.
>>
>> On Thu, 2022-04-07 at 13:45 +0800, CK Hu wrote:
>>> Hi, Jason:
>>>
>>> On Thu, 2022-04-07 at 11:04 +0800, jason-jh.lin wrote:
>>>> 1. Add mt8195 mmsys compatible for vdosys0.
>>>> 2. Add mt8195 routing table settings and fix build fail.
>>>> 3. Add clock name, clock driver name and routing table into the
>>>> driver data
>>>> of mt8195 vdosys0.
>>>> 4. Add get match data by clock name function and clock platform
>>>> labels
>>>> to identify which mmsys node is corresponding to vdosys0.
>>>>
>>>> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
>>>> ---
>>>> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
>>>> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 6 +-
>>>> drivers/soc/mediatek/mt8167-mmsys.h | 2 +-
>>>> drivers/soc/mediatek/mt8183-mmsys.h | 2 +-
>>>> drivers/soc/mediatek/mt8186-mmsys.h | 4 +-
>>>> drivers/soc/mediatek/mt8192-mmsys.h | 4 +-
>>>> drivers/soc/mediatek/mt8195-mmsys.h | 370
>>>> ++++++++++++++++++++
>>>> drivers/soc/mediatek/mt8365-mmsys.h | 4 +-
>>>> drivers/soc/mediatek/mtk-mmsys.c | 62 ++++
>>>> drivers/soc/mediatek/mtk-mmsys.h | 1 +
>>>> drivers/soc/mediatek/mtk-mutex.c | 8 +-
>>>> include/linux/soc/mediatek/mtk-mmsys.h | 13 +-
>>>> 12 files changed, 461 insertions(+), 17 deletions(-)
>>>> create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
>>>>
>>>
>>> [snip]
>>>
>>>> diff --git a/drivers/soc/mediatek/mtk-mmsys.c
>>>> b/drivers/soc/mediatek/mtk-mmsys.c
>>>> index 4fc4c2c9ea20..b2fa239c5f5f 100644
>>>> --- a/drivers/soc/mediatek/mtk-mmsys.c
>>>> +++ b/drivers/soc/mediatek/mtk-mmsys.c
>>>> @@ -4,6 +4,8 @@
>>>> * Author: James Liao <jamesjj.liao@mediatek.com>
>>>> */
>>>>
..snip..
>>
>> I think there might be another chip that needs to get driver data by
>> clk_name .
>> So I use "clk-mt8195" in clk_driver to identify the corresponding
>> platform whose clk_name of mmsys is also "cfg_vod0".
>
> We usually don't care the future because the future may not happen. If
Hello CK,
I'm sorry, but I really have to disagree here.
Sure, the future may not happen, but from what I can see, MediaTek's commitment
on upstreaming their SoCs is continuative and they care about the future.
Let's also not forget that these drivers are not on a downstream tree, where
you don't care about the past or the future, but on upstream, where you:
- Definitely care about the past
- Should care about the future, if you want to avoid commit noise and
making big changes to your drivers everytime, which would slow down
your upstreaming due to reviewers having to put 3x efforts on each
iteration.
And let's also not forget that this being upstream means that these drivers
may (or may not) be extended even by passionate community developers, for
which, having such mechanisms there for other SoCs that MediaTek didn't try
to upstream yet can only be good - and when these are engineered with a
certain flexibility, while keeping the codebase solid, that can only be good.
Besides, if I've misunderstood your "don't care the future" statement,
pretend that I've never replied.
> it's sure that would happen, I think clk_driver is not a good choice.
> For now, the clk_driver name is different for each SoC, but it could be
> the same for each SoC because only one clock driver would be compiled.
> I think "compatible" would be different for each SoC.
>
...but I agree on that one (and I gave my own review and suggestions on
how to improve that situation).
Regards,
Angelo
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [RESEND v17 3/7] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
@ 2022-04-08 8:49 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 49+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-04-08 8:49 UTC (permalink / raw)
To: CK Hu, Jason-JH Lin, Rob Herring, Matthias Brugger, Chun-Kuang Hu
Cc: David Airlie, singo.chang, Alexandre Torgue, postmaster,
Fabien Parent, John 'Warthog9' Hawley, linux-stm32,
roy-cw.yeh, Project_Global_Chrome_Upstream_Group, Philipp Zabel,
devicetree, Daniel Vetter, nancy.lin, linux-mediatek, hsinyi,
linux-arm-kernel, linux-kernel, moudy.ho, Maxime Coquelin
Il 08/04/22 03:28, CK Hu ha scritto:
> Hi, Jason:
>
> On Thu, 2022-04-07 at 14:27 +0800, Jason-JH Lin wrote:
>> Hi CK,
>>
>> Thanks for the reviews.
>>
>> On Thu, 2022-04-07 at 13:45 +0800, CK Hu wrote:
>>> Hi, Jason:
>>>
>>> On Thu, 2022-04-07 at 11:04 +0800, jason-jh.lin wrote:
>>>> 1. Add mt8195 mmsys compatible for vdosys0.
>>>> 2. Add mt8195 routing table settings and fix build fail.
>>>> 3. Add clock name, clock driver name and routing table into the
>>>> driver data
>>>> of mt8195 vdosys0.
>>>> 4. Add get match data by clock name function and clock platform
>>>> labels
>>>> to identify which mmsys node is corresponding to vdosys0.
>>>>
>>>> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
>>>> ---
>>>> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
>>>> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 6 +-
>>>> drivers/soc/mediatek/mt8167-mmsys.h | 2 +-
>>>> drivers/soc/mediatek/mt8183-mmsys.h | 2 +-
>>>> drivers/soc/mediatek/mt8186-mmsys.h | 4 +-
>>>> drivers/soc/mediatek/mt8192-mmsys.h | 4 +-
>>>> drivers/soc/mediatek/mt8195-mmsys.h | 370
>>>> ++++++++++++++++++++
>>>> drivers/soc/mediatek/mt8365-mmsys.h | 4 +-
>>>> drivers/soc/mediatek/mtk-mmsys.c | 62 ++++
>>>> drivers/soc/mediatek/mtk-mmsys.h | 1 +
>>>> drivers/soc/mediatek/mtk-mutex.c | 8 +-
>>>> include/linux/soc/mediatek/mtk-mmsys.h | 13 +-
>>>> 12 files changed, 461 insertions(+), 17 deletions(-)
>>>> create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
>>>>
>>>
>>> [snip]
>>>
>>>> diff --git a/drivers/soc/mediatek/mtk-mmsys.c
>>>> b/drivers/soc/mediatek/mtk-mmsys.c
>>>> index 4fc4c2c9ea20..b2fa239c5f5f 100644
>>>> --- a/drivers/soc/mediatek/mtk-mmsys.c
>>>> +++ b/drivers/soc/mediatek/mtk-mmsys.c
>>>> @@ -4,6 +4,8 @@
>>>> * Author: James Liao <jamesjj.liao@mediatek.com>
>>>> */
>>>>
..snip..
>>
>> I think there might be another chip that needs to get driver data by
>> clk_name .
>> So I use "clk-mt8195" in clk_driver to identify the corresponding
>> platform whose clk_name of mmsys is also "cfg_vod0".
>
> We usually don't care the future because the future may not happen. If
Hello CK,
I'm sorry, but I really have to disagree here.
Sure, the future may not happen, but from what I can see, MediaTek's commitment
on upstreaming their SoCs is continuative and they care about the future.
Let's also not forget that these drivers are not on a downstream tree, where
you don't care about the past or the future, but on upstream, where you:
- Definitely care about the past
- Should care about the future, if you want to avoid commit noise and
making big changes to your drivers everytime, which would slow down
your upstreaming due to reviewers having to put 3x efforts on each
iteration.
And let's also not forget that this being upstream means that these drivers
may (or may not) be extended even by passionate community developers, for
which, having such mechanisms there for other SoCs that MediaTek didn't try
to upstream yet can only be good - and when these are engineered with a
certain flexibility, while keeping the codebase solid, that can only be good.
Besides, if I've misunderstood your "don't care the future" statement,
pretend that I've never replied.
> it's sure that would happen, I think clk_driver is not a good choice.
> For now, the clk_driver name is different for each SoC, but it could be
> the same for each SoC because only one clock driver would be compiled.
> I think "compatible" would be different for each SoC.
>
...but I agree on that one (and I gave my own review and suggestions on
how to improve that situation).
Regards,
Angelo
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [RESEND v17 3/7] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
2022-04-08 8:49 ` AngeloGioacchino Del Regno
(?)
@ 2022-04-12 6:33 ` CK Hu
-1 siblings, 0 replies; 49+ messages in thread
From: CK Hu @ 2022-04-12 6:33 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Jason-JH Lin, Rob Herring,
Matthias Brugger, Chun-Kuang Hu
Cc: David Airlie, singo.chang, Alexandre Torgue, postmaster,
Fabien Parent, John 'Warthog9' Hawley, linux-stm32,
roy-cw.yeh, Project_Global_Chrome_Upstream_Group, Philipp Zabel,
devicetree, Daniel Vetter, nancy.lin, linux-mediatek, hsinyi,
linux-arm-kernel, linux-kernel, moudy.ho, Maxime Coquelin
Hi, Angelo:
On Fri, 2022-04-08 at 10:49 +0200, AngeloGioacchino Del Regno wrote:
> Il 08/04/22 03:28, CK Hu ha scritto:
> > Hi, Jason:
> >
> > On Thu, 2022-04-07 at 14:27 +0800, Jason-JH Lin wrote:
> > > Hi CK,
> > >
> > > Thanks for the reviews.
> > >
> > > On Thu, 2022-04-07 at 13:45 +0800, CK Hu wrote:
> > > > Hi, Jason:
> > > >
> > > > On Thu, 2022-04-07 at 11:04 +0800, jason-jh.lin wrote:
> > > > > 1. Add mt8195 mmsys compatible for vdosys0.
> > > > > 2. Add mt8195 routing table settings and fix build fail.
> > > > > 3. Add clock name, clock driver name and routing table into
> > > > > the
> > > > > driver data
> > > > > of mt8195 vdosys0.
> > > > > 4. Add get match data by clock name function and clock
> > > > > platform
> > > > > labels
> > > > > to identify which mmsys node is corresponding to vdosys0.
> > > > >
> > > > > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > > > > ---
> > > > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
> > > > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 6 +-
> > > > > drivers/soc/mediatek/mt8167-mmsys.h | 2 +-
> > > > > drivers/soc/mediatek/mt8183-mmsys.h | 2 +-
> > > > > drivers/soc/mediatek/mt8186-mmsys.h | 4 +-
> > > > > drivers/soc/mediatek/mt8192-mmsys.h | 4 +-
> > > > > drivers/soc/mediatek/mt8195-mmsys.h | 370
> > > > > ++++++++++++++++++++
> > > > > drivers/soc/mediatek/mt8365-mmsys.h | 4 +-
> > > > > drivers/soc/mediatek/mtk-mmsys.c | 62 ++++
> > > > > drivers/soc/mediatek/mtk-mmsys.h | 1 +
> > > > > drivers/soc/mediatek/mtk-mutex.c | 8 +-
> > > > > include/linux/soc/mediatek/mtk-mmsys.h | 13 +-
> > > > > 12 files changed, 461 insertions(+), 17 deletions(-)
> > > > > create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
> > > > >
> > > >
> > > > [snip]
> > > >
> > > > > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > > > > b/drivers/soc/mediatek/mtk-mmsys.c
> > > > > index 4fc4c2c9ea20..b2fa239c5f5f 100644
> > > > > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > > > > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > > > > @@ -4,6 +4,8 @@
> > > > > * Author: James Liao <jamesjj.liao@mediatek.com>
> > > > > */
> > > > >
>
> ..snip..
>
> > >
> > > I think there might be another chip that needs to get driver data
> > > by
> > > clk_name .
> > > So I use "clk-mt8195" in clk_driver to identify the corresponding
> > > platform whose clk_name of mmsys is also "cfg_vod0".
> >
> > We usually don't care the future because the future may not happen.
> > If
>
> Hello CK,
>
> I'm sorry, but I really have to disagree here.
> Sure, the future may not happen, but from what I can see, MediaTek's
> commitment
> on upstreaming their SoCs is continuative and they care about the
> future.
>
> Let's also not forget that these drivers are not on a downstream
> tree, where
> you don't care about the past or the future, but on upstream, where
> you:
> - Definitely care about the past
> - Should care about the future, if you want to avoid commit noise and
> making big changes to your drivers everytime, which would slow
> down
> your upstreaming due to reviewers having to put 3x efforts on each
> iteration.
>
> And let's also not forget that this being upstream means that these
> drivers
> may (or may not) be extended even by passionate community developers,
> for
> which, having such mechanisms there for other SoCs that MediaTek
> didn't try
> to upstream yet can only be good - and when these are engineered with
> a
> certain flexibility, while keeping the codebase solid, that can only
> be good.
>
> Besides, if I've misunderstood your "don't care the future"
> statement,
> pretend that I've never replied.
OK, let's break this patch into two patches. The first is to support
mt8195 only with clock name identification. The second patch is to
identify SoC. In this series, we just need the first patch, so move the
second patch to the series of another SoC with multiple mmsys device.
Maybe another SoC with multiple mmsys device has new property which
could be used to identify SoC, so we have no information about what is
the better implementation of second patch. I do really care the future,
but I have no information about the future. Please public any hidden
information so we could have better decision.
Regards,
CK
>
>
> > it's sure that would happen, I think clk_driver is not a good
> > choice.
> > For now, the clk_driver name is different for each SoC, but it
> > could be
> > the same for each SoC because only one clock driver would be
> > compiled.
> > I think "compatible" would be different for each SoC.
> >
>
> ...but I agree on that one (and I gave my own review and suggestions
> on
> how to improve that situation).
>
> Regards,
> Angelo
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [RESEND v17 3/7] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
@ 2022-04-12 6:33 ` CK Hu
0 siblings, 0 replies; 49+ messages in thread
From: CK Hu @ 2022-04-12 6:33 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Jason-JH Lin, Rob Herring,
Matthias Brugger, Chun-Kuang Hu
Cc: David Airlie, singo.chang, Alexandre Torgue, postmaster,
Fabien Parent, John 'Warthog9' Hawley, linux-stm32,
roy-cw.yeh, Project_Global_Chrome_Upstream_Group, Philipp Zabel,
devicetree, Daniel Vetter, nancy.lin, linux-mediatek, hsinyi,
linux-arm-kernel, linux-kernel, moudy.ho, Maxime Coquelin
Hi, Angelo:
On Fri, 2022-04-08 at 10:49 +0200, AngeloGioacchino Del Regno wrote:
> Il 08/04/22 03:28, CK Hu ha scritto:
> > Hi, Jason:
> >
> > On Thu, 2022-04-07 at 14:27 +0800, Jason-JH Lin wrote:
> > > Hi CK,
> > >
> > > Thanks for the reviews.
> > >
> > > On Thu, 2022-04-07 at 13:45 +0800, CK Hu wrote:
> > > > Hi, Jason:
> > > >
> > > > On Thu, 2022-04-07 at 11:04 +0800, jason-jh.lin wrote:
> > > > > 1. Add mt8195 mmsys compatible for vdosys0.
> > > > > 2. Add mt8195 routing table settings and fix build fail.
> > > > > 3. Add clock name, clock driver name and routing table into
> > > > > the
> > > > > driver data
> > > > > of mt8195 vdosys0.
> > > > > 4. Add get match data by clock name function and clock
> > > > > platform
> > > > > labels
> > > > > to identify which mmsys node is corresponding to vdosys0.
> > > > >
> > > > > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > > > > ---
> > > > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
> > > > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 6 +-
> > > > > drivers/soc/mediatek/mt8167-mmsys.h | 2 +-
> > > > > drivers/soc/mediatek/mt8183-mmsys.h | 2 +-
> > > > > drivers/soc/mediatek/mt8186-mmsys.h | 4 +-
> > > > > drivers/soc/mediatek/mt8192-mmsys.h | 4 +-
> > > > > drivers/soc/mediatek/mt8195-mmsys.h | 370
> > > > > ++++++++++++++++++++
> > > > > drivers/soc/mediatek/mt8365-mmsys.h | 4 +-
> > > > > drivers/soc/mediatek/mtk-mmsys.c | 62 ++++
> > > > > drivers/soc/mediatek/mtk-mmsys.h | 1 +
> > > > > drivers/soc/mediatek/mtk-mutex.c | 8 +-
> > > > > include/linux/soc/mediatek/mtk-mmsys.h | 13 +-
> > > > > 12 files changed, 461 insertions(+), 17 deletions(-)
> > > > > create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
> > > > >
> > > >
> > > > [snip]
> > > >
> > > > > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > > > > b/drivers/soc/mediatek/mtk-mmsys.c
> > > > > index 4fc4c2c9ea20..b2fa239c5f5f 100644
> > > > > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > > > > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > > > > @@ -4,6 +4,8 @@
> > > > > * Author: James Liao <jamesjj.liao@mediatek.com>
> > > > > */
> > > > >
>
> ..snip..
>
> > >
> > > I think there might be another chip that needs to get driver data
> > > by
> > > clk_name .
> > > So I use "clk-mt8195" in clk_driver to identify the corresponding
> > > platform whose clk_name of mmsys is also "cfg_vod0".
> >
> > We usually don't care the future because the future may not happen.
> > If
>
> Hello CK,
>
> I'm sorry, but I really have to disagree here.
> Sure, the future may not happen, but from what I can see, MediaTek's
> commitment
> on upstreaming their SoCs is continuative and they care about the
> future.
>
> Let's also not forget that these drivers are not on a downstream
> tree, where
> you don't care about the past or the future, but on upstream, where
> you:
> - Definitely care about the past
> - Should care about the future, if you want to avoid commit noise and
> making big changes to your drivers everytime, which would slow
> down
> your upstreaming due to reviewers having to put 3x efforts on each
> iteration.
>
> And let's also not forget that this being upstream means that these
> drivers
> may (or may not) be extended even by passionate community developers,
> for
> which, having such mechanisms there for other SoCs that MediaTek
> didn't try
> to upstream yet can only be good - and when these are engineered with
> a
> certain flexibility, while keeping the codebase solid, that can only
> be good.
>
> Besides, if I've misunderstood your "don't care the future"
> statement,
> pretend that I've never replied.
OK, let's break this patch into two patches. The first is to support
mt8195 only with clock name identification. The second patch is to
identify SoC. In this series, we just need the first patch, so move the
second patch to the series of another SoC with multiple mmsys device.
Maybe another SoC with multiple mmsys device has new property which
could be used to identify SoC, so we have no information about what is
the better implementation of second patch. I do really care the future,
but I have no information about the future. Please public any hidden
information so we could have better decision.
Regards,
CK
>
>
> > it's sure that would happen, I think clk_driver is not a good
> > choice.
> > For now, the clk_driver name is different for each SoC, but it
> > could be
> > the same for each SoC because only one clock driver would be
> > compiled.
> > I think "compatible" would be different for each SoC.
> >
>
> ...but I agree on that one (and I gave my own review and suggestions
> on
> how to improve that situation).
>
> Regards,
> Angelo
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [RESEND v17 3/7] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
@ 2022-04-12 6:33 ` CK Hu
0 siblings, 0 replies; 49+ messages in thread
From: CK Hu @ 2022-04-12 6:33 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Jason-JH Lin, Rob Herring,
Matthias Brugger, Chun-Kuang Hu
Cc: David Airlie, singo.chang, Alexandre Torgue, postmaster,
Fabien Parent, John 'Warthog9' Hawley, linux-stm32,
roy-cw.yeh, Project_Global_Chrome_Upstream_Group, Philipp Zabel,
devicetree, Daniel Vetter, nancy.lin, linux-mediatek, hsinyi,
linux-arm-kernel, linux-kernel, moudy.ho, Maxime Coquelin
Hi, Angelo:
On Fri, 2022-04-08 at 10:49 +0200, AngeloGioacchino Del Regno wrote:
> Il 08/04/22 03:28, CK Hu ha scritto:
> > Hi, Jason:
> >
> > On Thu, 2022-04-07 at 14:27 +0800, Jason-JH Lin wrote:
> > > Hi CK,
> > >
> > > Thanks for the reviews.
> > >
> > > On Thu, 2022-04-07 at 13:45 +0800, CK Hu wrote:
> > > > Hi, Jason:
> > > >
> > > > On Thu, 2022-04-07 at 11:04 +0800, jason-jh.lin wrote:
> > > > > 1. Add mt8195 mmsys compatible for vdosys0.
> > > > > 2. Add mt8195 routing table settings and fix build fail.
> > > > > 3. Add clock name, clock driver name and routing table into
> > > > > the
> > > > > driver data
> > > > > of mt8195 vdosys0.
> > > > > 4. Add get match data by clock name function and clock
> > > > > platform
> > > > > labels
> > > > > to identify which mmsys node is corresponding to vdosys0.
> > > > >
> > > > > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > > > > ---
> > > > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
> > > > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 6 +-
> > > > > drivers/soc/mediatek/mt8167-mmsys.h | 2 +-
> > > > > drivers/soc/mediatek/mt8183-mmsys.h | 2 +-
> > > > > drivers/soc/mediatek/mt8186-mmsys.h | 4 +-
> > > > > drivers/soc/mediatek/mt8192-mmsys.h | 4 +-
> > > > > drivers/soc/mediatek/mt8195-mmsys.h | 370
> > > > > ++++++++++++++++++++
> > > > > drivers/soc/mediatek/mt8365-mmsys.h | 4 +-
> > > > > drivers/soc/mediatek/mtk-mmsys.c | 62 ++++
> > > > > drivers/soc/mediatek/mtk-mmsys.h | 1 +
> > > > > drivers/soc/mediatek/mtk-mutex.c | 8 +-
> > > > > include/linux/soc/mediatek/mtk-mmsys.h | 13 +-
> > > > > 12 files changed, 461 insertions(+), 17 deletions(-)
> > > > > create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
> > > > >
> > > >
> > > > [snip]
> > > >
> > > > > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > > > > b/drivers/soc/mediatek/mtk-mmsys.c
> > > > > index 4fc4c2c9ea20..b2fa239c5f5f 100644
> > > > > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > > > > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > > > > @@ -4,6 +4,8 @@
> > > > > * Author: James Liao <jamesjj.liao@mediatek.com>
> > > > > */
> > > > >
>
> ..snip..
>
> > >
> > > I think there might be another chip that needs to get driver data
> > > by
> > > clk_name .
> > > So I use "clk-mt8195" in clk_driver to identify the corresponding
> > > platform whose clk_name of mmsys is also "cfg_vod0".
> >
> > We usually don't care the future because the future may not happen.
> > If
>
> Hello CK,
>
> I'm sorry, but I really have to disagree here.
> Sure, the future may not happen, but from what I can see, MediaTek's
> commitment
> on upstreaming their SoCs is continuative and they care about the
> future.
>
> Let's also not forget that these drivers are not on a downstream
> tree, where
> you don't care about the past or the future, but on upstream, where
> you:
> - Definitely care about the past
> - Should care about the future, if you want to avoid commit noise and
> making big changes to your drivers everytime, which would slow
> down
> your upstreaming due to reviewers having to put 3x efforts on each
> iteration.
>
> And let's also not forget that this being upstream means that these
> drivers
> may (or may not) be extended even by passionate community developers,
> for
> which, having such mechanisms there for other SoCs that MediaTek
> didn't try
> to upstream yet can only be good - and when these are engineered with
> a
> certain flexibility, while keeping the codebase solid, that can only
> be good.
>
> Besides, if I've misunderstood your "don't care the future"
> statement,
> pretend that I've never replied.
OK, let's break this patch into two patches. The first is to support
mt8195 only with clock name identification. The second patch is to
identify SoC. In this series, we just need the first patch, so move the
second patch to the series of another SoC with multiple mmsys device.
Maybe another SoC with multiple mmsys device has new property which
could be used to identify SoC, so we have no information about what is
the better implementation of second patch. I do really care the future,
but I have no information about the future. Please public any hidden
information so we could have better decision.
Regards,
CK
>
>
> > it's sure that would happen, I think clk_driver is not a good
> > choice.
> > For now, the clk_driver name is different for each SoC, but it
> > could be
> > the same for each SoC because only one clock driver would be
> > compiled.
> > I think "compatible" would be different for each SoC.
> >
>
> ...but I agree on that one (and I gave my own review and suggestions
> on
> how to improve that situation).
>
> Regards,
> Angelo
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^ permalink raw reply [flat|nested] 49+ messages in thread
end of thread, other threads:[~2022-04-12 6:34 UTC | newest]
Thread overview: 49+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-04-07 3:04 [RESEND v17 0/7] Add Mediatek Soc DRM (vdosys0) support for mt8195 jason-jh.lin
2022-04-07 3:04 ` jason-jh.lin
2022-04-07 3:04 ` [RESEND v17 1/7] dt-bindings: arm: mediatek: mmsys: add power and gce properties jason-jh.lin
2022-04-07 3:04 ` jason-jh.lin
2022-04-07 3:04 ` [RESEND v17 2/7] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding jason-jh.lin
2022-04-07 3:04 ` jason-jh.lin
2022-04-07 5:12 ` CK Hu
2022-04-07 5:12 ` CK Hu
2022-04-07 8:30 ` AngeloGioacchino Del Regno
2022-04-07 8:30 ` AngeloGioacchino Del Regno
2022-04-07 8:30 ` AngeloGioacchino Del Regno
2022-04-07 3:04 ` [RESEND v17 3/7] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0 jason-jh.lin
2022-04-07 3:04 ` jason-jh.lin
2022-04-07 5:45 ` CK Hu
2022-04-07 5:45 ` CK Hu
2022-04-07 6:27 ` Jason-JH Lin
2022-04-07 6:27 ` Jason-JH Lin
2022-04-07 6:27 ` Jason-JH Lin
2022-04-08 1:28 ` CK Hu
2022-04-08 1:28 ` CK Hu
2022-04-08 1:28 ` CK Hu
2022-04-08 8:49 ` AngeloGioacchino Del Regno
2022-04-08 8:49 ` AngeloGioacchino Del Regno
2022-04-08 8:49 ` AngeloGioacchino Del Regno
2022-04-12 6:33 ` CK Hu
2022-04-12 6:33 ` CK Hu
2022-04-12 6:33 ` CK Hu
2022-04-07 5:58 ` CK Hu
2022-04-07 5:58 ` CK Hu
2022-04-08 1:42 ` Jason-JH Lin
2022-04-08 1:42 ` Jason-JH Lin
2022-04-08 1:42 ` Jason-JH Lin
2022-04-07 9:11 ` AngeloGioacchino Del Regno
2022-04-07 9:11 ` AngeloGioacchino Del Regno
2022-04-07 9:11 ` AngeloGioacchino Del Regno
2022-04-08 2:42 ` Jason-JH Lin
2022-04-08 2:42 ` Jason-JH Lin
2022-04-08 2:42 ` Jason-JH Lin
2022-04-08 8:34 ` AngeloGioacchino Del Regno
2022-04-08 8:34 ` AngeloGioacchino Del Regno
2022-04-08 8:34 ` AngeloGioacchino Del Regno
2022-04-07 3:04 ` [RESEND v17 4/7] soc: mediatek: add mtk-mutex " jason-jh.lin
2022-04-07 3:04 ` jason-jh.lin
2022-04-07 3:04 ` [RESEND v17 5/7] drm/mediatek: add DSC support for mediatek-drm jason-jh.lin
2022-04-07 3:04 ` jason-jh.lin
2022-04-07 3:04 ` [RESEND v17 6/7] drm/mediatek: add MERGE " jason-jh.lin
2022-04-07 3:04 ` jason-jh.lin
2022-04-07 3:04 ` [RESEND v17 7/7] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195 jason-jh.lin
2022-04-07 3:04 ` jason-jh.lin
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