From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A5941C433EF for ; Thu, 7 Apr 2022 10:19:34 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 08B9F83DA9; Thu, 7 Apr 2022 12:19:10 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="pJkBpeqF"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id DF722838AB; Thu, 7 Apr 2022 12:17:56 +0200 (CEST) Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 1989E83CAC for ; Thu, 7 Apr 2022 12:17:44 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 87EF561D50; Thu, 7 Apr 2022 10:17:42 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 90501C385AD; Thu, 7 Apr 2022 10:17:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1649326661; bh=z0DQSVLw9hq3Z1K3EYHO7migbrZpYoPjtANIB9MDKFI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pJkBpeqFq1hICN0mvEFc/D0x/Kux+aESkUSh1cWIKmd+dSA34retKh/lvSuRg9poy XeRZ2qE2YXd+qrNUhxB00pDa4ib81mS1zHyB/z89x8VDJeP4oQw3fQi5r7/BqeiHpz f0Uo5VXTdaTYyNAZnhHlQPpvxf+d83jvkA0u9vv4XANtgmOwqnbRoZnZsn+DbcVBb8 8JO80Mchyjrm+zbFcTQxz+qbYV8/nvFedkj7Jm2edXSOUP/IxxXSUB7dlAsj6PFzwS Od/zfwX878Um3KFjhf6HRaU8qzns4BaKuurGM/Rh+ThFaITLAmZ68JOJ7PLhkcg1PH RX9uynoMYOfZQ== Received: by pali.im (Postfix) id 495A2B6E; Thu, 7 Apr 2022 12:17:41 +0200 (CEST) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: Priyanka Jain , Qiang Zhao , Shengzhou Liu , Sinan Akman Cc: u-boot@lists.denx.de Subject: [PATCH 09/11] board: freescale: p1_p2_rdb_pc: Define SW macros for lower and upper NOR banks Date: Thu, 7 Apr 2022 12:16:22 +0200 Message-Id: <20220407101624.15850-10-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220407101624.15850-1-pali@kernel.org> References: <20220407101624.15850-1-pali@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Replace hardcoded i2c hex values for NOR banks by named SW macros in map_lowernorbank/map_uppernorbank env commands. Signed-off-by: Pali Rohár --- include/configs/p1_p2_rdb_pc.h | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index cb3b1a1da05d..995bd983cef1 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -22,6 +22,9 @@ #define __SW_BOOT_SD 0x9c #define __SW_BOOT_NAND 0xec #define __SW_BOOT_PCIE 0x6c +#define __SW_NOR_BANK_MASK 0xfd +#define __SW_NOR_BANK_UP 0x00 +#define __SW_NOR_BANK_LO 0x02 #define CONFIG_SYS_L2_SIZE (256 << 10) #endif @@ -48,6 +51,9 @@ #define __SW_BOOT_SD 0x24 #define __SW_BOOT_NAND 0x44 #define __SW_BOOT_PCIE 0x74 +#define __SW_NOR_BANK_MASK 0xfd +#define __SW_NOR_BANK_UP 0x00 +#define __SW_NOR_BANK_LO 0x02 #define CONFIG_SYS_L2_SIZE (256 << 10) /* * Dynamic MTD Partition support with mtdparts @@ -64,6 +70,9 @@ #define __SW_BOOT_SD2 0x18 #define __SW_BOOT_NAND 0xe8 #define __SW_BOOT_PCIE 0xa8 +#define __SW_NOR_BANK_MASK 0xfd +#define __SW_NOR_BANK_UP 0x00 +#define __SW_NOR_BANK_LO 0x02 #define CONFIG_SYS_L2_SIZE (512 << 10) /* * Dynamic MTD Partition support with mtdparts @@ -617,8 +626,8 @@ i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset "nandfdtaddr=80000\0" \ "ramdisk_size=120000\0" \ __VSCFW_ADDR \ -"map_lowernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 02 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 fd 1\0" \ -"map_uppernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 00 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 fd 1\0" \ +"map_lowernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_LO)" 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 "__stringify(__SW_NOR_BANK_MASK)" 1\0" \ +"map_uppernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_UP)" 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 "__stringify(__SW_NOR_BANK_MASK)" 1\0" \ __stringify(__NOR_RST_CMD)"\0" \ __stringify(__SPI_RST_CMD)"\0" \ __stringify(__SD_RST_CMD)"\0" \ -- 2.20.1