From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9D26EC433F5 for ; Thu, 7 Apr 2022 10:19:00 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 24ED283CD8; Thu, 7 Apr 2022 12:18:44 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="uvQlOM9j"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id B8CA1803C8; Thu, 7 Apr 2022 12:17:52 +0200 (CEST) Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id C694E83C8F for ; Thu, 7 Apr 2022 12:17:43 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 7B449B82718; Thu, 7 Apr 2022 10:17:43 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id F1F58C385A0; Thu, 7 Apr 2022 10:17:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1649326662; bh=w7vGwJSL8szfJBtVsZ+XPyh2BjylUyF2BBuI4D+D/dU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=uvQlOM9jz00Zmz+gaQxsXDRvnhtlC1QbtDNaHOY6Hc/XNTf2TDM+HN3rGLxFThTWX zRmi41uFlviQ20LGKOgh4oLKO8eK0eUg8koBuE6lUYMaToWgPAlReYl/cL04regeTN 9ggMDNPstBosxNjwkm63U6kJJAq75DHeSnupa3eKczs+lUk//KSqaPe4iEWGUmb060 D5nlmZ7fgXJ4RVY6EwRwmlQWJlP3o26aNSRp4GwuIxx02aHABZa0BIhVKwDqbmVvX2 LaW6tPCq9QqSYlGxsjcYS0vkO5s9nLNa0SVrhcZO7gfLW4ArT432nVbund3o4HItH9 CmV3CW0TAM5ug== Received: by pali.im (Postfix) id AC19DB91; Thu, 7 Apr 2022 12:17:41 +0200 (CEST) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: Priyanka Jain , Qiang Zhao , Shengzhou Liu , Sinan Akman Cc: u-boot@lists.denx.de Subject: [PATCH 10/11] board: freescale: p1_p2_rdb_pc: Move BootROM change source macros to p1_p2_bootrom.h Date: Thu, 7 Apr 2022 12:16:23 +0200 Message-Id: <20220407101624.15850-11-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220407101624.15850-1-pali@kernel.org> References: <20220407101624.15850-1-pali@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Code for changing BootROM source is platform generic and can be used by any P1* and P2* compatible board. Not only by RDB boards which use config header file p1_p2_rdb_pc.h. So move this code from p1_p2_rdb_pc.h to p1_p2_bootrom.h and cleanup macros for generating boot source env variables in CONFIG_EXTRA_ENV_SETTINGS. This allows to use code for changing BootROM source also by other boards in future. Signed-off-by: Pali Rohár --- include/configs/p1_p2_bootrom.h | 32 +++++++++++++++ include/configs/p1_p2_rdb_pc.h | 73 +++++++++++++++++++++------------ 2 files changed, 78 insertions(+), 27 deletions(-) create mode 100644 include/configs/p1_p2_bootrom.h diff --git a/include/configs/p1_p2_bootrom.h b/include/configs/p1_p2_bootrom.h new file mode 100644 index 000000000000..a1f61b788cf7 --- /dev/null +++ b/include/configs/p1_p2_bootrom.h @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ +// (C) 2022 Pali Rohár + +#define CHANGE_BOOTROM_SOURCE_CMD(SOURCE, MASK) i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 SOURCE 1; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 MASK 1 + +#ifdef __SW_NOR_BANK_LO +#define CHANGE_BOOTROM_LOWER_NOR_BANK_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_NOR_BANK_LO, __SW_NOR_BANK_MASK) +#endif + +#ifdef __SW_NOR_BANK_UP +#define CHANGE_BOOTROM_UPPER_NOR_BANK_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_NOR_BANK_UP, __SW_NOR_BANK_MASK) +#endif + +#ifdef __SW_BOOT_NOR +#define CHANGE_BOOTROM_SOURCE_DEF_NOR_BANK_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_NOR, __SW_BOOT_MASK) +#endif + +#ifdef __SW_BOOT_SPI +#define CHANGE_BOOTROM_SOURCE_SPI_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_SPI, __SW_BOOT_MASK) +#endif + +#ifdef __SW_BOOT_SD +#define CHANGE_BOOTROM_SOURCE_SD_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_SD, __SW_BOOT_MASK) +#endif + +#ifdef __SW_BOOT_NAND +#define CHANGE_BOOTROM_SOURCE_NAND_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_NAND, __SW_BOOT_MASK) +#endif + +#ifdef __SW_BOOT_PCIE +#define CHANGE_BOOTROM_SOURCE_PCIE_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_PCIE, __SW_BOOT_MASK) +#endif diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 995bd983cef1..d41b31081017 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -79,6 +79,8 @@ */ #endif +#include "p1_p2_bootrom.h" + #ifdef CONFIG_SDCARD #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" @@ -575,30 +577,46 @@ #define CONFIG_BOOTFILE "uImage" #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ -#ifdef __SW_BOOT_NOR -#define __NOR_RST_CMD \ -norboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NOR 1; \ -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset +#ifdef CHANGE_BOOTROM_LOWER_NOR_BANK_CMD +#define __MAP_NOR_LOWER_CMD "map_lowernorbank="__stringify(CHANGE_BOOTROM_LOWER_NOR_BANK_CMD)"\0" +#else +#define __MAP_NOR_LOWER_CMD "" +#endif + +#ifdef CHANGE_BOOTROM_UPPER_NOR_BANK_CMD +#define __MAP_NOR_UPPER_CMD "map_uppernorbank="__stringify(CHANGE_BOOTROM_UPPER_NOR_BANK_CMD)"\0" +#else +#define __MAP_NOR_UPPER_CMD "" +#endif + +#ifdef CHANGE_BOOTROM_SOURCE_DEF_NOR_BANK_CMD +#define __NOR_RST_CMD "norboot="__stringify(CHANGE_BOOTROM_SOURCE_DEF_NOR_BANK_CMD)"; reset\0" +#else +#define __NOR_RST_CMD "" #endif -#ifdef __SW_BOOT_SPI -#define __SPI_RST_CMD \ -spiboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SPI 1; \ -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset + +#ifdef CHANGE_BOOTROM_SOURCE_SPI_CMD +#define __SPI_RST_CMD "spiboot="__stringify(CHANGE_BOOTROM_SOURCE_SPI_CMD)"; reset\0" +#else +#define __SPI_RST_CMD "" #endif -#ifdef __SW_BOOT_SD -#define __SD_RST_CMD \ -sdboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SD 1; \ -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset + +#ifdef CHANGE_BOOTROM_SOURCE_SD_CMD +#define __SD_RST_CMD "sdboot="__stringify(CHANGE_BOOTROM_SOURCE_SD_CMD)"; reset\0" +#else +#define __SD_RST_CMD "" #endif -#ifdef __SW_BOOT_NAND -#define __NAND_RST_CMD \ -nandboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NAND 1; \ -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset + +#ifdef CHANGE_BOOTROM_SOURCE_NAND_CMD +#define __NAND_RST_CMD "nandboot="__stringify(CHANGE_BOOTROM_SOURCE_NAND_CMD)"; reset\0" +#else +#define __NAND_RST_CMD "" #endif -#ifdef __SW_BOOT_PCIE -#define __PCIE_RST_CMD \ -pciboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_PCIE 1; \ -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset + +#ifdef CHANGE_BOOTROM_SOURCE_PCIE_CMD +#define __PCIE_RST_CMD "pciboot="__stringify(CHANGE_BOOTROM_SOURCE_PCIE_CMD)"; reset\0" +#else +#define __PCIE_RST_CMD "" #endif #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -626,13 +644,14 @@ i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset "nandfdtaddr=80000\0" \ "ramdisk_size=120000\0" \ __VSCFW_ADDR \ -"map_lowernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_LO)" 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 "__stringify(__SW_NOR_BANK_MASK)" 1\0" \ -"map_uppernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_UP)" 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 "__stringify(__SW_NOR_BANK_MASK)" 1\0" \ -__stringify(__NOR_RST_CMD)"\0" \ -__stringify(__SPI_RST_CMD)"\0" \ -__stringify(__SD_RST_CMD)"\0" \ -__stringify(__NAND_RST_CMD)"\0" \ -__stringify(__PCIE_RST_CMD)"\0" +__MAP_NOR_LOWER_CMD \ +__MAP_NOR_UPPER_CMD \ +__NOR_RST_CMD \ +__SPI_RST_CMD \ +__SD_RST_CMD \ +__NAND_RST_CMD \ +__PCIE_RST_CMD \ +"" #define CONFIG_USB_FAT_BOOT \ "setenv bootargs root=/dev/ram rw " \ -- 2.20.1