From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 702FFC433EF for ; Thu, 7 Apr 2022 10:19:55 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id B103983DBA; Thu, 7 Apr 2022 12:19:18 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="nc0uKC5f"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id CB04183D0D; Thu, 7 Apr 2022 12:18:02 +0200 (CEST) Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 323A983CA3 for ; Thu, 7 Apr 2022 12:17:44 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id DD0A161D5C; Thu, 7 Apr 2022 10:17:42 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5A465C385A6; Thu, 7 Apr 2022 10:17:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1649326662; bh=7TBF4JCI3KATJaNowAAEZCuRdgiWhvnhJDRXrseApvc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nc0uKC5fKU+Balwd2nxu+hlI8CQ5kTJpz4iOasCqPmEAoWw/Acl3rPlhcKLLZ7JqM OJUvcwfZv0nzpCdTWmWqvY6L9qILXzdO6GtXsgGXaxRiKTyOeJICy4PFLcxqE826dL 58mTSe6syMtS6ifKgqC26Yq1O4C3Bent72en83bi14uzJuEp5ienyX/mH4TZjFl53I i86MetPuQRcycpkwVrpIb0tgojUgg3UASbhPQvQPsFZnLkhZkrVE1NLwlwaWKM1ejD aUtq5qHtwPVEIEOeNI0cIvAV7Tl6psgKHb6+EO8wZEV6DyIIZeGXlJQdcmEcjWnCR0 EMntjLjBU0/MA== Received: by pali.im (Postfix) id 131E7B6E; Thu, 7 Apr 2022 12:17:42 +0200 (CEST) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: Priyanka Jain , Qiang Zhao , Shengzhou Liu , Sinan Akman Cc: u-boot@lists.denx.de Subject: [PATCH 11/11] board: freescale: p1_p2_rdb_pc: Add env commands norlowerboot, norupperboot, sd2boot and defboot Date: Thu, 7 Apr 2022 12:16:24 +0200 Message-Id: <20220407101624.15850-12-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220407101624.15850-1-pali@kernel.org> References: <20220407101624.15850-1-pali@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean All *boot env commands overrides default BootROM boot location via i2c. BootROM then starts booting U-Boot from this specified location instead of the default one. Add new env command defboot which reverts BootROM boot location to the default value, which in most cases is configurable by HW DIP switches. And add new env commands norlowerboot, norupperboot, sd2boot to boot from other locations. norlowerboot would instruct BootROM to boot from lower NOR bank, norupperboot from upper NOR bank and sd2boot from SD card with alternative configuration. Signed-off-by: Pali Rohár --- include/configs/p1_p2_bootrom.h | 14 +++++++++++++ include/configs/p1_p2_rdb_pc.h | 37 +++++++++++++++++++++++++++++++++ 2 files changed, 51 insertions(+) diff --git a/include/configs/p1_p2_bootrom.h b/include/configs/p1_p2_bootrom.h index a1f61b788cf7..d1e91049606b 100644 --- a/include/configs/p1_p2_bootrom.h +++ b/include/configs/p1_p2_bootrom.h @@ -15,6 +15,14 @@ #define CHANGE_BOOTROM_SOURCE_DEF_NOR_BANK_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_NOR, __SW_BOOT_MASK) #endif +#ifdef __SW_BOOT_NOR_BANK_LO +#define CHANGE_BOOTROM_SOURCE_LOWER_NOR_BANK_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_NOR_BANK_LO, __SW_BOOT_NOR_BANK_MASK) +#endif + +#ifdef __SW_BOOT_NOR_BANK_UP +#define CHANGE_BOOTROM_SOURCE_UPPER_NOR_BANK_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_NOR_BANK_UP, __SW_BOOT_NOR_BANK_MASK) +#endif + #ifdef __SW_BOOT_SPI #define CHANGE_BOOTROM_SOURCE_SPI_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_SPI, __SW_BOOT_MASK) #endif @@ -23,6 +31,10 @@ #define CHANGE_BOOTROM_SOURCE_SD_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_SD, __SW_BOOT_MASK) #endif +#ifdef __SW_BOOT_SD2 +#define CHANGE_BOOTROM_SOURCE_SD2_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_SD2, __SW_BOOT_MASK) +#endif + #ifdef __SW_BOOT_NAND #define CHANGE_BOOTROM_SOURCE_NAND_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_NAND, __SW_BOOT_MASK) #endif @@ -30,3 +42,5 @@ #ifdef __SW_BOOT_PCIE #define CHANGE_BOOTROM_SOURCE_PCIE_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_PCIE, __SW_BOOT_MASK) #endif + +#define CHANGE_BOOTROM_SOURCE_DEF_CMD CHANGE_BOOTROM_SOURCE_CMD(0x00, 0xff) diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index d41b31081017..ac8199a88aa0 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -25,6 +25,9 @@ #define __SW_NOR_BANK_MASK 0xfd #define __SW_NOR_BANK_UP 0x00 #define __SW_NOR_BANK_LO 0x02 +#define __SW_BOOT_NOR_BANK_UP 0x5c /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */ +#define __SW_BOOT_NOR_BANK_LO 0x5e /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */ +#define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */ #define CONFIG_SYS_L2_SIZE (256 << 10) #endif @@ -54,6 +57,9 @@ #define __SW_NOR_BANK_MASK 0xfd #define __SW_NOR_BANK_UP 0x00 #define __SW_NOR_BANK_LO 0x02 +#define __SW_BOOT_NOR_BANK_UP 0x64 /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */ +#define __SW_BOOT_NOR_BANK_LO 0x66 /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */ +#define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */ #define CONFIG_SYS_L2_SIZE (256 << 10) /* * Dynamic MTD Partition support with mtdparts @@ -73,6 +79,9 @@ #define __SW_NOR_BANK_MASK 0xfd #define __SW_NOR_BANK_UP 0x00 #define __SW_NOR_BANK_LO 0x02 +#define __SW_BOOT_NOR_BANK_UP 0xc8 /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */ +#define __SW_BOOT_NOR_BANK_LO 0xca /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */ +#define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */ #define CONFIG_SYS_L2_SIZE (512 << 10) /* * Dynamic MTD Partition support with mtdparts @@ -595,6 +604,18 @@ #define __NOR_RST_CMD "" #endif +#ifdef CHANGE_BOOTROM_SOURCE_LOWER_NOR_BANK_CMD +#define __NOR_LOWER_RST_CMD "norlowerboot="__stringify(CHANGE_BOOTROM_SOURCE_LOWER_NOR_BANK_CMD)"; reset\0" +#else +#define __NOR_LOWER_RST_CMD "" +#endif + +#ifdef CHANGE_BOOTROM_SOURCE_UPPER_NOR_BANK_CMD +#define __NOR_UPPER_RST_CMD "norupperboot="__stringify(CHANGE_BOOTROM_SOURCE_UPPER_NOR_BANK_CMD)"; reset\0" +#else +#define __NOR_UPPER_RST_CMD "" +#endif + #ifdef CHANGE_BOOTROM_SOURCE_SPI_CMD #define __SPI_RST_CMD "spiboot="__stringify(CHANGE_BOOTROM_SOURCE_SPI_CMD)"; reset\0" #else @@ -607,6 +628,12 @@ #define __SD_RST_CMD "" #endif +#ifdef CHANGE_BOOTROM_SOURCE_SD2_CMD +#define __SD2_RST_CMD "sd2boot="__stringify(CHANGE_BOOTROM_SOURCE_SD2_CMD)"; reset\0" +#else +#define __SD2_RST_CMD "" +#endif + #ifdef CHANGE_BOOTROM_SOURCE_NAND_CMD #define __NAND_RST_CMD "nandboot="__stringify(CHANGE_BOOTROM_SOURCE_NAND_CMD)"; reset\0" #else @@ -619,6 +646,12 @@ #define __PCIE_RST_CMD "" #endif +#ifdef CHANGE_BOOTROM_SOURCE_DEF_CMD +#define __DEF_RST_CMD "defboot="__stringify(CHANGE_BOOTROM_SOURCE_DEF_CMD)"; reset\0" +#else +#define __DEF_RST_CMD "" +#endif + #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ @@ -647,10 +680,14 @@ __VSCFW_ADDR \ __MAP_NOR_LOWER_CMD \ __MAP_NOR_UPPER_CMD \ __NOR_RST_CMD \ +__NOR_LOWER_RST_CMD \ +__NOR_UPPER_RST_CMD \ __SPI_RST_CMD \ __SD_RST_CMD \ +__SD2_RST_CMD \ __NAND_RST_CMD \ __PCIE_RST_CMD \ +__DEF_RST_CMD \ "" #define CONFIG_USB_FAT_BOOT \ -- 2.20.1