* [PATCH 1/2] arm64: dts: imx8mp: Add missing speed grade phandle
@ 2022-03-11 17:23 Marek Vasut
2022-03-11 17:23 ` [PATCH 2/2] arm64: dts: imx8mp: Add cpu-freq support Marek Vasut
2022-04-09 3:49 ` [PATCH 1/2] arm64: dts: imx8mp: Add missing speed grade phandle Shawn Guo
0 siblings, 2 replies; 3+ messages in thread
From: Marek Vasut @ 2022-03-11 17:23 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Marek Vasut, Anson Huang, Fabio Estevam, Peng Fan, Shawn Guo,
NXP Linux Team
And missing speed grade phandle to cpu@0 node.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Anson Huang <Anson.Huang@nxp.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: NXP Linux Team <linux-imx@nxp.com>
To: linux-arm-kernel@lists.infradead.org
---
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 3f8703f3ba5b0..077ade2b1b0c4 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -58,6 +58,8 @@ A53_0: cpu@0 {
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>;
+ nvmem-cells = <&cpu_speed_grade>;
+ nvmem-cell-names = "speed_grade";
#cooling-cells = <2>;
};
--
2.34.1
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^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH 2/2] arm64: dts: imx8mp: Add cpu-freq support
2022-03-11 17:23 [PATCH 1/2] arm64: dts: imx8mp: Add missing speed grade phandle Marek Vasut
@ 2022-03-11 17:23 ` Marek Vasut
2022-04-09 3:49 ` [PATCH 1/2] arm64: dts: imx8mp: Add missing speed grade phandle Shawn Guo
1 sibling, 0 replies; 3+ messages in thread
From: Marek Vasut @ 2022-03-11 17:23 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Marek Vasut, Anson Huang, Fabio Estevam, Peng Fan, Shawn Guo,
NXP Linux Team
Add A53 OPP table and cpu regulator to support cpu-freq driver.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Anson Huang <Anson.Huang@nxp.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: NXP Linux Team <linux-imx@nxp.com>
To: linux-arm-kernel@lists.infradead.org
---
Note: the commit message is partly copied from MX8MN
---
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 33 +++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 077ade2b1b0c4..89f4005beecb2 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -60,6 +60,7 @@ A53_0: cpu@0 {
next-level-cache = <&A53_L2>;
nvmem-cells = <&cpu_speed_grade>;
nvmem-cell-names = "speed_grade";
+ operating-points-v2 = <&a53_opp_table>;
#cooling-cells = <2>;
};
@@ -77,6 +78,7 @@ A53_1: cpu@1 {
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>;
+ operating-points-v2 = <&a53_opp_table>;
#cooling-cells = <2>;
};
@@ -94,6 +96,7 @@ A53_2: cpu@2 {
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>;
+ operating-points-v2 = <&a53_opp_table>;
#cooling-cells = <2>;
};
@@ -111,6 +114,7 @@ A53_3: cpu@3 {
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>;
+ operating-points-v2 = <&a53_opp_table>;
#cooling-cells = <2>;
};
@@ -123,6 +127,35 @@ A53_L2: l2-cache0 {
};
};
+ a53_opp_table: opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <850000>;
+ opp-supported-hw = <0x8a0>, <0x7>;
+ clock-latency-ns = <150000>;
+ opp-suspend;
+ };
+
+ opp-1600000000 {
+ opp-hz = /bits/ 64 <1600000000>;
+ opp-microvolt = <950000>;
+ opp-supported-hw = <0xa0>, <0x7>;
+ clock-latency-ns = <150000>;
+ opp-suspend;
+ };
+
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <1000000>;
+ opp-supported-hw = <0x20>, <0x3>;
+ clock-latency-ns = <150000>;
+ opp-suspend;
+ };
+ };
+
osc_32k: clock-osc-32k {
compatible = "fixed-clock";
#clock-cells = <0>;
--
2.34.1
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linux-arm-kernel@lists.infradead.org
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^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH 1/2] arm64: dts: imx8mp: Add missing speed grade phandle
2022-03-11 17:23 [PATCH 1/2] arm64: dts: imx8mp: Add missing speed grade phandle Marek Vasut
2022-03-11 17:23 ` [PATCH 2/2] arm64: dts: imx8mp: Add cpu-freq support Marek Vasut
@ 2022-04-09 3:49 ` Shawn Guo
1 sibling, 0 replies; 3+ messages in thread
From: Shawn Guo @ 2022-04-09 3:49 UTC (permalink / raw)
To: Marek Vasut
Cc: linux-arm-kernel, Anson Huang, Fabio Estevam, Peng Fan, NXP Linux Team
On Fri, Mar 11, 2022 at 06:23:51PM +0100, Marek Vasut wrote:
> And missing speed grade phandle to cpu@0 node.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Anson Huang <Anson.Huang@nxp.com>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: NXP Linux Team <linux-imx@nxp.com>
> To: linux-arm-kernel@lists.infradead.org
Applied both, thanks!
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2022-04-09 3:51 UTC | newest]
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2022-03-11 17:23 [PATCH 1/2] arm64: dts: imx8mp: Add missing speed grade phandle Marek Vasut
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2022-04-09 3:49 ` [PATCH 1/2] arm64: dts: imx8mp: Add missing speed grade phandle Shawn Guo
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