* [RFC PATCH v1 1/1] include/hw/pci/pcie_host: Correct PCIE_MMCFG_BUS_MASK
@ 2022-04-11 19:38 Francisco Iglesias
2022-04-11 21:12 ` Michael S. Tsirkin
0 siblings, 1 reply; 3+ messages in thread
From: Francisco Iglesias @ 2022-04-11 19:38 UTC (permalink / raw)
To: qemu-devel; +Cc: frasse.iglesias, mst
According to [1] address bits 27 - 20 are mapped to the bus number (the
TLPs bus number field is 8 bits).
[1] PCI Express® Base Specification Revision 5.0 Version 1.0
Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com>
---
include/hw/pci/pcie_host.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/hw/pci/pcie_host.h b/include/hw/pci/pcie_host.h
index 076457b270..b3c8ce973c 100644
--- a/include/hw/pci/pcie_host.h
+++ b/include/hw/pci/pcie_host.h
@@ -60,7 +60,7 @@ void pcie_host_mmcfg_update(PCIExpressHost *e,
/*
* PCI express ECAM (Enhanced Configuration Address Mapping) format.
* AKA mmcfg address
- * bit 20 - 28: bus number
+ * bit 20 - 27: bus number
* bit 15 - 19: device number
* bit 12 - 14: function number
* bit 0 - 11: offset in configuration space of a given device
@@ -68,7 +68,7 @@ void pcie_host_mmcfg_update(PCIExpressHost *e,
#define PCIE_MMCFG_SIZE_MAX (1ULL << 29)
#define PCIE_MMCFG_SIZE_MIN (1ULL << 20)
#define PCIE_MMCFG_BUS_BIT 20
-#define PCIE_MMCFG_BUS_MASK 0x1ff
+#define PCIE_MMCFG_BUS_MASK 0xff
#define PCIE_MMCFG_DEVFN_BIT 12
#define PCIE_MMCFG_DEVFN_MASK 0xff
#define PCIE_MMCFG_CONFOFFSET_MASK 0xfff
--
2.20.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [RFC PATCH v1 1/1] include/hw/pci/pcie_host: Correct PCIE_MMCFG_BUS_MASK
2022-04-11 19:38 [RFC PATCH v1 1/1] include/hw/pci/pcie_host: Correct PCIE_MMCFG_BUS_MASK Francisco Iglesias
@ 2022-04-11 21:12 ` Michael S. Tsirkin
2022-04-11 22:16 ` Francisco Iglesias
0 siblings, 1 reply; 3+ messages in thread
From: Michael S. Tsirkin @ 2022-04-11 21:12 UTC (permalink / raw)
To: Francisco Iglesias; +Cc: qemu-devel
On Mon, Apr 11, 2022 at 09:38:18PM +0200, Francisco Iglesias wrote:
> According to [1] address bits 27 - 20 are mapped to the bus number (the
> TLPs bus number field is 8 bits).
>
> [1] PCI Express® Base Specification Revision 5.0 Version 1.0
>
> Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com>
> ---
> include/hw/pci/pcie_host.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/include/hw/pci/pcie_host.h b/include/hw/pci/pcie_host.h
> index 076457b270..b3c8ce973c 100644
> --- a/include/hw/pci/pcie_host.h
> +++ b/include/hw/pci/pcie_host.h
> @@ -60,7 +60,7 @@ void pcie_host_mmcfg_update(PCIExpressHost *e,
> /*
> * PCI express ECAM (Enhanced Configuration Address Mapping) format.
> * AKA mmcfg address
> - * bit 20 - 28: bus number
> + * bit 20 - 27: bus number
> * bit 15 - 19: device number
> * bit 12 - 14: function number
> * bit 0 - 11: offset in configuration space of a given device
this is correct, or to be more precise:
A[(20 + n – 1):20] and 1 <= n <= 8
> @@ -68,7 +68,7 @@ void pcie_host_mmcfg_update(PCIExpressHost *e,
> #define PCIE_MMCFG_SIZE_MAX (1ULL << 29)
> #define PCIE_MMCFG_SIZE_MIN (1ULL << 20)
> #define PCIE_MMCFG_BUS_BIT 20
> -#define PCIE_MMCFG_BUS_MASK 0x1ff
> +#define PCIE_MMCFG_BUS_MASK 0xff
> #define PCIE_MMCFG_DEVFN_BIT 12
> #define PCIE_MMCFG_DEVFN_MASK 0xff
> #define PCIE_MMCFG_CONFOFFSET_MASK 0xfff
> --
> 2.20.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [RFC PATCH v1 1/1] include/hw/pci/pcie_host: Correct PCIE_MMCFG_BUS_MASK
2022-04-11 21:12 ` Michael S. Tsirkin
@ 2022-04-11 22:16 ` Francisco Iglesias
0 siblings, 0 replies; 3+ messages in thread
From: Francisco Iglesias @ 2022-04-11 22:16 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: qemu-devel
Hi Michael,
On [2022 Apr 11] Mon 17:12:47, Michael S. Tsirkin wrote:
> On Mon, Apr 11, 2022 at 09:38:18PM +0200, Francisco Iglesias wrote:
> > According to [1] address bits 27 - 20 are mapped to the bus number (the
> > TLPs bus number field is 8 bits).
> >
> > [1] PCI Express® Base Specification Revision 5.0 Version 1.0
> >
> > Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com>
> > ---
> > include/hw/pci/pcie_host.h | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/include/hw/pci/pcie_host.h b/include/hw/pci/pcie_host.h
> > index 076457b270..b3c8ce973c 100644
> > --- a/include/hw/pci/pcie_host.h
> > +++ b/include/hw/pci/pcie_host.h
> > @@ -60,7 +60,7 @@ void pcie_host_mmcfg_update(PCIExpressHost *e,
> > /*
> > * PCI express ECAM (Enhanced Configuration Address Mapping) format.
> > * AKA mmcfg address
> > - * bit 20 - 28: bus number
> > + * bit 20 - 27: bus number
> > * bit 15 - 19: device number
> > * bit 12 - 14: function number
> > * bit 0 - 11: offset in configuration space of a given device
>
> this is correct, or to be more precise:
> A[(20 + n – 1):20] and 1 <= n <= 8
Thank you for having a look! I'll create a patch for this and also a
second proposing a correction for PCIE_MMCFG_SIZE_MAX and repost!
Best regards,
Francisco
>
>
> > @@ -68,7 +68,7 @@ void pcie_host_mmcfg_update(PCIExpressHost *e,
> > #define PCIE_MMCFG_SIZE_MAX (1ULL << 29)
> > #define PCIE_MMCFG_SIZE_MIN (1ULL << 20)
> > #define PCIE_MMCFG_BUS_BIT 20
> > -#define PCIE_MMCFG_BUS_MASK 0x1ff
> > +#define PCIE_MMCFG_BUS_MASK 0xff
> > #define PCIE_MMCFG_DEVFN_BIT 12
> > #define PCIE_MMCFG_DEVFN_MASK 0xff
> > #define PCIE_MMCFG_CONFOFFSET_MASK 0xfff
> > --
> > 2.20.1
>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2022-04-11 22:17 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-04-11 19:38 [RFC PATCH v1 1/1] include/hw/pci/pcie_host: Correct PCIE_MMCFG_BUS_MASK Francisco Iglesias
2022-04-11 21:12 ` Michael S. Tsirkin
2022-04-11 22:16 ` Francisco Iglesias
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.