From: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
To: u-boot@lists.denx.de
Cc: Peter.Hoyes@arm.com, aford173@gmail.com, alice.guo@nxp.com,
andre.przywara@arm.com, andrey.zhizhikin@leica-geosystems.com,
ariel.dalessandro@collabora.com, bmeng.cn@gmail.com,
christian.gmeiner@gmail.com, christianshewitt@gmail.com,
festevam@gmail.com, iliev@ronetix.at, jagan@amarulasolutions.com,
jh80.chung@samsung.com, joe.hershberger@ni.com,
kettenis@openbsd.org, kever.yang@rock-chips.com,
kuldeep.singh@nxp.com, marcel.ziswiler@toradex.com,
marex@denx.de, michael@amarulasolutions.com,
michal.simek@xilinx.com, oliver.graute@kococonnector.com,
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sbabic@denx.de, simon.k.r.goldschmidt@gmail.com,
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tien.fong.chee@intel.com, uboot-imx@nxp.com,
vladimir.oltean@nxp.com, wd@denx.de, xypron.glpk@gmx.de,
ye.li@nxp.com
Subject: [PATCH v5 1/7] imx8m: add regs used by GPMI
Date: Tue, 12 Apr 2022 10:31:32 -0300 [thread overview]
Message-ID: <20220412133138.110815-2-ariel.dalessandro@collabora.com> (raw)
In-Reply-To: <20220412133138.110815-1-ariel.dalessandro@collabora.com>
From: Michael Trimarchi <michael@amarulasolutions.com>
Add regs used by GPMI
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
---
arch/arm/include/asm/arch-imx8m/imx-regs.h | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index 45d95a7c197..fb665412465 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -58,6 +58,13 @@
#define SRC_DDRC_RCR_ADDR 0x30391000
#define SRC_DDRC2_RCR_ADDR 0x30391004
+#define APBH_DMA_ARB_BASE_ADDR 0x33000000
+#define APBH_DMA_ARB_END_ADDR 0x33007FFF
+#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
+
+#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
+#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
+
#define DDRC_DDR_SS_GPR0 0x3d000000
#define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000))
#define DDR_CSD1_BASE_ADDR 0x40000000
--
2.34.1
next prev parent reply other threads:[~2022-04-12 13:33 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-12 13:31 [PATCH v5 0/7] imx8mn-smm-s2/pro: Add iMX8MN BSH SMM S2 boards Ariel D'Alessandro
2022-04-12 13:31 ` Ariel D'Alessandro [this message]
2022-04-12 18:47 ` [PATCH v5 1/7] imx8m: add regs used by GPMI sbabic
2022-04-12 13:31 ` [PATCH v5 2/7] imx8m: add init_nand_clk Ariel D'Alessandro
2022-04-12 18:46 ` sbabic
2022-04-12 13:31 ` [PATCH v5 3/7] phy: nxp-c45-tja11xx: Rename functions to be c45 tja11xx specific Ariel D'Alessandro
2022-04-12 18:46 ` sbabic
2022-04-12 13:31 ` [PATCH v5 4/7] iopoll: Extend read_poll_timeout macro to support variable parameters Ariel D'Alessandro
2022-04-12 18:45 ` sbabic
2022-04-12 13:31 ` [PATCH v5 5/7] net: phy: Add phy_modify() accessor Ariel D'Alessandro
2022-04-12 18:43 ` sbabic
2022-04-12 13:31 ` [PATCH v5 6/7] net: phy: nxp-tja11xx: Add NXP TJA11xx PHY driver Ariel D'Alessandro
2022-04-12 18:45 ` sbabic
2022-04-12 13:31 ` [PATCH v5 7/7] bsh: imx8mn-smm-s2/pro: Add iMX8MN BSH SMM S2 boards Ariel D'Alessandro
2022-04-12 18:46 ` sbabic
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