From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2EC6FC433F5 for ; Tue, 12 Apr 2022 16:13:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1355407AbiDLQPR (ORCPT ); Tue, 12 Apr 2022 12:15:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60558 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238419AbiDLQPR (ORCPT ); Tue, 12 Apr 2022 12:15:17 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 1D2074EA24; Tue, 12 Apr 2022 09:12:59 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CF6421424; Tue, 12 Apr 2022 09:12:58 -0700 (PDT) Received: from lpieralisi (unknown [10.57.8.134]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 23AE93F5A1; Tue, 12 Apr 2022 09:12:54 -0700 (PDT) Date: Tue, 12 Apr 2022 17:12:59 +0100 From: Lorenzo Pieralisi To: Baruch Siach , Bjorn Andersson , Andy Gross Cc: Selvam Sathappan Periakaruppan , Kathiravan T , Bjorn Helgaas , Rob Herring , Thierry Reding , Jonathan Hunter , Jingoo Han , Gustavo Pimentel , Robert Marko , Bryan O'Donoghue , linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-tegra@vger.kernel.org Subject: Re: [PATCH v6 0/3] PCI: IPQ6018 platform support Message-ID: <20220412161259.GA7109@lpieralisi> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.4 (2018-02-28) Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org On Mon, Feb 07, 2022 at 04:51:23PM +0200, Baruch Siach wrote: > This series adds support for the single PCIe lane on IPQ6018 SoCs. The code is > ported from downstream Codeaurora v5.4 kernel. The main difference from > downstream code is the split of PCIe registers configuration from .init to > .post_init, since it requires phy_power_on(). > > Tested on IPQ6010 based hardware. > > Changes in v6: > > * Drop DT patch applied to the qcom tree > > * Normalize driver changes subject line > > * Add a preparatory patch to rename PCIE_CAP_LINK1_VAL to PCIE_CAP_SLOT_VAL, > and define it using PCI_EXP_SLTCAP_* macros > > * Drop a vague comment about ASPM configuration > > * Add a comment about the source of delay periods > > Changes in v5: > > * Remove comments from qcom_pcie_init_2_9_0() (Bjorn Andersson) > > Changes in v4: > > * Drop applied DT bits > > * Add max-link-speed that was missing from the applied v2 patch > > * Rebase the driver on v5.16-rc3 > > Changes in v3: > > * Drop applied patches > > * Rely on generic code for speed setup > > * Drop unused macros > > * Formatting fixes > > Changes in v2: > > * Add patch moving GEN3_RELATED macros to a common header > > * Drop ATU configuration from pcie-qcom > > * Remove local definition of common registers > > * Use bulk clk and reset APIs > > * Remove msi-parent from device-tree > > Baruch Siach (2): > PCI: dwc: tegra: move GEN3_RELATED DBI register to common header > PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_* > > Selvam Sathappan Periakaruppan (1): > PCI: qcom: Add IPQ60xx support > > drivers/pci/controller/dwc/pcie-designware.h | 7 + > drivers/pci/controller/dwc/pcie-qcom.c | 155 ++++++++++++++++++- > drivers/pci/controller/dwc/pcie-tegra194.c | 6 - > 3 files changed, 160 insertions(+), 8 deletions(-) Hi Bjorn, Andy, any feedback on this series please ? Thanks, Lorenzo From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D78D0C433EF for ; Tue, 12 Apr 2022 16:14:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=nQUyb3FLX3m3y2J+Flsw9H0DAu3rlLHKfZp32pIWN8o=; b=htljNTpDJcQua5 4USyG81+H1XkbLt5gvy1ImnbOffDI5mmVTEhoH7wd/K1vcu8AZZsJ7VIN/1MM3+KBU0UoywGBHSB6 zZAiuV/ZuIYRenf8fMqt4E1Zod1oAyMMnoAHzWX74/VWEdXUXG+LOITO+6rm0gJ2tlAKl7fZBxA1K ksCXGLs4AGY9v+9j/EWCCk7OCoYtzNJrmd1p5eNzEsULFkajoDIu4Eg4ZrO/xyj9Ghz0gPsS39vaL +SCObq8ZuNyvjL1Rf3XW0oWvigxiak9BseNCH5ncNinFAE2B02W8/60B3t9aR246/Yn/pcLtUtK1J k7cRkLI7W/eJ9QELLuxw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1neJ8Z-00F3zt-Mw; Tue, 12 Apr 2022 16:13:03 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1neJ8W-00F3z8-Vn for linux-arm-kernel@lists.infradead.org; Tue, 12 Apr 2022 16:13:02 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CF6421424; Tue, 12 Apr 2022 09:12:58 -0700 (PDT) Received: from lpieralisi (unknown [10.57.8.134]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 23AE93F5A1; Tue, 12 Apr 2022 09:12:54 -0700 (PDT) Date: Tue, 12 Apr 2022 17:12:59 +0100 From: Lorenzo Pieralisi To: Baruch Siach , Bjorn Andersson , Andy Gross Cc: Selvam Sathappan Periakaruppan , Kathiravan T , Bjorn Helgaas , Rob Herring , Thierry Reding , Jonathan Hunter , Jingoo Han , Gustavo Pimentel , Robert Marko , Bryan O'Donoghue , linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-tegra@vger.kernel.org Subject: Re: [PATCH v6 0/3] PCI: IPQ6018 platform support Message-ID: <20220412161259.GA7109@lpieralisi> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.4 (2018-02-28) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220412_091301_123346_48FB60E7 X-CRM114-Status: GOOD ( 22.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Feb 07, 2022 at 04:51:23PM +0200, Baruch Siach wrote: > This series adds support for the single PCIe lane on IPQ6018 SoCs. The code is > ported from downstream Codeaurora v5.4 kernel. The main difference from > downstream code is the split of PCIe registers configuration from .init to > .post_init, since it requires phy_power_on(). > > Tested on IPQ6010 based hardware. > > Changes in v6: > > * Drop DT patch applied to the qcom tree > > * Normalize driver changes subject line > > * Add a preparatory patch to rename PCIE_CAP_LINK1_VAL to PCIE_CAP_SLOT_VAL, > and define it using PCI_EXP_SLTCAP_* macros > > * Drop a vague comment about ASPM configuration > > * Add a comment about the source of delay periods > > Changes in v5: > > * Remove comments from qcom_pcie_init_2_9_0() (Bjorn Andersson) > > Changes in v4: > > * Drop applied DT bits > > * Add max-link-speed that was missing from the applied v2 patch > > * Rebase the driver on v5.16-rc3 > > Changes in v3: > > * Drop applied patches > > * Rely on generic code for speed setup > > * Drop unused macros > > * Formatting fixes > > Changes in v2: > > * Add patch moving GEN3_RELATED macros to a common header > > * Drop ATU configuration from pcie-qcom > > * Remove local definition of common registers > > * Use bulk clk and reset APIs > > * Remove msi-parent from device-tree > > Baruch Siach (2): > PCI: dwc: tegra: move GEN3_RELATED DBI register to common header > PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_* > > Selvam Sathappan Periakaruppan (1): > PCI: qcom: Add IPQ60xx support > > drivers/pci/controller/dwc/pcie-designware.h | 7 + > drivers/pci/controller/dwc/pcie-qcom.c | 155 ++++++++++++++++++- > drivers/pci/controller/dwc/pcie-tegra194.c | 6 - > 3 files changed, 160 insertions(+), 8 deletions(-) Hi Bjorn, Andy, any feedback on this series please ? Thanks, Lorenzo _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel