From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EDB14C433EF for ; Tue, 12 Apr 2022 19:40:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351621AbiDLTmQ (ORCPT ); Tue, 12 Apr 2022 15:42:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52520 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1359106AbiDLTmI (ORCPT ); Tue, 12 Apr 2022 15:42:08 -0400 Received: from relay12.mail.gandi.net (relay12.mail.gandi.net [IPv6:2001:4b98:dc4:8::232]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 462124E38C; Tue, 12 Apr 2022 12:39:43 -0700 (PDT) Received: (Authenticated sender: miquel.raynal@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id CF97B200005; Tue, 12 Apr 2022 19:39:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1649792381; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=7PA5+rXzWjZ9Q6wg5gmJXLAXoBOOOTL5d3kZBJW8pVc=; b=DX3AluMX5UR8jEAVIysiQJKG9VhRRvJvfegI107e8lfNkgMLj92BVTvWHyQ3PFAK0+0YTh FXKp0JnoHFYoyHoS4/0jz6EAhHtDVxYmj2ecmn4klUvQTTMKqyToiWkuY9Pjox9TeFPHB5 Xxf/MKjDhCyd6R4KPjkG5GcxLejenn0okS4vDZoG063CjfT8QTkUbUWzF48Y1y/LZu25xe IFJLTB9G9lEDFJyukTamJ+9twFZx9m3hOBwYhKlaiPWpxRuNxKENf68wyB81hOvyVyqUGs UIo3P6G+QRuZoF+a9XdS9cF//Lke+3U9L6+8qCB/Kcy3fHU++L2YcyEA/21Oug== From: Miquel Raynal To: Magnus Damm , Gareth Williams , Phil Edworthy , Geert Uytterhoeven , Vinod Koul Cc: Miquel Raynal , linux-renesas-soc@vger.kernel.org, dmaengine@vger.kernel.org, Milan Stevanovic , Jimmy Lalande , Pascal Eberhard , Thomas Petazzoni , Herve Codina , Clement Leger , Stephen Boyd , Michael Turquette , linux-clk@vger.kernel.org, Viresh Kumar , Andy Shevchenko , Ilpo Jarvinen , Rob Herring , devicetree@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v10 1/9] dt-bindings: dmaengine: Introduce RZN1 dmamux bindings Date: Tue, 12 Apr 2022 21:39:28 +0200 Message-Id: <20220412193936.63355-2-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220412193936.63355-1-miquel.raynal@bootlin.com> References: <20220412193936.63355-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org The Renesas RZN1 DMA IP is based on a DW core, with eg. an additional dmamux register located in the system control area which can take up to 32 requests (16 per DMA controller). Each DMA channel can be wired to two different peripherals. Signed-off-by: Miquel Raynal Reviewed-by: Geert Uytterhoeven Reviewed-by: Rob Herring Acked-By: Vinod Koul --- .../bindings/dma/renesas,rzn1-dmamux.yaml | 51 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/renesas,rzn1-dmamux.yaml diff --git a/Documentation/devicetree/bindings/dma/renesas,rzn1-dmamux.yaml b/Documentation/devicetree/bindings/dma/renesas,rzn1-dmamux.yaml new file mode 100644 index 000000000000..d83013b0dd74 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/renesas,rzn1-dmamux.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/renesas,rzn1-dmamux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/N1 DMA mux + +maintainers: + - Miquel Raynal + +allOf: + - $ref: "dma-router.yaml#" + +properties: + compatible: + const: renesas,rzn1-dmamux + + reg: + maxItems: 1 + description: DMA mux first register offset within the system control parent. + + '#dma-cells': + const: 6 + description: + The first four cells are dedicated to the master DMA controller. The fifth + cell gives the DMA mux bit index that must be set starting from 0. The + sixth cell gives the binary value that must be written there, ie. 0 or 1. + + dma-masters: + minItems: 1 + maxItems: 2 + + dma-requests: + const: 32 + +required: + - reg + - dma-requests + +additionalProperties: false + +examples: + - | + dma-router@a0 { + compatible = "renesas,rzn1-dmamux"; + reg = <0xa0 4>; + #dma-cells = <6>; + dma-masters = <&dma0 &dma1>; + dma-requests = <32>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index fd768d43e048..120d3ae57a4b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19040,6 +19040,7 @@ SYNOPSYS DESIGNWARE DMAC DRIVER M: Viresh Kumar R: Andy Shevchenko S: Maintained +F: Documentation/devicetree/bindings/dma/renesas,rzn1-dmamux.yaml F: Documentation/devicetree/bindings/dma/snps,dma-spear1340.yaml F: drivers/dma/dw/ F: include/dt-bindings/dma/dw-dmac.h -- 2.27.0