All of lore.kernel.org
 help / color / mirror / Atom feed
From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
To: intel-gfx@lists.freedesktop.org,
	Matt Roper <matthew.d.roper@intel.com>,
	daniele.ceraolospurio@intel.com, john.c.harrison@intel.com,
	vinay.belgaumkar@intel.com
Subject: [Intel-gfx] [PATCH 10/10] drm/i915/dg2: Enable Wa_22012727170/Wa_22012727685
Date: Wed, 13 Apr 2022 12:27:30 -0700	[thread overview]
Message-ID: <20220413192730.3608660-11-umesh.nerlige.ramappa@intel.com> (raw)
In-Reply-To: <20220413192730.3608660-1-umesh.nerlige.ramappa@intel.com>

From: John Harrison <John.C.Harrison@Intel.com>

The above two workaronuds regarding context isolation are implemented
by GuC. The KMD just needs to enable them.

v2: Use dg2 stepping for ctx isolation WA (Umesh)
v3: Rebase (Umesh)
v4: Fix WA comments (Daniele)
v5: Drop Wa_22012727685 for G10 as it is n/a
v6: Undo v5 change since the G10 condition is needed

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_guc.c      | 8 ++++++++
 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 1 +
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 228070e31ef0..2c4ad4a65089 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -319,6 +319,14 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
 	    IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0))
 		flags |= GUC_WA_RCS_RESET_BEFORE_RC6;
 
+	/*
+	 * Wa_22012727170:dg2_g10[a0-c0), dg2_g11[a0..)
+	 * Wa_22012727685:dg2_g11[a0..)
+	 */
+	if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) ||
+	    IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_FOREVER))
+		flags |= GUC_WA_CONTEXT_ISOLATION;
+
 	return flags;
 }
 
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index e389a3a041a2..42cb7a9a6199 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -101,6 +101,7 @@
 #define   GUC_WA_GAM_CREDITS		BIT(10)
 #define   GUC_WA_DUAL_QUEUE		BIT(11)
 #define   GUC_WA_RCS_RESET_BEFORE_RC6	BIT(13)
+#define   GUC_WA_CONTEXT_ISOLATION	BIT(15)
 #define   GUC_WA_PRE_PARSER		BIT(14)
 #define   GUC_WA_HOLD_CCS_SWITCHOUT	BIT(17)
 #define   GUC_WA_POLLCS			BIT(18)
-- 
2.35.1


  parent reply	other threads:[~2022-04-13 19:27 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-13 19:27 [Intel-gfx] [PATCH 00/10] Enable compute and related WAs for DG2 Umesh Nerlige Ramappa
2022-04-13 19:27 ` [Intel-gfx] [PATCH 01/10] drm/i915/guc: Update context registration to new GuC API Umesh Nerlige Ramappa
2022-04-13 19:27 ` [Intel-gfx] [PATCH 02/10] drm/i915/guc: Update scheduling policies " Umesh Nerlige Ramappa
2022-04-13 19:27 ` [Intel-gfx] [PATCH 03/10] drm/i915/guc: Update to GuC version 70.1.1 Umesh Nerlige Ramappa
2022-04-13 19:27 ` [Intel-gfx] [PATCH 04/10] drm/i915/xehp: Add compute engine ABI Umesh Nerlige Ramappa
2022-04-13 19:27 ` [Intel-gfx] [PATCH 05/10] drm/i915: Xe_HP SDV and DG2 have 4 CCS engines Umesh Nerlige Ramappa
2022-04-13 19:27 ` [Intel-gfx] [PATCH 06/10] drm/i915: Add Wa_22011802037 force cs halt Umesh Nerlige Ramappa
2022-04-15  0:09   ` John Harrison
2022-04-13 19:27 ` [Intel-gfx] [PATCH 07/10] drm/i915/guc: Enable GuC based workarounds for DG2 Umesh Nerlige Ramappa
2022-04-15 20:29   ` Ceraolo Spurio, Daniele
2022-04-13 19:27 ` [Intel-gfx] [PATCH 08/10] drm/i915/guc: Apply Wa_16011777198 Umesh Nerlige Ramappa
2022-04-15  0:15   ` John Harrison
2022-04-13 19:27 ` [Intel-gfx] [PATCH 09/10] drm/i915/dg2: Enable Wa_14014475959 - RCS / CCS context exit Umesh Nerlige Ramappa
2022-04-15  0:21   ` John Harrison
2022-04-15  4:11   ` Matthew Brost
2022-04-13 19:27 ` Umesh Nerlige Ramappa [this message]
2022-04-15  0:22   ` [Intel-gfx] [PATCH 10/10] drm/i915/dg2: Enable Wa_22012727170/Wa_22012727685 John Harrison
2022-04-15  0:28     ` Umesh Nerlige Ramappa
2022-04-14  1:40 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable compute and related WAs for DG2 Patchwork
2022-04-14  1:40 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-04-14  2:02 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20220413192730.3608660-11-umesh.nerlige.ramappa@intel.com \
    --to=umesh.nerlige.ramappa@intel.com \
    --cc=daniele.ceraolospurio@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=john.c.harrison@intel.com \
    --cc=matthew.d.roper@intel.com \
    --cc=vinay.belgaumkar@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.